Lines Matching +full:adc +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
24 #include "adau-utils.h"
125 static const DECLARE_TLV_DB_MINMAX(adau1372_digital_tlv, -9563, 0);
126 static const DECLARE_TLV_DB_SCALE(adau1372_pga_tlv, -1200, 75, 0);
176 SOC_SINGLE_TLV("ADC 0 Capture Volume", ADAU1372_REG_ADC_VOL(0),
178 SOC_SINGLE_TLV("ADC 1 Capture Volume", ADAU1372_REG_ADC_VOL(1),
180 SOC_SINGLE_TLV("ADC 2 Capture Volume", ADAU1372_REG_ADC_VOL(2),
182 SOC_SINGLE_TLV("ADC 3 Capture Volume", ADAU1372_REG_ADC_VOL(3),
184 SOC_SINGLE("ADC 0 Capture Switch", ADAU1372_REG_ADC_CTRL0, 3, 1, 1),
185 SOC_SINGLE("ADC 1 Capture Switch", ADAU1372_REG_ADC_CTRL0, 4, 1, 1),
186 SOC_SINGLE("ADC 2 Capture Switch", ADAU1372_REG_ADC_CTRL1, 3, 1, 1),
187 SOC_SINGLE("ADC 3 Capture Switch", ADAU1372_REG_ADC_CTRL1, 4, 1, 1),
189 SOC_ENUM("ADC 0+1 High-Pass-Filter", adau1372_hpf0_1_enum),
190 SOC_ENUM("ADC 2+3 High-Pass-Filter", adau1372_hpf2_3_enum),
224 SOC_ENUM("ADC 0+1 Bias", adau1372_bias_adc0_1_enum),
225 SOC_ENUM("ADC 2+3 Bias", adau1372_bias_adc2_3_enum),
230 "ADC",
238 SOC_DAPM_ENUM("Decimator 0+1 Capture Mux", adau1372_decimator0_1_mux_enum);
244 SOC_DAPM_ENUM("Decimator 2+3 Capture Mux", adau1372_decimator2_3_mux_enum);
267 SOC_DAPM_ENUM("Output ASRC0 Capture Mux", adau1372_asrco0_mux_enum);
269 SOC_DAPM_ENUM("Output ASRC1 Capture Mux", adau1372_asrco1_mux_enum);
271 SOC_DAPM_ENUM("Output ASRC2 Capture Mux", adau1372_asrco2_mux_enum);
273 SOC_DAPM_ENUM("Output ASRC3 Capture Mux", adau1372_asrco3_mux_enum);
312 SOC_DAPM_ENUM("Serial Output 0 Capture Mux", adau1372_sout0_mux_enum);
314 SOC_DAPM_ENUM("Serial Output 1 Capture Mux", adau1372_sout1_mux_enum);
316 SOC_DAPM_ENUM("Serial Output 2 Capture Mux", adau1372_sout2_mux_enum);
318 SOC_DAPM_ENUM("Serial Output 3 Capture Mux", adau1372_sout3_mux_enum);
320 SOC_DAPM_ENUM("Serial Output 4 Capture Mux", adau1372_sout4_mux_enum);
322 SOC_DAPM_ENUM("Serial Output 5 Capture Mux", adau1372_sout5_mux_enum);
324 SOC_DAPM_ENUM("Serial Output 6 Capture Mux", adau1372_sout6_mux_enum);
326 SOC_DAPM_ENUM("Serial Output 7 Capture Mux", adau1372_sout7_mux_enum);
339 SOC_DAPM_ENUM("Input ASRC Playback Mux", adau1372_asrci_mux_enum);
356 SOC_DAPM_ENUM("DAC 0 Playback Mux", adau1372_dac0_mux_enum);
358 SOC_DAPM_ENUM("DAC 1 Playback Mux", adau1372_dac1_mux_enum);
389 SND_SOC_DAPM_MUX("Decimator0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
390 SND_SOC_DAPM_MUX("Decimator1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator0_1_mux_control),
391 SND_SOC_DAPM_MUX("Decimator2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
392 SND_SOC_DAPM_MUX("Decimator3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_decimator2_3_mux_control),
394 SND_SOC_DAPM_MUX("Output ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco0_mux_control),
395 SND_SOC_DAPM_MUX("Output ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco1_mux_control),
396 SND_SOC_DAPM_MUX("Output ASRC2 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco2_mux_control),
397 SND_SOC_DAPM_MUX("Output ASRC3 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrco3_mux_control),
398 SND_SOC_DAPM_MUX("Serial Output 0 Capture Mux", SND_SOC_NOPM, 0, 0,
400 SND_SOC_DAPM_MUX("Serial Output 1 Capture Mux", SND_SOC_NOPM, 0, 0,
402 SND_SOC_DAPM_MUX("Serial Output 2 Capture Mux", SND_SOC_NOPM, 0, 0,
404 SND_SOC_DAPM_MUX("Serial Output 3 Capture Mux", SND_SOC_NOPM, 0, 0,
406 SND_SOC_DAPM_MUX("Serial Output 4 Capture Mux", SND_SOC_NOPM, 0, 0,
408 SND_SOC_DAPM_MUX("Serial Output 5 Capture Mux", SND_SOC_NOPM, 0, 0,
410 SND_SOC_DAPM_MUX("Serial Output 6 Capture Mux", SND_SOC_NOPM, 0, 0,
412 SND_SOC_DAPM_MUX("Serial Output 7 Capture Mux", SND_SOC_NOPM, 0, 0,
441 SND_SOC_DAPM_MUX("Input ASRC0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
442 SND_SOC_DAPM_MUX("Input ASRC1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_asrci_mux_control),
444 SND_SOC_DAPM_MUX("DAC 0 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac0_mux_control),
445 SND_SOC_DAPM_MUX("DAC 1 Mux", SND_SOC_NOPM, 0, 0, &adau1372_dac1_mux_control),
460 { "Serial Output " #x " Capture Mux", "Output ASRC0", "Output ASRC0 Mux" }, \
461 { "Serial Output " #x " Capture Mux", "Output ASRC1", "Output ASRC1 Mux" }, \
462 { "Serial Output " #x " Capture Mux", "Output ASRC2", "Output ASRC2 Mux" }, \
463 { "Serial Output " #x " Capture Mux", "Output ASRC3", "Output ASRC3 Mux" }, \
464 { "Serial Output " #x " Capture Mux", "Serial Input 0", "Serial Input 0" }, \
465 { "Serial Output " #x " Capture Mux", "Serial Input 1", "Serial Input 1" }, \
466 { "Serial Output " #x " Capture Mux", "Serial Input 2", "Serial Input 2" }, \
467 { "Serial Output " #x " Capture Mux", "Serial Input 3", "Serial Input 3" }, \
468 { "Serial Output " #x " Capture Mux", "Serial Input 4", "Serial Input 4" }, \
469 { "Serial Output " #x " Capture Mux", "Serial Input 5", "Serial Input 5" }, \
470 { "Serial Output " #x " Capture Mux", "Serial Input 6", "Serial Input 6" }, \
471 { "Serial Output " #x " Capture Mux", "Serial Input 7", "Serial Input 7" }, \
472 { "Serial Output " #x, NULL, "Serial Output " #x " Capture Mux" }, \
476 { "Output ASRC" #x " Mux", "Decimator0", "Decimator0 Mux" }, \
477 { "Output ASRC" #x " Mux", "Decimator1", "Decimator1 Mux" }, \
478 { "Output ASRC" #x " Mux", "Decimator2", "Decimator2 Mux" }, \
479 { "Output ASRC" #x " Mux", "Decimator3", "Decimator3 Mux" }
492 { "Decimator0 Mux", "ADC", "ADC0" },
493 { "Decimator1 Mux", "ADC", "ADC1" },
494 { "Decimator2 Mux", "ADC", "ADC2" },
495 { "Decimator3 Mux", "ADC", "ADC3" },
497 { "Decimator0 Mux", "DMIC", "DMIC0_1" },
498 { "Decimator1 Mux", "DMIC", "DMIC0_1" },
499 { "Decimator2 Mux", "DMIC", "DMIC2_3" },
500 { "Decimator3 Mux", "DMIC", "DMIC2_3" },
502 { "Decimator0 Mux", NULL, "ADC0 Filter" },
503 { "Decimator1 Mux", NULL, "ADC1 Filter" },
504 { "Decimator2 Mux", NULL, "ADC2 Filter" },
505 { "Decimator3 Mux", NULL, "ADC3 Filter" },
507 { "Output ASRC0 Mux", NULL, "Output ASRC Supply" },
508 { "Output ASRC1 Mux", NULL, "Output ASRC Supply" },
509 { "Output ASRC2 Mux", NULL, "Output ASRC Supply" },
510 { "Output ASRC3 Mux", NULL, "Output ASRC Supply" },
511 { "Output ASRC0 Mux", NULL, "Output ASRC0 Decimator" },
512 { "Output ASRC1 Mux", NULL, "Output ASRC1 Decimator" },
513 { "Output ASRC2 Mux", NULL, "Output ASRC2 Decimator" },
514 { "Output ASRC3 Mux", NULL, "Output ASRC3 Decimator" },
539 { "Input ASRC0 Mux", "Serial Input 0+1", "Serial Input 0" },
540 { "Input ASRC1 Mux", "Serial Input 0+1", "Serial Input 1" },
541 { "Input ASRC0 Mux", "Serial Input 2+3", "Serial Input 2" },
542 { "Input ASRC1 Mux", "Serial Input 2+3", "Serial Input 3" },
543 { "Input ASRC0 Mux", "Serial Input 4+5", "Serial Input 4" },
544 { "Input ASRC1 Mux", "Serial Input 4+5", "Serial Input 5" },
545 { "Input ASRC0 Mux", "Serial Input 6+7", "Serial Input 6" },
546 { "Input ASRC1 Mux", "Serial Input 6+7", "Serial Input 7" },
547 { "Input ASRC0 Mux", NULL, "Input ASRC Supply" },
548 { "Input ASRC1 Mux", NULL, "Input ASRC Supply" },
549 { "Input ASRC0 Mux", NULL, "Input ASRC0 Interpolator" },
550 { "Input ASRC1 Mux", NULL, "Input ASRC1 Interpolator" },
552 { "DAC 0 Mux", "Input ASRC0", "Input ASRC0 Mux" },
553 { "DAC 0 Mux", "Input ASRC1", "Input ASRC1 Mux" },
554 { "DAC 1 Mux", "Input ASRC0", "Input ASRC0 Mux" },
555 { "DAC 1 Mux", "Input ASRC1", "Input ASRC1 Mux" },
557 { "DAC0", NULL, "DAC 0 Mux" },
558 { "DAC1", NULL, "DAC 1 Mux" },
581 adau1372->clock_provider = true; in adau1372_set_dai_fmt()
585 adau1372->clock_provider = false; in adau1372_set_dai_fmt()
588 return -EINVAL; in adau1372_set_dai_fmt()
629 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_DELAY_MASK, sai0); in adau1372_set_dai_fmt()
630 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, in adau1372_set_dai_fmt()
652 return -EINVAL; in adau1372_hw_params()
656 slot_width = adau1372->slot_width; in adau1372_hw_params()
669 return -EINVAL; in adau1372_hw_params()
672 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_FS_MASK, sai0); in adau1372_hw_params()
673 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLKRATE, sai1); in adau1372_hw_params()
687 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, in adau1372_set_tdm_slot()
689 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2; in adau1372_set_tdm_slot()
690 adau1372->slot_width = 0; in adau1372_set_tdm_slot()
696 return -EINVAL; in adau1372_set_tdm_slot()
707 return -EINVAL; in adau1372_set_tdm_slot()
713 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2; in adau1372_set_tdm_slot()
717 if (adau1372->clock_provider) in adau1372_set_tdm_slot()
718 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4_MASTER; in adau1372_set_tdm_slot()
720 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4; in adau1372_set_tdm_slot()
724 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM8; in adau1372_set_tdm_slot()
727 return -EINVAL; in adau1372_set_tdm_slot()
730 adau1372->slot_width = width; in adau1372_set_tdm_slot()
732 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_SAI_MASK, sai0); in adau1372_set_tdm_slot()
733 regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLK_TDMC, sai1); in adau1372_set_tdm_slot()
736 regmap_write(adau1372->regmap, ADAU1372_REG_SOUT_CTRL, ~tx_mask); in adau1372_set_tdm_slot()
751 return regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_TDM_TS, sai1); in adau1372_set_tristate()
758 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, in adau1372_startup()
759 &adau1372->rate_constraints); in adau1372_startup()
769 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL, in adau1372_enable_pll()
774 ret = regmap_read(adau1372->regmap, ADAU1372_REG_PLL(5), &val); in adau1372_enable_pll()
781 dev_err(adau1372->dev, "Failed to lock PLL\n"); in adau1372_enable_pll()
786 if (adau1372->enabled == enable) in adau1372_set_power()
792 clk_prepare_enable(adau1372->mclk); in adau1372_set_power()
793 if (adau1372->pd_gpio) in adau1372_set_power()
794 gpiod_set_value(adau1372->pd_gpio, 0); in adau1372_set_power()
796 if (adau1372->switch_mode) in adau1372_set_power()
797 adau1372->switch_mode(adau1372->dev); in adau1372_set_power()
799 regcache_cache_only(adau1372->regmap, false); in adau1372_set_power()
805 if (adau1372->use_pll) { in adau1372_set_power()
810 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL, in adau1372_set_power()
812 regcache_sync(adau1372->regmap); in adau1372_set_power()
814 if (adau1372->pd_gpio) { in adau1372_set_power()
820 gpiod_set_value(adau1372->pd_gpio, 1); in adau1372_set_power()
821 regcache_mark_dirty(adau1372->regmap); in adau1372_set_power()
823 regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL, in adau1372_set_power()
826 clk_disable_unprepare(adau1372->mclk); in adau1372_set_power()
827 regcache_cache_only(adau1372->regmap, true); in adau1372_set_power()
830 adau1372->enabled = enable; in adau1372_set_power()
910 regmap_write(adau1372->regmap, ADAU1372_REG_PLL(i), regs[i]); in adau1372_setup_pll()
928 return -ENOMEM; in adau1372_probe()
930 adau1372->mclk = devm_clk_get(dev, "mclk"); in adau1372_probe()
931 if (IS_ERR(adau1372->mclk)) in adau1372_probe()
932 return PTR_ERR(adau1372->mclk); in adau1372_probe()
934 adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH); in adau1372_probe()
935 if (IS_ERR(adau1372->pd_gpio)) in adau1372_probe()
936 return PTR_ERR(adau1372->pd_gpio); in adau1372_probe()
938 adau1372->regmap = regmap; in adau1372_probe()
939 adau1372->switch_mode = switch_mode; in adau1372_probe()
940 adau1372->dev = dev; in adau1372_probe()
941 adau1372->rate_constraints.list = adau1372_rates; in adau1372_probe()
942 adau1372->rate_constraints.count = ARRAY_SIZE(adau1372_rates); in adau1372_probe()
943 adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2; in adau1372_probe()
952 rate = clk_get_rate(adau1372->mclk); in adau1372_probe()
966 adau1372->use_pll = true; in adau1372_probe()
979 * No pinctrl support yet, put the multi-purpose pins in the most in adau1372_probe()
1064 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");