Lines Matching +full:0 +full:x1240000

10 #define ACP_DEVICE_ID 0x15E2
11 #define ACP63_REG_START		0x1240000
12 #define ACP63_REG_END		0x1250200
15 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK	0x00010001
17 #define ACP_PGFSM_CNTL_POWER_OFF_MASK	0
19 #define ACP_POWERED_ON			0
24 #define ACP_ERROR_MASK 0x20000000
25 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
26 #define PDM_DMA_STAT 0x10
28 #define PDM_DMA_INTR_MASK	0x10000
34 #define ACP_PDM_DISABLE		0
40 #define ACP_SRAM_PTE_OFFSET	0x03800000
42 #define PDM_PTE_OFFSET		0
43 #define PDM_MEM_WINDOW_START	0x4000000
92 #define ACP63_PDM_DEV_CONFIG		BIT(0)
101 #define ACP63_SDW_PDM_DEV_CONFIG	GENMASK(1, 0)
106 #define ACP_AUDIO0_TX_THRESHOLD		0x1c
107 #define ACP_AUDIO1_TX_THRESHOLD		0x1a
108 #define ACP_AUDIO2_TX_THRESHOLD		0x18
109 #define ACP_AUDIO0_RX_THRESHOLD		0x1b
110 #define ACP_AUDIO1_RX_THRESHOLD		0x19
111 #define ACP_AUDIO2_RX_THRESHOLD		0x17
114 #define ACP_SDW_DMA_IRQ_MASK		0x1F800000
115 #define ACP_P1_SDW_DMA_IRQ_MASK		0x60
124  * 0 (SDW0_AUDIO0_TX)	28
138  * 0 (SDW1_AUDIO1_TX)	6
145 #define SDW0_MEM_WINDOW_START	0x4800000
146 #define ACP_SDW_SRAM_PTE_OFFSET	0x03800400
147 #define SDW0_PTE_OFFSET		0x400
148 #define SDW_FIFO_SIZE		0x100
149 #define SDW_DMA_SIZE		0x40
150 #define ACP_SDW0_FIFO_OFFSET	0x100
151 #define ACP_SDW_PTE_OFFSET	0x100
152 #define SDW_FIFO_OFFSET		0x100
153 #define SDW_PTE_OFFSET(i)	(SDW0_PTE_OFFSET + ((i) * 0x600))
154 #define ACP_SDW_FIFO_OFFSET(i)	(ACP_SDW0_FIFO_OFFSET + ((i) * 0x500))
155 #define SDW_MEM_WINDOW_START(i)	(SDW0_MEM_WINDOW_START + ((i) * 0xC0000))
170 	ACP_CONFIG_0 = 0,
189 	ACP_SDW0_AUDIO0_TX = 0,
263  * @sdw0_dev_index: SoundWire Manager-0 platform device index