Lines Matching +full:0 +full:x500
23 #define ACP63_DEV 0x63
24 #define ACP70_DEV 0x70
26 #define DMIC_INSTANCE 0x00
27 #define I2S_SP_INSTANCE 0x01
28 #define I2S_BT_INSTANCE 0x02
29 #define I2S_HS_INSTANCE 0x03
31 #define MEM_WINDOW_START 0x4080000
33 #define ACP_I2S_REG_START 0x1242400
34 #define ACP_I2S_REG_END 0x1242810
35 #define ACP3x_I2STDM_REG_START 0x1242400
36 #define ACP3x_I2STDM_REG_END 0x1242410
37 #define ACP3x_BT_TDM_REG_START 0x1242800
38 #define ACP3x_BT_TDM_REG_END 0x1242810
48 #define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
49 #define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
50 #define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
51 #define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
52 #define ACP_SRAM_PDM_PTE_OFFSET 0x400
53 #define ACP_SRAM_HS_PB_PTE_OFFSET 0x500
54 #define ACP_SRAM_HS_CP_PTE_OFFSET 0x600
55 #define PAGE_SIZE_4K_ENABLE 0x2
57 #define I2S_SP_TX_MEM_WINDOW_START 0x4000000
58 #define I2S_SP_RX_MEM_WINDOW_START 0x4020000
59 #define I2S_BT_TX_MEM_WINDOW_START 0x4040000
60 #define I2S_BT_RX_MEM_WINDOW_START 0x4060000
61 #define I2S_HS_TX_MEM_WINDOW_START 0x40A0000
62 #define I2S_HS_RX_MEM_WINDOW_START 0x40C0000
64 #define SP_PB_FIFO_ADDR_OFFSET 0x500
65 #define SP_CAPT_FIFO_ADDR_OFFSET 0x700
66 #define BT_PB_FIFO_ADDR_OFFSET 0x900
67 #define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
68 #define HS_PB_FIFO_ADDR_OFFSET 0xD00
69 #define HS_CAPT_FIFO_ADDR_OFFSET 0xF00
81 #define FIFO_SIZE 0x100
82 #define DMA_SIZE 0x40
83 #define FRM_LEN 0x100
85 #define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
90 #define TDM_DISABLE 0
92 #define SLOT_WIDTH_8 0x8
93 #define SLOT_WIDTH_16 0x10
94 #define SLOT_WIDTH_24 0x18
95 #define SLOT_WIDTH_32 0x20
97 #define ACP6X_PGFSM_CONTROL 0x1024
98 #define ACP6X_PGFSM_STATUS 0x1028
106 #define ACP_SOFT_RST_DONE_MASK 0x00010001
108 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0xffffffff
109 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
110 #define ACP_PGFSM_STATUS_MASK 0x03
111 #define ACP_POWERED_ON 0x00
112 #define ACP_POWER_ON_IN_PROGRESS 0x01
113 #define ACP_POWERED_OFF 0x02
114 #define ACP_POWER_OFF_IN_PROGRESS 0x03
116 #define ACP_ERROR_MASK 0x20000000
117 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xffffffff
123 #define PDM_DMA_STAT 0x10
124 #define PDM_DMA_INTR_MASK 0x10000
125 #define PDM_DEC_64 0x2
126 #define PDM_CLK_FREQ_MASK 0x07
127 #define PDM_MISC_CTRL_MASK 0x10
128 #define PDM_ENABLE 0x01
129 #define PDM_DISABLE 0x00
130 #define DMA_EN_MASK 0x02
133 #define ACP_REGION2_OFFSET 0x02000000
199 ACP_CONFIG_0 = 0,
247 u64 byte_count = 0, low = 0, high = 0; in acp_get_byte_count()