1 // SPDX-License-Identifier: GPL-2.0
3  * Library implementing the most common irq chip callback functions
22  * irq_gc_noop - NOOP function
31  * irq_gc_mask_disable_reg - Mask chip via disable register
34  * Chip has separate enable/disable registers instead of a single mask
41 	u32 mask = d->mask;  in irq_gc_mask_disable_reg()
44 	irq_reg_writel(gc, mask, ct->regs.disable);  in irq_gc_mask_disable_reg()
45 	*ct->mask_cache &= ~mask;  in irq_gc_mask_disable_reg()
51  * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
54  * Chip has a single mask register. Values of this register are cached
55  * and protected by gc->lock
61 	u32 mask = d->mask;  in irq_gc_mask_set_bit()
64 	*ct->mask_cache |= mask;  in irq_gc_mask_set_bit()
65 	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);  in irq_gc_mask_set_bit()
71  * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
74  * Chip has a single mask register. Values of this register are cached
75  * and protected by gc->lock
81 	u32 mask = d->mask;  in irq_gc_mask_clr_bit()
84 	*ct->mask_cache &= ~mask;  in irq_gc_mask_clr_bit()
85 	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);  in irq_gc_mask_clr_bit()
91  * irq_gc_unmask_enable_reg - Unmask chip via enable register
94  * Chip has separate enable/disable registers instead of a single mask
101 	u32 mask = d->mask;  in irq_gc_unmask_enable_reg()
104 	irq_reg_writel(gc, mask, ct->regs.enable);  in irq_gc_unmask_enable_reg()
105 	*ct->mask_cache |= mask;  in irq_gc_unmask_enable_reg()
111  * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
118 	u32 mask = d->mask;  in irq_gc_ack_set_bit()
121 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_ack_set_bit()
127  * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
134 	u32 mask = ~d->mask;  in irq_gc_ack_clr_bit()
137 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_ack_clr_bit()
142  * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
157 	u32 mask = d->mask;  in irq_gc_mask_disable_and_ack_set()
160 	irq_reg_writel(gc, mask, ct->regs.disable);  in irq_gc_mask_disable_and_ack_set()
161 	*ct->mask_cache &= ~mask;  in irq_gc_mask_disable_and_ack_set()
162 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_mask_disable_and_ack_set()
167  * irq_gc_eoi - EOI interrupt
174 	u32 mask = d->mask;  in irq_gc_eoi()
177 	irq_reg_writel(gc, mask, ct->regs.eoi);  in irq_gc_eoi()
182  * irq_gc_set_wake - Set/clr wake bit for an interrupt
193 	u32 mask = d->mask;  in irq_gc_set_wake()
195 	if (!(mask & gc->wake_enabled))  in irq_gc_set_wake()
196 		return -EINVAL;  in irq_gc_set_wake()
200 		gc->wake_active |= mask;  in irq_gc_set_wake()
202 		gc->wake_active &= ~mask;  in irq_gc_set_wake()
222 	struct irq_chip_type *ct = gc->chip_types;  in irq_init_generic_chip()
225 	raw_spin_lock_init(&gc->lock);  in irq_init_generic_chip()
226 	gc->num_ct = num_ct;  in irq_init_generic_chip()
227 	gc->irq_base = irq_base;  in irq_init_generic_chip()
228 	gc->reg_base = reg_base;  in irq_init_generic_chip()
230 		ct[i].chip.name = name;  in irq_init_generic_chip()
231 	gc->chip_types->handler = handler;  in irq_init_generic_chip()
235  * irq_alloc_generic_chip - Allocate a generic chip and initialize it
236  * @name:	Name of the irq chip
238  * @irq_base:	Interrupt base nr for this chip
240  * @handler:	Default flow handler associated with this chip
242  * Returns an initialized irq_chip_generic structure. The chip defaults
263 	struct irq_chip_type *ct = gc->chip_types;  in irq_gc_init_mask_cache()
264 	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;  in irq_gc_init_mask_cache()
267 	for (i = 0; i < gc->num_ct; i++) {  in irq_gc_init_mask_cache()
279  * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
281  * @irqs_per_chip:	Number of interrupts each chip handles (max 32)
283  * @name:		Name of the irq chip
287  * @gcflags:		Generic chip specific setup flags
304 	if (d->gc)  in __irq_alloc_domain_generic_chips()
305 		return -EBUSY;  in __irq_alloc_domain_generic_chips()
307 	numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);  in __irq_alloc_domain_generic_chips()
309 		return -EINVAL;  in __irq_alloc_domain_generic_chips()
311 	/* Allocate a pointer, generic chip and chiptypes for each chip */  in __irq_alloc_domain_generic_chips()
318 		return -ENOMEM;  in __irq_alloc_domain_generic_chips()
319 	dgc->irqs_per_chip = irqs_per_chip;  in __irq_alloc_domain_generic_chips()
320 	dgc->num_chips = numchips;  in __irq_alloc_domain_generic_chips()
321 	dgc->irq_flags_to_set = set;  in __irq_alloc_domain_generic_chips()
322 	dgc->irq_flags_to_clear = clr;  in __irq_alloc_domain_generic_chips()
323 	dgc->gc_flags = gcflags;  in __irq_alloc_domain_generic_chips()
324 	d->gc = dgc;  in __irq_alloc_domain_generic_chips()
326 	/* Calc pointer to the first generic chip */  in __irq_alloc_domain_generic_chips()
329 		/* Store the pointer to the generic chip */  in __irq_alloc_domain_generic_chips()
330 		dgc->gc[i] = gc = tmp;  in __irq_alloc_domain_generic_chips()
334 		gc->domain = d;  in __irq_alloc_domain_generic_chips()
336 			gc->reg_readl = &irq_readl_be;  in __irq_alloc_domain_generic_chips()
337 			gc->reg_writel = &irq_writel_be;  in __irq_alloc_domain_generic_chips()
341 		list_add_tail(&gc->list, &gc_list);  in __irq_alloc_domain_generic_chips()
343 		/* Calc pointer to the next generic chip */  in __irq_alloc_domain_generic_chips()
353 	struct irq_domain_chip_generic *dgc = d->gc;  in __irq_get_domain_generic_chip()
357 		return ERR_PTR(-ENODEV);  in __irq_get_domain_generic_chip()
358 	idx = hw_irq / dgc->irqs_per_chip;  in __irq_get_domain_generic_chip()
359 	if (idx >= dgc->num_chips)  in __irq_get_domain_generic_chip()
360 		return ERR_PTR(-EINVAL);  in __irq_get_domain_generic_chip()
361 	return dgc->gc[idx];  in __irq_get_domain_generic_chip()
365  * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
379  * Separate lockdep classes for interrupt chip which can nest irq_desc
386  * irq_map_generic_chip - Map a generic chip for an irq domain
392 	struct irq_domain_chip_generic *dgc = d->gc;  in irq_map_generic_chip()
395 	struct irq_chip *chip;  in irq_map_generic_chip()  local
403 	idx = hw_irq % dgc->irqs_per_chip;  in irq_map_generic_chip()
405 	if (test_bit(idx, &gc->unused))  in irq_map_generic_chip()
406 		return -ENOTSUPP;  in irq_map_generic_chip()
408 	if (test_bit(idx, &gc->installed))  in irq_map_generic_chip()
409 		return -EBUSY;  in irq_map_generic_chip()
411 	ct = gc->chip_types;  in irq_map_generic_chip()
412 	chip = &ct->chip;  in irq_map_generic_chip()
414 	/* We only init the cache for the first mapping of a generic chip */  in irq_map_generic_chip()
415 	if (!gc->installed) {  in irq_map_generic_chip()
416 		raw_spin_lock_irqsave(&gc->lock, flags);  in irq_map_generic_chip()
417 		irq_gc_init_mask_cache(gc, dgc->gc_flags);  in irq_map_generic_chip()
418 		raw_spin_unlock_irqrestore(&gc->lock, flags);  in irq_map_generic_chip()
422 	set_bit(idx, &gc->installed);  in irq_map_generic_chip()
424 	if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)  in irq_map_generic_chip()
428 	if (chip->irq_calc_mask)  in irq_map_generic_chip()
429 		chip->irq_calc_mask(data);  in irq_map_generic_chip()
431 		data->mask = 1 << idx;  in irq_map_generic_chip()
433 	irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);  in irq_map_generic_chip()
434 	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);  in irq_map_generic_chip()
441 	struct irq_domain_chip_generic *dgc = d->gc;  in irq_unmap_generic_chip()
442 	unsigned int hw_irq = data->hwirq;  in irq_unmap_generic_chip()
450 	irq_idx = hw_irq % dgc->irqs_per_chip;  in irq_unmap_generic_chip()
452 	clear_bit(irq_idx, &gc->installed);  in irq_unmap_generic_chip()
466  * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
467  * @gc:		Generic irq chip holding all data
468  * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
473  * Set up max. 32 interrupts starting from gc->irq_base. Note, this
481 	struct irq_chip_type *ct = gc->chip_types;  in irq_setup_generic_chip()
482 	struct irq_chip *chip = &ct->chip;  in irq_setup_generic_chip()  local
486 	list_add_tail(&gc->list, &gc_list);  in irq_setup_generic_chip()
491 	for (i = gc->irq_base; msk; msk >>= 1, i++) {  in irq_setup_generic_chip()
502 			if (chip->irq_calc_mask)  in irq_setup_generic_chip()
503 				chip->irq_calc_mask(d);  in irq_setup_generic_chip()
505 				d->mask = 1 << (i - gc->irq_base);  in irq_setup_generic_chip()
507 		irq_set_chip_and_handler(i, chip, ct->handler);  in irq_setup_generic_chip()
511 	gc->irq_cnt = i - gc->irq_base;  in irq_setup_generic_chip()
516  * irq_setup_alt_chip - Switch to alternative chip
520  * Only to be called from chip->irq_set_type() callbacks.
525 	struct irq_chip_type *ct = gc->chip_types;  in irq_setup_alt_chip()
528 	for (i = 0; i < gc->num_ct; i++, ct++) {  in irq_setup_alt_chip()
529 		if (ct->type & type) {  in irq_setup_alt_chip()
530 			d->chip = &ct->chip;  in irq_setup_alt_chip()
531 			irq_data_to_desc(d)->handle_irq = ct->handler;  in irq_setup_alt_chip()
535 	return -EINVAL;  in irq_setup_alt_chip()
540  * irq_remove_generic_chip - Remove a chip
541  * @gc:		Generic irq chip holding all data
542  * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
546  * Remove up to 32 interrupts starting from gc->irq_base.
554 	list_del(&gc->list);  in irq_remove_generic_chip()
566 		if (gc->domain) {  in irq_remove_generic_chip()
567 			virq = irq_find_mapping(gc->domain, gc->irq_base + i);  in irq_remove_generic_chip()
571 			virq = gc->irq_base + i;  in irq_remove_generic_chip()
587 	if (!gc->domain)  in irq_gc_get_irq_data()
588 		return irq_get_irq_data(gc->irq_base);  in irq_gc_get_irq_data()
594 	if (!gc->installed)  in irq_gc_get_irq_data()
597 	virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));  in irq_gc_get_irq_data()
607 		struct irq_chip_type *ct = gc->chip_types;  in irq_gc_suspend()
609 		if (ct->chip.irq_suspend) {  in irq_gc_suspend()
613 				ct->chip.irq_suspend(data);  in irq_gc_suspend()
616 		if (gc->suspend)  in irq_gc_suspend()
617 			gc->suspend(gc);  in irq_gc_suspend()
627 		struct irq_chip_type *ct = gc->chip_types;  in irq_gc_resume()
629 		if (gc->resume)  in irq_gc_resume()
630 			gc->resume(gc);  in irq_gc_resume()
632 		if (ct->chip.irq_resume) {  in irq_gc_resume()
636 				ct->chip.irq_resume(data);  in irq_gc_resume()
650 		struct irq_chip_type *ct = gc->chip_types;  in irq_gc_shutdown()
652 		if (ct->chip.irq_pm_shutdown) {  in irq_gc_shutdown()
656 				ct->chip.irq_pm_shutdown(data);  in irq_gc_shutdown()