Lines Matching +full:rx +full:- +full:tx +full:- +full:swap
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
58 /* Media-dependent registers. */
59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
60 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
61 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
62 * Lanes B-D are numbered 134-136. */
63 #define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */
64 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
65 #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
66 #define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
67 #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
68 #define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
69 #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
70 #define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */
71 #define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
72 #define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
73 #define MDIO_PMA_PMD_BT1 18 /* BASE-T1 PMA/PMD extended ability */
74 #define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */
75 #define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */
76 #define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
77 #define MDIO_AN_T1_ADV_M 515 /* BASE-T1 AN advertisement register [31:16] */
78 #define MDIO_AN_T1_ADV_H 516 /* BASE-T1 AN advertisement register [47:32] */
79 #define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */
80 #define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */
81 #define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */
82 #define MDIO_AN_10BT1_AN_CTRL 526 /* 10BASE-T1 AN control register */
83 #define MDIO_AN_10BT1_AN_STAT 527 /* 10BASE-T1 AN status register */
84 #define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */
85 #define MDIO_PCS_1000BT1_CTRL 2304 /* 1000BASE-T1 PCS control register */
86 #define MDIO_PCS_1000BT1_STAT 2305 /* 1000BASE-T1 PCS status register */
116 /* 10PASS-TS/2BASE-TL */
124 #define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */
136 #define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
137 #define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
141 #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
161 #define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
162 #define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
163 #define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */
164 #define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
165 #define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */
166 #define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */
167 #define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */
168 #define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */
169 #define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */
170 #define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */
171 #define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */
172 #define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */
173 #define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */
174 #define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */
175 #define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */
176 #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
179 #define MDIO_PMA_CTRL2_BASET1 0x003D /* BASE-T1 type */
181 #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
182 #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
183 #define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
184 #define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */
192 #define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
193 #define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
194 #define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
195 #define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */
196 #define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */
197 #define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */
198 #define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
199 #define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */
203 #define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
204 #define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
205 #define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
210 #define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */
211 #define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */
212 #define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */
213 #define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */
214 #define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */
217 #define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */
218 #define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */
219 #define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */
220 #define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */
221 #define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */
224 #define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
225 #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
226 #define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
227 #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */
228 #define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */
229 #define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */
230 #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
231 #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
232 #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
233 #define MDIO_PMA_EXTABLE_BT1 0x0800 /* BASE-T1 ability */
234 #define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */
267 /* PMA 10GBASE-T pair swap & polarity */
275 /* PMA 10GBASE-T TX power register. */
276 #define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
278 /* PMA 10GBASE-T SNR registers. */
279 /* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
283 /* PMA 10GBASE-R FEC ability register. */
287 /* PMA 10GBASE-R Fast Retrain status and control register. */
290 /* PCS 10GBASE-R/-T status register 1. */
293 /* PCS 10GBASE-R/-T status register 2. */
297 /* AN 10GBASE-T control register. */
298 #define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020 /* Advertise 2.5GBASE-T fast retrain */
299 #define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */
300 #define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */
301 #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */
303 /* AN 10GBASE-T status register. */
314 /* 10BASE-T1L PMA control */
317 #define MDIO_PMA_10T1L_CTRL_LOW_POWER 0x0800 /* Low-power mode */
322 /* 10BASE-T1L PMA status register. */
328 #define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800 /* PMA has low-power ability */
332 /* 10BASE-T1L PCS control register. */
336 /* BASE-T1 PMA/PMD extended ability register. */
337 #define MDIO_PMA_PMD_BT1_B100_ABLE 0x0001 /* 100BASE-T1 Ability */
338 #define MDIO_PMA_PMD_BT1_B1000_ABLE 0x0002 /* 1000BASE-T1 Ability */
339 #define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 /* 10BASE-T1L Ability */
341 /* BASE-T1 auto-negotiation advertisement register [15:0] */
349 /* BASE-T1 auto-negotiation advertisement register [31:16] */
350 #define MDIO_AN_T1_ADV_M_B10L 0x4000 /* device is compatible with 10BASE-T1L */
353 /* BASE-T1 auto-negotiation advertisement register [47:32] */
354 #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level Transmit Request */
355 #define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level Transmit Ability */
357 /* BASE-T1 AN LP Base Page ability register [15:0] */
365 /* BASE-T1 AN LP Base Page ability register [31:16] */
367 #define MDIO_AN_T1_LP_M_B10L 0x4000 /* LP is compatible with 10BASE-T1L */
369 /* BASE-T1 AN LP Base Page ability register [47:32] */
370 #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */
371 #define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
373 /* 10BASE-T1 AN control register */
374 #define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000 /* 10BASE-T1L EEE ability advertisement */
376 /* 10BASE-T1 AN status register */
377 #define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 /* 10BASE-T1L LP EEE ability advertisement */
379 /* BASE-T1 PMA/PMD control register */
381 #define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000 0x0001 /* Select 1000BASE-T1 */
382 #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */
384 /* 1000BASE-T1 PCS control register */
389 /* 1000BASE-T1 PCS status register */
400 #define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
402 /* Note: the two defines above can be potentially used by the user-land
407 #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */
421 /* AN MultiGBASE-T AN control 2 */
429 #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
430 #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */
431 #define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */
432 #define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */
436 #define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */
437 #define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */
438 #define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */
461 /* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/
468 #define MDIO_USXGMII_10HALF 0x0000 /* 10Mbps half-duplex */
469 #define MDIO_USXGMII_10FULL 0x1000 /* 10Mbps full-duplex */
471 #define MDIO_USXGMII_100HALF 0x0200 /* 100Mbps half-duplex */
472 #define MDIO_USXGMII_100FULL 0x1200 /* 100Mbps full-duplex */
474 #define MDIO_USXGMII_1000HALF 0x0400 /* 1000Mbps half-duplex */
475 #define MDIO_USXGMII_1000FULL 0x1400 /* 1000Mbps full-duplex */
477 #define MDIO_USXGMII_10GHALF 0x0600 /* 10Gbps half-duplex */
478 #define MDIO_USXGMII_10GFULL 0x1600 /* 10Gbps full-duplex */
480 #define MDIO_USXGMII_2500HALF 0x0800 /* 2500Mbps half-duplex */
481 #define MDIO_USXGMII_2500FULL 0x1800 /* 2500Mbps full-duplex */
483 #define MDIO_USXGMII_5000HALF 0x0a00 /* 5000Mbps half-duplex */
484 #define MDIO_USXGMII_5000FULL 0x1a00 /* 5000Mbps full-duplex */
485 #define MDIO_USXGMII_LINK 0x8000 /* PHY link with copper-side partner */