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38 #define MDIO_CTRL2 7 /* 10G control 2 */
39 #define MDIO_STAT2 8 /* 10G status 2 */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
60 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
61 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
63 #define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */
64 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
65 #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
66 #define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
67 #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
68 #define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
69 #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
70 #define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */
71 #define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
72 #define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
82 #define MDIO_AN_10BT1_AN_CTRL 526 /* 10BASE-T1 AN control register */
83 #define MDIO_AN_10BT1_AN_STAT 527 /* 10BASE-T1 AN status register */
114 /* 10 Gb/s */
116 /* 10PASS-TS/2BASE-TL */
135 #define MDIO_SPEED_10G 0x0001 /* 10G capable */
137 #define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
140 #define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */
141 #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
161 #define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
162 #define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
163 #define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */
164 #define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
165 #define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */
166 #define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */
167 #define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */
168 #define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */
169 #define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */
170 #define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */
171 #define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */
172 #define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */
176 #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
181 #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
182 #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
183 #define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
184 #define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */
192 #define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
193 #define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
194 #define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
195 #define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */
196 #define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */
197 #define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */
198 #define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
203 #define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
204 #define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
205 #define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
224 #define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
225 #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
226 #define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
227 #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */
228 #define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */
232 #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
239 #define MDIO_AN_C73_0_PAUSE BIT(10)
251 #define MDIO_AN_C73_1_100GBASE_CR10 BIT(10)
267 /* PMA 10GBASE-T pair swap & polarity */
275 /* PMA 10GBASE-T TX power register. */
278 /* PMA 10GBASE-T SNR registers. */
283 /* PMA 10GBASE-R FEC ability register. */
287 /* PMA 10GBASE-R Fast Retrain status and control register. */
290 /* PCS 10GBASE-R/-T status register 1. */
293 /* PCS 10GBASE-R/-T status register 2. */
297 /* AN 10GBASE-T control register. */
301 #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */
303 /* AN 10GBASE-T status register. */
308 #define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */
314 /* 10BASE-T1L PMA control */
322 /* 10BASE-T1L PMA status register. */
332 /* 10BASE-T1L PCS control register. */
339 #define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 /* 10BASE-T1L Ability */
350 #define MDIO_AN_T1_ADV_M_B10L 0x4000 /* device is compatible with 10BASE-T1L */
354 #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level Transmit Request */
355 #define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level Transmit Ability */
367 #define MDIO_AN_T1_LP_M_B10L 0x4000 /* LP is compatible with 10BASE-T1L */
370 #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */
371 #define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
373 /* 10BASE-T1 AN control register */
374 #define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000 /* 10BASE-T1L EEE ability advertisement */
376 /* 10BASE-T1 AN status register */
377 #define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 /* 10BASE-T1L LP EEE ability advertisement */
409 #define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */
411 #define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */
412 #define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */
467 #define MDIO_USXGMII_10 0x0000 /* 10Mbps */
468 #define MDIO_USXGMII_10HALF 0x0000 /* 10Mbps half-duplex */
469 #define MDIO_USXGMII_10FULL 0x1000 /* 10Mbps full-duplex */
476 #define MDIO_USXGMII_10G 0x0600 /* 10Gbps */
477 #define MDIO_USXGMII_10GHALF 0x0600 /* 10Gbps half-duplex */
478 #define MDIO_USXGMII_10GFULL 0x1600 /* 10Gbps full-duplex */