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4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
44 * Format modifiers are used in conjunction with a fourcc code, forming a
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
69 * a canonical pair needs to be defined and used by all drivers. Preferred
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ argument
117 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
128 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */
129 #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
140 /* 8 bpp Red (direct relationship between channel value and brightness) */
141 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
153 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
154 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
160 /* 8 bpp RGB */
161 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
162 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
170 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian…
171 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian…
172 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian…
173 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian…
180 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian…
181 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian…
182 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian…
183 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian…
193 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian…
194 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian…
195 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian…
196 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian…
198 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian…
199 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian…
200 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian…
201 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian…
208 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
209 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
210 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
211 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
214 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 littl…
215 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 littl…
217 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 littl…
218 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 littl…
222 * IEEE 754-2008 binary16 half-precision float
228 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 litt…
229 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 litt…
232 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
235 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 1…
238 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little end…
239 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little end…
240 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little end…
241 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little end…
243 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian …
244 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endi…
245 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endi…
246 #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endi…
247 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
248 …010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only …
252 * 16-xx padding occupy lsb
260 * 16-xx padding occupy lsb except Y410
262 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
263 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12…
264 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 lit…
268 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 lit…
272 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
274 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
276 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
285 * 1-plane YUV 4:2:0
288 * These formats can only be used with a non-Linear modifier.
290 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
294 * 2 plane RGB + A
296 * index 1 = A plane, [7:0] A
298 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
299 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
300 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
301 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
302 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
303 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
304 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
305 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
318 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
319 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
327 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
364 /* 3 plane non-subsampled (444) YCbCr
372 /* 3 plane non-subsampled (444) YCrCb
397 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
398 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
404 * Format modifiers describe, typically, a re-ordering or modification
405 * of the data in a plane of an FB. This can be used to express tiled/
406 * swizzled formats, or compression, or a combination of the two.
408 * The upper 8 bits of the format modifier are a vendor-id as assigned
427 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
441 * When adding a new token please document the layout with a code comment,
447 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
449 * compatibility, in cases where a vendor-specific definition already exists and
450 * a generic name for it is desired, the common name is a purely symbolic alias
454 * generic layouts (such as pixel re-ordering), which may have
455 * independently-developed support across multiple vendors.
457 * In future cases where a generic layout is identified before merging with a
458 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
461 * apply to a single vendor.
474 * This modifier can be used as a sentinel to terminate the format modifiers
475 * list, or to initialize a variable with an invalid modifier. It might also be
485 * which tells the driver to also take driver-internal information into account
486 * and so might actually result in a tiled framebuffer.
495 * used is out-of-band information carried in an API-specific way (e.g. in a
503 * Intel X-tiling layout
505 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
506 * in row-major layout. Within the tile bytes are laid out row-major, with
507 * a platform-dependent stride. On top of that the memory can apply
508 * platform-depending swizzling of some higher address bits into bit6.
510 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
512 * cross-driver sharing. It exists since on a given platform it does uniquely
513 * identify the layout in a simple way for i915-specific userspace, which
520 * Intel Y-tiling layout
522 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
523 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
524 * chunks column-major, with a platform-dependent height. On top of that the
525 * memory can apply platform-depending swizzling of some higher address bits
528 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
530 * cross-driver sharing. It exists since on a given platform it does uniquely
531 * identify the layout in a simple way for i915-specific userspace, which
538 * Intel Yf-tiling layout
540 * This is a tiled layout using 4Kb tiles in row-major layout.
541 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
542 * are arranged in four groups (two wide, two high) with column-major layout.
544 * out as 2x2 column-major.
546 * either a square block or a 2:1 unit.
555 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
556 * The main surface will be plane index 0 and must be Y/Yf-tiled,
559 * Each CCS tile matches a 1024x512 pixel area of the main surface.
564 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
565 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
573 * Intel color control surfaces (CCS) for Gen-12 render compression.
575 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
576 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
577 * main surface. In other words, 4 bits in CCS map to a main surface cache
578 * line pair. The main surface pitch is required to be a multiple of four
579 * Y-tile widths.
584 * Intel color control surfaces (CCS) for Gen-12 media compression
586 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
587 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
588 * main surface. In other words, 4 bits in CCS map to a main surface cache
589 * line pair. The main surface pitch is required to be a multiple of four
590 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
597 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
600 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
609 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
611 * pitch is required to be a multiple of 4 tile widths.
613 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
618 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
621 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
622 * of 64B x 8 rows.
630 * outside of the GEM object in a reserved memory area dedicated for the
632 * main surface pitch is required to be a multiple of four Tile 4 widths.
639 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
642 * GEM object in a reserved memory area dedicated for the storage of the
644 * pitch is required to be a multiple of four Tile 4 widths.
652 * outside of the GEM object in a reserved memory area dedicated for the
654 * main surface pitch is required to be a multiple of four Tile 4 widths. The
666 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
667 * main surface. In other words, 4 bits in CCS map to a main surface cache
668 * line pair. The main surface pitch is required to be a multiple of four
677 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
678 * main surface. In other words, 4 bits in CCS map to a main surface cache
679 * line pair. The main surface pitch is required to be a multiple of four
680 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
699 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
701 * pitch is required to be a multiple of 4 tile widths.
706 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
708 * Macroblocks are laid in a Z-shape, and each pixel data is following the
713 * - multiple of 128 pixels for the width
714 * - multiple of 32 pixels for the height
716 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
721 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
723 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
724 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
732 * Refers to a compressed variant of the base format that is compressed.
733 * Implementation may be platform and base-format specific.
746 * Implementation may be platform and base-format specific.
759 * Implementation may be platform and base-format specific.
769 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
775 * Vivante 64x64 super-tiling layout
777 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
778 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
782 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
787 * Vivante 4x4 tiling layout for dual-pipe
789 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
791 * compared to the non-split tiled layout.
796 * Vivante 64x64 super-tiling layout for dual-pipe
798 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
799 * starts at a different base address. Offsets from the base addresses are
800 * therefore halved compared to the non-split super-tiled layout.
805 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
806 * the color buffer tiling modifiers defined above. When TS is present it's a
811 * We reserve the top 8 bits of the Vivante modifier space for tile status
822 * Vivante compression modifiers. Those depend on a TS modifier being present
848 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
850 * a block depth or height of "4").
857 * ---- ----- -----------------------------------------------------------------
861 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
863 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
865 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
867 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
871 * hardware support a block width of two gobs, but it is impractical
875 * 11:9 - Reserved (To support 2D-array textures with variable array stride
879 * 19:12 k Page Kind. This value directly maps to a field in the page
892 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
896 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
897 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
898 * 2 = Gob Height 8, Turing+ Page Kind mapping
901 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
907 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
923 * 55:25 - Reserved for future use. Must be zero.
935 * with block-linear layouts, is remapped within drivers to the value 0xfe,
936 * which corresponds to the "generic" kind used for simple single-sample
937 * uncompressed color formats on Fermi - Volta GPUs.
952 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
954 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
988 * type, and the next 24 bits for parameters. Top 8 bits are the
991 #define __fourcc_mod_broadcom_param_shift 8
997 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
999 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
1008 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1011 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1014 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1018 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1019 * tiles) or right-to-left (odd rows of 4k tiles).
1042 * and UV. Some SAND-using hardware stores UV in a separate tiled
1048 * wide, but as this is a 10 bpp format that translates to 96 pixels.
1085 * necessary to reduce the padding. If a hardware block can't do XOR,
1086 * the assumption is that a no-XOR tiling modifier will be created.
1093 * AFBC is a proprietary lossless image compression protocol and format.
1094 * It provides fine-grained random access and minimizes the amount of data
1099 * and different devices or use-cases may support different combinations.
1108 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1124 * size (in pixels) must be aligned to a multiple of the superblock size.
1131 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1148 * AFBC block-split
1151 * half of the payload is positioned at a predefined offset from the start
1159 * This flag indicates that the payload of each superblock must be stored at a
1169 * AFBC copy-block restrict
1171 * Buffers with this flag must obey the copy-block restriction. The restriction
1172 * is such that there are no copy-blocks referring across the border of 8x8
1173 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
1180 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1181 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1187 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
1192 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1193 * can be reduced if a whole superblock is a single color.
1198 * AFBC double-buffer
1200 * Indicates that the buffer is allocated in a layout safe for front-buffer
1208 * Indicates that the buffer includes per-superblock content hints.
1218 * affects the storage mode of the individual superblocks. Note that even a
1225 * Arm Fixed-Rate Compression (AFRC) modifiers
1227 * AFRC is a proprietary fixed rate image compression protocol and format,
1229 * reductions in graphics and media use-cases.
1235 * "coding unit" blocks which are individually compressed to a
1236 * fixed size (in bytes). All coding units within a given plane of a buffer
1245 * ---------------- ---------------
1251 * to a multiple of the paging tile dimensions.
1256 * ------ ----------------- ------------------
1258 * ROT 8 coding units 8 coding units
1265 * ----------------------------- --------- ----------------- ------------------
1267 * Example: 16x4 luma samples in a 'Y' plane
1268 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1269 * ----------------------------- --------- ----------------- ------------------
1270 * 1 ROT 8 samples 8 samples
1271 * Example: 8x8 luma samples in a 'Y' plane
1272 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1273 * ----------------------------- --------- ----------------- ------------------
1274 * 2 DONT CARE 8 samples 4 samples
1275 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1276 * ----------------------------- --------- ----------------- ------------------
1279 * ----------------------------- --------- ----------------- ------------------
1298 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1303 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1305 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1307 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1321 * Indicates if the buffer uses the scanline-optimised layout
1322 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1325 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1328 * Arm 16x16 Block U-Interleaved modifier
1341 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1347 * both in row-major order.
1354 * Amlogic uses a proprietary lossless image compression protocol and format
1361 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1363 * - DRM_FORMAT_YUV420_8BIT
1364 * - DRM_FORMAT_YUV420_10BIT
1366 * The first 8 bits of the mode defines the layout, then the following 8 bits
1373 #define __fourcc_mod_amlogic_options_shift 8
1388 * - a body content organized in 64x32 superblocks with 4096 bytes per
1390 * - a 32 bytes per 128x64 header block
1408 * be accessible by the user-space clients, but only accessible by the
1411 * The user-space clients should expect a failure while trying to mmap
1412 * the DMA-BUF handle returned by the producer.
1422 * boundaries, i.e. 8bit should be stored in this mode to save allocation
1437 * - main surface
1440 * - main surface in plane 0
1441 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1444 * - main surface in plane 0
1445 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1446 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1448 * For multi-plane formats the above surfaces get merged into one plane for
1452 * ----- ------------------------ ---------------------------------------------
1455 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1468 * 55:36 - Reserved for future use, must be zero
1487 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1502 #define AMD_FMT_MOD_TILE_SHIFT 8
1511 * one which is not-aligned.
1530 * and prefers the driver provided color. This necessitates doing a fastclear
1531 * eliminate operation before a process transfers control.