Lines Matching +full:dac +full:- +full:mode +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
28 #define MAXPAGES0 4096 /* 32 bit mode */
29 #define MAXPAGES1 8192 /* 31 bit mode */
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
35 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
41 // This is used to define hardware bit-fields (sub-registers) by combining
43 // mask must represent a single run of adjacent bits.
44 // The non-concatenating (_NC) variant should be used directly only for
45 // sub-registers that do not follow the <register>_<field> naming pattern.
46 #define SUB_REG_NC(reg, field, mask) \ argument
48 field ## _MASK = mask, \
50 (__builtin_ctz(mask) << 16) | \
51 (__builtin_popcount(mask) << 24), \
53 #define SUB_REG(reg, field, mask) SUB_REG_NC(reg, reg ## _ ## field, mask) argument
55 // Macros for manipulating values of bit-fields declared using the above macros.
59 // single sub-register at a time.
62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
79 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
81 /* accessed. For non per-channel registers the */
117 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
134 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
139 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
143 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
144 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
145 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
146 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
148 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
161 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
162 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
180 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
181 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
215 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
216 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
219 /* they are not rate-locked to the external */
223 /* the SPDIF V-bit indicates invalid audio */
237 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
238 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
249 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
255 /* they are not rate-locked to the external */
267 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
271 // On Audigy, the MPU port moved to the 0x70-0x74 ptr registers
290 // card-specific info can be found in the emu_chip_details table.
291 // On E-MU cards the port is used as the interface to the FPGA.
300 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
320 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
346 /* 0x00000000 2-channel output. */
347 /* 0x00000200 8-channel output. */
354 * bit 8: Record 8-channel in phase.
355 * bit 9: Playback 8-channel in phase.
356 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
383 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
388 // "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers
389 // "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view
392 // - The engine has 64 playback channels, also called voices. The channels
394 // - PCM samples are fetched into the cache; see description of CD0 below.
395 // - Samples are consumed at the rate CPF_CURRENTPITCH.
396 // - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8
397 // - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated
400 // - The value is multiplied by CVCF_CURRENTVOL.
401 // - The value goes through a filter with cutoff CVCF_CURRENTFILTER;
403 // - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2)
405 // multiplied by a per-send amount (*_FXSENDAMOUNT_*).
406 // The scaling of the send amounts is exponential-ish.
407 // - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*.
408 // - The pitch, volume, and filter cutoff can be modulated by two envelope
410 // - To avoid abrupt changes to the parameters (which may cause audible
417 // The somewhat non-obviously still meaningful ones are:
471 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
472 /* 8-bit samples are unsigned, 16-bit ones signed */
479 /* Auto-set from CPF_STEREO_MASK */
481 /* Auto-set from CCCA_8BITSELECT */
513 /* 0x8000-n == 666*n usec delay */
517 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
532 /* 0x8000-n == 666*n usec delay */
536 /* 0x8000-n == 666*n usec delay */
540 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
552 /* 0x8000-n == 666*n usec delay */
567 /* Signed 2's complement, +/- one octave peak extremes */
569 /* Signed 2's complement, +/- six octaves peak extremes */
574 /* Signed 2's complement, +/- one octave extremes */
576 /* Signed 2's complement, +/- three octave extremes */
580 /* Signed 2's complement, with +/- 12dB extremes */
586 /* Signed 2's complement, +/- one octave extremes */
591 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
598 // In stereo mode, the two channels' caches are concatenated into one,
600 // The cache holds 64 frames, so the upper half is not used in 8-bit mode.
603 // The cache is filled from (CCCA_CURRADDR - CCR_CACHEINVALIDSIZE)
604 // into (CCR_READADDRESS - CCR_CACHEINVALIDSIZE).
606 // CCR_CACHEINVALIDSIZE below 8 (16-bit stereo), 16 (16-bit mono,
607 // 8-bit stereo), or 32 (8-bit mono). The actual transfers are pretty
645 /* 0x20-0x3f) to host memory. This mode of recording */
671 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
679 /* The following mask values define the size of the ADC, MIC and FX buffers in bytes */
720 // NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1)
721 #define CDCS 0x50 /* CD-ROM digital channel status register */
735 // NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1)
756 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
757 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
758 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
762 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
764 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
768 /* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */
781 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
782 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
783 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
784 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
785 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
795 // NOTE: 0x60,61,62: 64-bit
796 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
810 /* Note that these values can vary +/- by a small amount */
830 /* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */
859 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
860 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
886 #define A_EHC_P17V_TVM 0x00000001 /* Tank virtual memory mode */
897 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
941 /* E-MU Digital Audio System overview */
944 // - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2);
946 // - All physical PCM I/O is routed through an additional FPGA; the regular
948 // - The FPGA has a signal routing matrix, to connect each destination (output
950 // - The FPGA is controlled via Audigy's GPIO port, while sample data is
951 // transmitted via proprietary EMU32 serial links. On first-generation
952 // E-MU 1010 cards, Audigy's I2S inputs are also used for sample data.
953 // - The Audio/Micro Dock is attached to Hana via EDI, a "network" link.
954 // - The Audigy chip operates in slave mode; the clock is supplied by the FPGA.
955 // Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples),
957 // - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz
960 // - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total
962 // - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due
964 // can overlap with the Dock's ADC/DAC's high channels.
965 // - The code names are mentioned below and in the emu_chip_details table.
1019 #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
1036 #define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */
1037 #define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */
1039 #define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */
1040 #define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */
1071 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
1072 #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
1073 #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
1074 #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
1075 #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
1076 #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
1077 #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
1078 #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
1087 #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
1088 #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
1089 #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
1090 #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
1091 #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
1092 #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
1094 /* 0x14 - 0x1f Unused R/W registers */
1119 // The actual code disagrees about the bit width of the registers -
1134 /* 0x30 - 0x3f Unused Read only registers */
1136 // The meaning of this is not clear; kX-project just calls it "lock" in some info-only code.
1144 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1145 * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock
1146 * 0x00: Dock DAC 1 Left
1147 * 0x04: Dock DAC 1 Right
1148 * 0x08: Dock DAC 2 Left
1149 * 0x0c: Dock DAC 2 Right
1150 * 0x10: Dock DAC 3 Left
1151 * 0x12: PHONES Left (n/a in 2x/4x mode; output mirrors DAC4 Left)
1152 * 0x14: Dock DAC 3 Right
1153 * 0x16: PHONES Right (n/a in 2x/4x mode; output mirrors DAC4 Right)
1154 * 0x18: Dock DAC 4 Left
1156 * 0x1c: Dock DAC 4 Right
1160 * 0x03, 0x00: Hamoa DAC Left
1161 * 0x03, 0x01: Hamoa DAC Right
1162 * 0x04, 0x00-0x07: Hana ADAT
1174 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1175 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1176 * 0x00: Dock DAC 1 Left
1177 * 0x04: Dock DAC 1 Right
1178 * 0x08: Dock DAC 2 Left
1179 * 0x0c: Dock DAC 2 Right
1180 * 0x10: Dock DAC 3 Left
1182 * 0x14: Dock DAC 3 Right
1184 * 0x18-0x1f: Dock ADAT 0-7
1187 * 0x03, 0x00: Hamoa DAC Left
1188 * 0x03, 0x01: Hamoa DAC Right
1189 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1190 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1191 * 0x06-0x07: Not used
1195 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina
1199 * 0x03, 0x00: DAC Left
1200 * 0x03, 0x01: DAC Right
1201 * 0x04-0x07: Not used
1204 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1205 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1208 * 0x03, 0x00: Mana DAC Left
1209 * 0x03, 0x01: Mana DAC Right
1210 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1211 * 0x05-0x07: Not used
1214 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1215 * physical outputs of Hana, or outputs going to Alice2/Tina for capture -
1217 * a channel depends on the mixer control setting for each destination - see
1285 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1286 #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
1287 #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
1288 #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */
1289 #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1290 #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
1291 #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
1292 #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
1293 // In S/MUX mode, the samples of one channel are adjacent.
1317 * 0x00, 0x00-0x1f: Silence
1318 * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock
1329 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1330 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1331 * 0x04, 0x00-0x07: Hana ADAT
1334 * 0x06-0x07: Not used
1340 * 0x00, 0x00-0x1f: Silence
1341 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1350 * 0x18-0x1f: Dock ADAT 0-7
1353 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1354 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1355 * 0x04, 0x00-0x07: Hana3 ADAT
1358 * 0x06-0x07: Not used
1362 * 0x00, 0x00-0x1f: Silence
1366 * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output
1367 * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output
1371 * 0x06-0x07: Not used
1374 * 0x00, 0x00-0x1f: Silence
1375 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1378 * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output
1379 * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output
1380 * 0x04-0x07: Not used
1383 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1384 * destinations using a mixer control for each destination - see emumixer.c.
1385 * Sources are either physical inputs of Hana, or inputs from Alice2/Tina -
1431 // In S/MUX mode, the samples of one channel are adjacent.
1453 /* ------------------- CONSTANTS -------------------- */
1462 /* ------------------- STRUCTURES -------------------- */
1507 unsigned int capture_ipr; /* interrupt acknowledge mask */
1508 unsigned int capture_inte; /* interrupt enable mask */
1549 …efine snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (P…
1578 unsigned int channels; /* 16-bit channels count */
1633 // Chip-o-logy:
1634 // - All SB Live! cards use EMU10K1 chips
1635 // - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver
1636 // - Original Audigy uses CA0100 "Alice"
1637 // - Audigy 2 uses CA0102/CA10200 "Alice2"
1638 // - Has an interface for CA0151 (P16V) "Alice3"
1639 // - Audigy 2 Value uses CA0108/CA10300 "Tina"
1640 // - Approximately a CA0102 with an on-chip CA0151 (P17V)
1641 // - Audigy 2 ZS NB uses CA0109 "Tina2"
1642 // - Cardbus version of CA0108
1660 unsigned int sblive51:1; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1664 unsigned int spi_dac:1; /* SPI interface for DAC; requires ca0108_chip */
1670 const char *id; /* for backward compatibility - can be NULL if not needed */
1679 unsigned int adc_pads; /* bit mask */
1680 unsigned int dac_pads; /* bit mask */
1706 unsigned int address_mode; /* address mode */
1707 unsigned long dma_mask; /* PCI DMA mask */
1744 spinlock_t reg_lock; // high-level driver lock
1745 spinlock_t emu_lock; // low-level i/o lock
1860 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >>… in snd_emu10k1_wc()