Lines Matching +full:0 +full:xe00
20 VIA_PORT_NONE = 0,
26 VIA_MODE_OFF = 0,
32 VIA_PORT_26 = 0,
105 #define VDE_INTERRUPT 0x200 /* Video interrupt flags/masks */
106 #define VDE_I_DVISENSE 0x00000001 /* DVI sense int status */
107 #define VDE_I_VBLANK 0x00000002 /* Vertical blank status */
108 #define VDE_I_MCCFI 0x00000004 /* MCE compl. frame int status */
109 #define VDE_I_VSYNC 0x00000008 /* VGA VSYNC int status */
110 #define VDE_I_DMA0DDONE 0x00000010 /* DMA 0 descr done */
111 #define VDE_I_DMA0TDONE 0x00000020 /* DMA 0 transfer done */
112 #define VDE_I_DMA1DDONE 0x00000040 /* DMA 1 descr done */
113 #define VDE_I_DMA1TDONE 0x00000080 /* DMA 1 transfer done */
114 #define VDE_I_C1AV 0x00000100 /* Cap Eng 1 act vid end */
115 #define VDE_I_HQV0 0x00000200 /* First HQV engine */
116 #define VDE_I_HQV1 0x00000400 /* Second HQV engine */
117 #define VDE_I_HQV1EN 0x00000800 /* Second HQV engine enable */
118 #define VDE_I_C0AV 0x00001000 /* Cap Eng 0 act vid end */
119 #define VDE_I_C0VBI 0x00002000 /* Cap Eng 0 VBI end */
120 #define VDE_I_C1VBI 0x00004000 /* Cap Eng 1 VBI end */
121 #define VDE_I_VSYNC2 0x00008000 /* Sec. Disp. VSYNC */
122 #define VDE_I_DVISNSEN 0x00010000 /* DVI sense enable */
123 #define VDE_I_VSYNC2EN 0x00020000 /* Sec Disp VSYNC enable */
124 #define VDE_I_MCCFIEN 0x00040000 /* MC comp frame int mask enable */
125 #define VDE_I_VSYNCEN 0x00080000 /* VSYNC enable */
126 #define VDE_I_DMA0DDEN 0x00100000 /* DMA 0 descr done enable */
127 #define VDE_I_DMA0TDEN 0x00200000 /* DMA 0 trans done enable */
128 #define VDE_I_DMA1DDEN 0x00400000 /* DMA 1 descr done enable */
129 #define VDE_I_DMA1TDEN 0x00800000 /* DMA 1 trans done enable */
130 #define VDE_I_C1AVEN 0x01000000 /* cap 1 act vid end enable */
131 #define VDE_I_HQV0EN 0x02000000 /* First hqv engine enable */
132 #define VDE_I_C1VBIEN 0x04000000 /* Cap 1 VBI end enable */
133 #define VDE_I_LVDSSI 0x08000000 /* LVDS sense interrupt */
134 #define VDE_I_C0AVEN 0x10000000 /* Cap 0 act vid end enable */
135 #define VDE_I_C0VBIEN 0x20000000 /* Cap 0 VBI end enable */
136 #define VDE_I_LVDSSIEN 0x40000000 /* LVDS Sense enable */
137 #define VDE_I_ENABLE 0x80000000 /* Global interrupt enable */
151 #define VDMA_MR0 0xe00 /* Mod reg 0 */
152 #define VDMA_MR_CHAIN 0x01 /* Chaining mode */
153 #define VDMA_MR_TDIE 0x02 /* Transfer done int enable */
154 #define VDMA_CSR0 0xe04 /* Control/status */
155 #define VDMA_C_ENABLE 0x01 /* DMA Enable */
156 #define VDMA_C_START 0x02 /* Start a transfer */
157 #define VDMA_C_ABORT 0x04 /* Abort a transfer */
158 #define VDMA_C_DONE 0x08 /* Transfer is done */
159 #define VDMA_MARL0 0xe20 /* Mem addr low */
160 #define VDMA_MARH0 0xe24 /* Mem addr high */
161 #define VDMA_DAR0 0xe28 /* Device address */
162 #define VDMA_DQWCR0 0xe2c /* Count (16-byte) */
163 #define VDMA_TMR0 0xe30 /* Tile mode reg */
164 #define VDMA_DPRL0 0xe34 /* Not sure */
165 #define VDMA_DPR_IN 0x08 /* Inbound transfer to FB */
166 #define VDMA_DPRH0 0xe38
167 #define VDMA_PMR0 (0xe00 + 0x134) /* Pitch mode */
182 #define VIAStatus 0x3DA /* Non-indexed port */
183 #define VIACR 0x3D4
184 #define VIASR 0x3C4
185 #define VIAGR 0x3CE
186 #define VIAAR 0x3C0
209 #define VIA_MISC_REG_READ 0x03CC
210 #define VIA_MISC_REG_WRITE 0x03C2