Lines Matching +full:0 +full:x042
14 #define SDW_SHIM_BASE 0x2C000
15 #define SDW_ALH_BASE 0x2C800
16 #define SDW_SHIM_BASE_ACE 0x38000
17 #define SDW_ALH_BASE_ACE 0x24000
18 #define SDW_LINK_BASE 0x30000
19 #define SDW_LINK_SIZE 0x10000
23 #define SDW_SHIM_LCAP 0x0
24 #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
27 #define SDW_SHIM_LCTL 0x4
29 #define SDW_SHIM_LCTL_SPA BIT(0)
30 #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
35 #define SDW_SHIM_SYNC 0xC
39 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
46 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
47 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
48 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
49 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
50 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
53 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
55 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
60 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
63 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
65 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
71 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
73 #define SDW_SHIM_IOCTL_MIF BIT(0)
84 #define SDW_SHIM_WAKEEN 0x190
86 #define SDW_SHIM_WAKEEN_ENABLE BIT(0)
89 #define SDW_SHIM_WAKESTS 0x192
91 #define SDW_SHIM_WAKESTS_STATUS BIT(0)
94 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
96 #define SDW_SHIM_CTMCTL_DACTQE BIT(0)
101 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
104 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
105 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
113 #define SDW_SHIM2_GENERIC_BASE(x) (0x00030000 + 0x8000 * (x))
114 #define SDW_IP_BASE(x) (0x00030100 + 0x8000 * (x))
115 #define SDW_SHIM2_VS_BASE(x) (0x00036000 + 0x8000 * (x))
119 #define SDW_SHIM2_LECAP 0x00
120 #define SDW_SHIM2_LECAP_HDS BIT(0) /* unset -> Host mode */
124 #define SDW_SHIM2_PCMSCAP 0x10
125 #define SDW_SHIM2_PCMSCAP_ISS GENMASK(3, 0) /* Input-only streams */
130 #define SDW_SHIM2_PCMSYCHC(y) (0x14 + (0x4 * (y)))
131 #define SDW_SHIM2_PCMSYCHC_CS GENMASK(3, 0) /* Channels Supported */
134 #define SDW_SHIM2_PCMSYCHM(y) (0x16 + (0x4 * (y)))
135 #define SDW_SHIM2_PCMSYCHM_LCHAN GENMASK(3, 0) /* Lowest channel used by the FIFO port */
141 #define SDW_SHIM2_INTEL_VS_LVSCTL 0x04
147 #define SDW_SHIM2_MLCS_XTAL_CLK 0x0
148 #define SDW_SHIM2_MLCS_CARDINAL_CLK 0x1
149 #define SDW_SHIM2_MLCS_AUDIO_PLL_CLK 0x2
150 #define SDW_SHIM2_MLCS_MCLK_INPUT_CLK 0x3
151 #define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK 0x4
153 #define SDW_SHIM2_INTEL_VS_WAKEEN 0x08
154 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWE BIT(0)
156 #define SDW_SHIM2_INTEL_VS_WAKESTS 0x0A
157 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWS BIT(0)
159 #define SDW_SHIM2_INTEL_VS_IOCTL 0x0C
160 #define SDW_SHIM2_INTEL_VS_IOCTL_MIF BIT(0)
172 #define SDW_SHIM2_INTEL_VS_ACTMCTL 0x0E
173 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE BIT(0)
240 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0)