92 #define rtsx_pci_writel(pcr, reg, value) \  argument
94 #define rtsx_pci_readl(pcr, reg) \  argument
96 #define rtsx_pci_writew(pcr, reg, value) \  argument
98 #define rtsx_pci_readw(pcr, reg) \  argument
100 #define rtsx_pci_writeb(pcr, reg, value) \  argument
102 #define rtsx_pci_readb(pcr, reg) \  argument
1080 #define rtsx_pci_init_cmd(pcr)		((pcr)->ci = 0)  argument
1088 	struct rtsx_pcr			*pcr;  member
1283 #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))  argument
1284 #define PCI_VID(pcr)			((pcr)->pci->vendor)  argument
1285 #define PCI_PID(pcr)			((pcr)->pci->device)  argument
1286 #define is_version(pcr, pid, ver)				\  argument
1288 #define is_version_higher_than(pcr, pid, ver)			\  argument
1290 #define pcr_dbg(pcr, fmt, arg...)				\  argument
1296 #define SDR104_TX_PHASE(pcr)		SDR104_PHASE((pcr)->tx_initial_phase)  argument
1297 #define SDR50_TX_PHASE(pcr)		SDR50_PHASE((pcr)->tx_initial_phase)  argument
1298 #define DDR50_TX_PHASE(pcr)		DDR50_PHASE((pcr)->tx_initial_phase)  argument
1299 #define SDR104_RX_PHASE(pcr)		SDR104_PHASE((pcr)->rx_initial_phase)  argument
1300 #define SDR50_RX_PHASE(pcr)		SDR50_PHASE((pcr)->rx_initial_phase)  argument
1301 #define DDR50_RX_PHASE(pcr)		DDR50_PHASE((pcr)->rx_initial_phase)  argument
1336 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)  in rtsx_pci_get_cmd_data()
1341 static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)  in rtsx_pci_write_be32()
1349 static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,  in rtsx_pci_update_phy()