Lines Matching +full:we +full:- +full:extra +full:- +full:delay

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 	/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
47 	/* WE signals timings corresponding to GPMC_CONFIG4 */
48 	u32 we_on;		/* WE assertion time */
49 	u32 we_off;		/* WE deassertion time */
58 	u32 page_burst_access;	/* Multiple access word delay */
59 	u32 access;		/* Start-cycle to first data valid delay */
99 	u32 t_weasu;	/* address setup to WE valid */
105 	u32 t_bacc;	/* burst access valid clock to output delay */
113 	u32 t_ce_avd;	/* CS on to ADV on delay */
124 	/* extra delays */
134 #define GPMC_DEVWIDTH_8BIT		1	/* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT		2	/* 16-bit device width */
136 #define GPMC_MUX_AAD			1	/* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD			2	/* Addr-Data multiplex */
158 	u32 wait_pin;		/* wait-pin to be used */