linux/platform_data/gpmc-omap.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 	/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
37 	u32 cs_wr_off;		/* Write deassertion time */
42 	u32 adv_wr_off;		/* Write deassertion time */
45 	u32 adv_aad_mux_wr_off;	/* ADV write deassertion time for AAD */
59 	u32 access;		/* Start-cycle to first data valid delay */
61 	u32 wr_cycle;		/* Total write cycle time */
69 	/* The following are only on OMAP3430 */
97 	u32 t_cez_w;	/* write CS deassertion to high Z */
100 	u32 t_wpl;	/* write assertion time */
101 	u32 t_wph;	/* write deassertion time */
102 	u32 t_wr_cycle;	/* write cycle time */
113 	u32 t_ce_avd;	/* CS on to ADV on delay */
119 	u8 cyc_aavdh_we;/* write address hold time in cycles */
121 	u8 cyc_wpl;	/* write deassertion time in cycles */
134 #define GPMC_DEVWIDTH_8BIT		1	/* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT		2	/* 16-bit device width */
136 #define GPMC_MUX_AAD			1	/* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD			2	/* Addr-Data multiplex */
139 /* Wait pin polarity values */
149 	bool burst_write;	/* enables write page/burst mode */
153 	bool wait_on_read;	/* monitor wait on reads */
154 	bool wait_on_write;	/* monitor wait on writes */
158 	u32 wait_pin;		/* wait-pin to be used */