18 #define FLCMNCR(f)		(f->reg + 0x0)  argument
19 #define FLCMDCR(f)		(f->reg + 0x4)  argument
20 #define FLCMCDR(f)		(f->reg + 0x8)  argument
21 #define FLADR(f)		(f->reg + 0xC)  argument
22 #define FLADR2(f)		(f->reg + 0x3C)  argument
23 #define FLDATAR(f)		(f->reg + 0x10)  argument
24 #define FLDTCNTR(f)		(f->reg + 0x14)  argument
25 #define FLINTDMACR(f)		(f->reg + 0x18)  argument
26 #define FLBSYTMR(f)		(f->reg + 0x1C)  argument
27 #define FLBSYCNT(f)		(f->reg + 0x20)  argument
28 #define FLDTFIFO(f)		(f->reg + 0x24)  argument
29 #define FLECFIFO(f)		(f->reg + 0x28)  argument
30 #define FLTRCR(f)		(f->reg + 0x2C)  argument
31 #define FLHOLDCR(f)		(f->reg + 0x38)  argument
32 #define	FL4ECCRESULT0(f)	(f->reg + 0x80)  argument
33 #define	FL4ECCRESULT1(f)	(f->reg + 0x84)  argument
34 #define	FL4ECCRESULT2(f)	(f->reg + 0x88)  argument
35 #define	FL4ECCRESULT3(f)	(f->reg + 0x8C)  argument
36 #define	FL4ECCCR(f)		(f->reg + 0x90)  argument
37 #define	FL4ECCCNT(f)		(f->reg + 0x94)  argument
38 #define	FLERRADR(f)		(f->reg + 0x98)  argument
46 #define SNAND_E		(0x1 << 18)	/* SNAND (0=512 1=2048)*/
48 #define ENDIAN		(0x1 << 16)	/* 1 = little endian */
53 #define	CE1_ENABLE	(0x1 << 4)	/* Chip Enable 1 */
86 #define SELRW		(0x1 << 21)	/*  0:read 1:write */
88 #define ADRCNT_1	(0x00 << 18)	/* Address data bytes: 1byte */
93 #define DOCMD1_E	(0x1 << 16)	/* 1st cmd stage execute */
106 #define TREND		(0x1 << 1)	/* translation end */
119 #define	_4ECCEND	(0x1 << 1)	/* 4 symbols end */
152 	unsigned page_size:1;	/* NAND page size (0 = 512, 1 = 2048) */
153 	unsigned hwecc:1;	/* Hardware ECC (0 = disabled, 1 = enabled) */
154 	unsigned holden:1;	/* Hardware has FLHOLDCR and HOLDEN is set */
155 	unsigned qos_request:1;	/* QoS request to prevent deep power shutdown */
168 	unsigned has_hwecc:1;
169 	unsigned use_holden:1;