Lines Matching +full:0 +full:x10
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1,
69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15,
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20,
74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25,
78 MLX5_SHARED_RESOURCE_UID = 0xffff,
82 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23,
96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
101 MLX5_OBJ_TYPE_MKEY = 0xff01,
102 MLX5_OBJ_TYPE_QP = 0xff02,
103 MLX5_OBJ_TYPE_PSV = 0xff03,
104 MLX5_OBJ_TYPE_RMP = 0xff04,
105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
106 MLX5_OBJ_TYPE_RQ = 0xff06,
107 MLX5_OBJ_TYPE_SQ = 0xff07,
108 MLX5_OBJ_TYPE_TIR = 0xff08,
109 MLX5_OBJ_TYPE_TIS = 0xff09,
110 MLX5_OBJ_TYPE_DCT = 0xff0a,
111 MLX5_OBJ_TYPE_XRQ = 0xff0b,
112 MLX5_OBJ_TYPE_RQT = 0xff0e,
113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
114 MLX5_OBJ_TYPE_CQ = 0xff10,
118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
120 MLX5_CMD_OP_INIT_HCA = 0x102,
121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
122 MLX5_CMD_OP_ENABLE_HCA = 0x104,
123 MLX5_CMD_OP_DISABLE_HCA = 0x105,
124 MLX5_CMD_OP_QUERY_PAGES = 0x107,
125 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
126 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
127 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
128 MLX5_CMD_OP_SET_ISSI = 0x10b,
129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
131 MLX5_CMD_OP_ALLOC_SF = 0x113,
132 MLX5_CMD_OP_DEALLOC_SF = 0x114,
133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115,
134 MLX5_CMD_OP_RESUME_VHCA = 0x116,
135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117,
136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118,
137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119,
138 MLX5_CMD_OP_CREATE_MKEY = 0x200,
139 MLX5_CMD_OP_QUERY_MKEY = 0x201,
140 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
146 MLX5_CMD_OP_CREATE_EQ = 0x301,
147 MLX5_CMD_OP_DESTROY_EQ = 0x302,
148 MLX5_CMD_OP_QUERY_EQ = 0x303,
149 MLX5_CMD_OP_GEN_EQE = 0x304,
150 MLX5_CMD_OP_CREATE_CQ = 0x400,
151 MLX5_CMD_OP_DESTROY_CQ = 0x401,
152 MLX5_CMD_OP_QUERY_CQ = 0x402,
153 MLX5_CMD_OP_MODIFY_CQ = 0x403,
154 MLX5_CMD_OP_CREATE_QP = 0x500,
155 MLX5_CMD_OP_DESTROY_QP = 0x501,
156 MLX5_CMD_OP_RST2INIT_QP = 0x502,
157 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
158 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
159 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
161 MLX5_CMD_OP_2ERR_QP = 0x507,
162 MLX5_CMD_OP_2RST_QP = 0x50a,
163 MLX5_CMD_OP_QUERY_QP = 0x50b,
164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
166 MLX5_CMD_OP_CREATE_PSV = 0x600,
167 MLX5_CMD_OP_DESTROY_PSV = 0x601,
168 MLX5_CMD_OP_CREATE_SRQ = 0x700,
169 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
170 MLX5_CMD_OP_QUERY_SRQ = 0x702,
171 MLX5_CMD_OP_ARM_RQ = 0x703,
172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
176 MLX5_CMD_OP_CREATE_DCT = 0x710,
177 MLX5_CMD_OP_DESTROY_DCT = 0x711,
178 MLX5_CMD_OP_DRAIN_DCT = 0x712,
179 MLX5_CMD_OP_QUERY_DCT = 0x713,
180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
181 MLX5_CMD_OP_CREATE_XRQ = 0x717,
182 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
183 MLX5_CMD_OP_QUERY_XRQ = 0x719,
184 MLX5_CMD_OP_ARM_XRQ = 0x71a,
185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
218 MLX5_CMD_OP_ALLOC_PD = 0x800,
219 MLX5_CMD_OP_DEALLOC_PD = 0x801,
220 MLX5_CMD_OP_ALLOC_UAR = 0x802,
221 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
223 MLX5_CMD_OP_ACCESS_REG = 0x805,
224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
227 MLX5_CMD_OP_MAD_IFC = 0x50d,
228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
230 MLX5_CMD_OP_NOP = 0x80d,
231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
245 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
247 MLX5_CMD_OP_CREATE_LAG = 0x840,
248 MLX5_CMD_OP_MODIFY_LAG = 0x841,
249 MLX5_CMD_OP_QUERY_LAG = 0x842,
250 MLX5_CMD_OP_DESTROY_LAG = 0x843,
251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
253 MLX5_CMD_OP_CREATE_TIR = 0x900,
254 MLX5_CMD_OP_MODIFY_TIR = 0x901,
255 MLX5_CMD_OP_DESTROY_TIR = 0x902,
256 MLX5_CMD_OP_QUERY_TIR = 0x903,
257 MLX5_CMD_OP_CREATE_SQ = 0x904,
258 MLX5_CMD_OP_MODIFY_SQ = 0x905,
259 MLX5_CMD_OP_DESTROY_SQ = 0x906,
260 MLX5_CMD_OP_QUERY_SQ = 0x907,
261 MLX5_CMD_OP_CREATE_RQ = 0x908,
262 MLX5_CMD_OP_MODIFY_RQ = 0x909,
263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
264 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
265 MLX5_CMD_OP_QUERY_RQ = 0x90b,
266 MLX5_CMD_OP_CREATE_RMP = 0x90c,
267 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
268 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
269 MLX5_CMD_OP_QUERY_RMP = 0x90f,
270 MLX5_CMD_OP_CREATE_TIS = 0x912,
271 MLX5_CMD_OP_MODIFY_TIS = 0x913,
272 MLX5_CMD_OP_DESTROY_TIS = 0x914,
273 MLX5_CMD_OP_QUERY_TIS = 0x915,
274 MLX5_CMD_OP_CREATE_RQT = 0x916,
275 MLX5_CMD_OP_MODIFY_RQT = 0x917,
276 MLX5_CMD_OP_DESTROY_RQT = 0x918,
277 MLX5_CMD_OP_QUERY_RQT = 0x919,
278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
307 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
309 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
311 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12,
315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16,
321 MLX5_CMD_OP_GENERAL_START = 0xb00,
322 MLX5_CMD_OP_GENERAL_END = 0xd00,
326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
335 u8 outer_dmac[0x1];
336 u8 outer_smac[0x1];
337 u8 outer_ether_type[0x1];
338 u8 outer_ip_version[0x1];
339 u8 outer_first_prio[0x1];
340 u8 outer_first_cfi[0x1];
341 u8 outer_first_vid[0x1];
342 u8 outer_ipv4_ttl[0x1];
343 u8 outer_second_prio[0x1];
344 u8 outer_second_cfi[0x1];
345 u8 outer_second_vid[0x1];
346 u8 reserved_at_b[0x1];
347 u8 outer_sip[0x1];
348 u8 outer_dip[0x1];
349 u8 outer_frag[0x1];
350 u8 outer_ip_protocol[0x1];
351 u8 outer_ip_ecn[0x1];
352 u8 outer_ip_dscp[0x1];
353 u8 outer_udp_sport[0x1];
354 u8 outer_udp_dport[0x1];
355 u8 outer_tcp_sport[0x1];
356 u8 outer_tcp_dport[0x1];
357 u8 outer_tcp_flags[0x1];
358 u8 outer_gre_protocol[0x1];
359 u8 outer_gre_key[0x1];
360 u8 outer_vxlan_vni[0x1];
361 u8 outer_geneve_vni[0x1];
362 u8 outer_geneve_oam[0x1];
363 u8 outer_geneve_protocol_type[0x1];
364 u8 outer_geneve_opt_len[0x1];
365 u8 source_vhca_port[0x1];
366 u8 source_eswitch_port[0x1];
368 u8 inner_dmac[0x1];
369 u8 inner_smac[0x1];
370 u8 inner_ether_type[0x1];
371 u8 inner_ip_version[0x1];
372 u8 inner_first_prio[0x1];
373 u8 inner_first_cfi[0x1];
374 u8 inner_first_vid[0x1];
375 u8 reserved_at_27[0x1];
376 u8 inner_second_prio[0x1];
377 u8 inner_second_cfi[0x1];
378 u8 inner_second_vid[0x1];
379 u8 reserved_at_2b[0x1];
380 u8 inner_sip[0x1];
381 u8 inner_dip[0x1];
382 u8 inner_frag[0x1];
383 u8 inner_ip_protocol[0x1];
384 u8 inner_ip_ecn[0x1];
385 u8 inner_ip_dscp[0x1];
386 u8 inner_udp_sport[0x1];
387 u8 inner_udp_dport[0x1];
388 u8 inner_tcp_sport[0x1];
389 u8 inner_tcp_dport[0x1];
390 u8 inner_tcp_flags[0x1];
391 u8 reserved_at_37[0x9];
393 u8 geneve_tlv_option_0_data[0x1];
394 u8 geneve_tlv_option_0_exist[0x1];
395 u8 reserved_at_42[0x3];
396 u8 outer_first_mpls_over_udp[0x4];
397 u8 outer_first_mpls_over_gre[0x4];
398 u8 inner_first_mpls[0x4];
399 u8 outer_first_mpls[0x4];
400 u8 reserved_at_55[0x2];
401 u8 outer_esp_spi[0x1];
402 u8 reserved_at_58[0x2];
403 u8 bth_dst_qp[0x1];
404 u8 reserved_at_5b[0x5];
406 u8 reserved_at_60[0x18];
407 u8 metadata_reg_c_7[0x1];
408 u8 metadata_reg_c_6[0x1];
409 u8 metadata_reg_c_5[0x1];
410 u8 metadata_reg_c_4[0x1];
411 u8 metadata_reg_c_3[0x1];
412 u8 metadata_reg_c_2[0x1];
413 u8 metadata_reg_c_1[0x1];
414 u8 metadata_reg_c_0[0x1];
419 u8 reserved_at_0[0xe];
420 u8 bth_opcode[0x1];
421 u8 reserved_at_f[0x1];
422 u8 tunnel_header_0_1[0x1];
423 u8 reserved_at_11[0xf];
425 u8 reserved_at_20[0x60];
429 u8 ft_support[0x1];
430 u8 reserved_at_1[0x1];
431 u8 flow_counter[0x1];
432 u8 flow_modify_en[0x1];
433 u8 modify_root[0x1];
434 u8 identified_miss_table_mode[0x1];
435 u8 flow_table_modify[0x1];
436 u8 reformat[0x1];
437 u8 decap[0x1];
438 u8 reset_root_to_default[0x1];
439 u8 pop_vlan[0x1];
440 u8 push_vlan[0x1];
441 u8 reserved_at_c[0x1];
442 u8 pop_vlan_2[0x1];
443 u8 push_vlan_2[0x1];
444 u8 reformat_and_vlan_action[0x1];
445 u8 reserved_at_10[0x1];
446 u8 sw_owner[0x1];
447 u8 reformat_l3_tunnel_to_l2[0x1];
448 u8 reformat_l2_to_l3_tunnel[0x1];
449 u8 reformat_and_modify_action[0x1];
450 u8 ignore_flow_level[0x1];
451 u8 reserved_at_16[0x1];
452 u8 table_miss_action_domain[0x1];
453 u8 termination_table[0x1];
454 u8 reformat_and_fwd_to_table[0x1];
455 u8 reserved_at_1a[0x2];
456 u8 ipsec_encrypt[0x1];
457 u8 ipsec_decrypt[0x1];
458 u8 sw_owner_v2[0x1];
459 u8 reserved_at_1f[0x1];
461 u8 termination_table_raw_traffic[0x1];
462 u8 reserved_at_21[0x1];
463 u8 log_max_ft_size[0x6];
464 u8 log_max_modify_header_context[0x8];
465 u8 max_modify_header_actions[0x8];
466 u8 max_ft_level[0x8];
468 u8 reformat_add_esp_trasport[0x1];
469 u8 reformat_l2_to_l3_esp_tunnel[0x1];
470 u8 reformat_add_esp_transport_over_udp[0x1];
471 u8 reformat_del_esp_trasport[0x1];
472 u8 reformat_l3_esp_tunnel_to_l2[0x1];
473 u8 reformat_del_esp_transport_over_udp[0x1];
474 u8 execute_aso[0x1];
475 u8 reserved_at_47[0x19];
477 u8 reserved_at_60[0x2];
478 u8 reformat_insert[0x1];
479 u8 reformat_remove[0x1];
480 u8 macsec_encrypt[0x1];
481 u8 macsec_decrypt[0x1];
482 u8 reserved_at_66[0x2];
483 u8 reformat_add_macsec[0x1];
484 u8 reformat_remove_macsec[0x1];
485 u8 reserved_at_6a[0xe];
486 u8 log_max_ft_num[0x8];
488 u8 reserved_at_80[0x10];
489 u8 log_max_flow_counter[0x8];
490 u8 log_max_destination[0x8];
492 u8 reserved_at_a0[0x18];
493 u8 log_max_flow[0x8];
495 u8 reserved_at_c0[0x40];
503 u8 send[0x1];
504 u8 receive[0x1];
505 u8 write[0x1];
506 u8 read[0x1];
507 u8 atomic[0x1];
508 u8 srq_receive[0x1];
509 u8 reserved_at_6[0x1a];
513 u8 reserved_at_0[0x60];
515 u8 ipv4[0x20];
519 u8 ipv6[16][0x8];
525 u8 reserved_at_0[0x80];
529 u8 smac_47_16[0x20];
531 u8 smac_15_0[0x10];
532 u8 ethertype[0x10];
534 u8 dmac_47_16[0x20];
536 u8 dmac_15_0[0x10];
537 u8 first_prio[0x3];
538 u8 first_cfi[0x1];
539 u8 first_vid[0xc];
541 u8 ip_protocol[0x8];
542 u8 ip_dscp[0x6];
543 u8 ip_ecn[0x2];
544 u8 cvlan_tag[0x1];
545 u8 svlan_tag[0x1];
546 u8 frag[0x1];
547 u8 ip_version[0x4];
548 u8 tcp_flags[0x9];
550 u8 tcp_sport[0x10];
551 u8 tcp_dport[0x10];
553 u8 reserved_at_c0[0x10];
554 u8 ipv4_ihl[0x4];
555 u8 reserved_at_c4[0x4];
557 u8 ttl_hoplimit[0x8];
559 u8 udp_sport[0x10];
560 u8 udp_dport[0x10];
568 u8 hi[0x18];
569 u8 lo[0x8];
574 u8 key[0x20];
578 u8 gre_c_present[0x1];
579 u8 reserved_at_1[0x1];
580 u8 gre_k_present[0x1];
581 u8 gre_s_present[0x1];
582 u8 source_vhca_port[0x4];
583 u8 source_sqn[0x18];
585 u8 source_eswitch_owner_vhca_id[0x10];
586 u8 source_port[0x10];
588 u8 outer_second_prio[0x3];
589 u8 outer_second_cfi[0x1];
590 u8 outer_second_vid[0xc];
591 u8 inner_second_prio[0x3];
592 u8 inner_second_cfi[0x1];
593 u8 inner_second_vid[0xc];
595 u8 outer_second_cvlan_tag[0x1];
596 u8 inner_second_cvlan_tag[0x1];
597 u8 outer_second_svlan_tag[0x1];
598 u8 inner_second_svlan_tag[0x1];
599 u8 reserved_at_64[0xc];
600 u8 gre_protocol[0x10];
604 u8 vxlan_vni[0x18];
605 u8 bth_opcode[0x8];
607 u8 geneve_vni[0x18];
608 u8 reserved_at_d8[0x6];
609 u8 geneve_tlv_option_0_exist[0x1];
610 u8 geneve_oam[0x1];
612 u8 reserved_at_e0[0xc];
613 u8 outer_ipv6_flow_label[0x14];
615 u8 reserved_at_100[0xc];
616 u8 inner_ipv6_flow_label[0x14];
618 u8 reserved_at_120[0xa];
619 u8 geneve_opt_len[0x6];
620 u8 geneve_protocol_type[0x10];
622 u8 reserved_at_140[0x8];
623 u8 bth_dst_qp[0x18];
624 u8 inner_esp_spi[0x20];
625 u8 outer_esp_spi[0x20];
626 u8 reserved_at_1a0[0x60];
630 u8 mpls_label[0x14];
631 u8 mpls_exp[0x3];
632 u8 mpls_s_bos[0x1];
633 u8 mpls_ttl[0x8];
645 u8 metadata_reg_c_7[0x20];
647 u8 metadata_reg_c_6[0x20];
649 u8 metadata_reg_c_5[0x20];
651 u8 metadata_reg_c_4[0x20];
653 u8 metadata_reg_c_3[0x20];
655 u8 metadata_reg_c_2[0x20];
657 u8 metadata_reg_c_1[0x20];
659 u8 metadata_reg_c_0[0x20];
661 u8 metadata_reg_a[0x20];
663 u8 reserved_at_1a0[0x8];
665 u8 macsec_syndrome[0x8];
666 u8 ipsec_syndrome[0x8];
667 u8 reserved_at_1b8[0x8];
669 u8 reserved_at_1c0[0x40];
673 u8 inner_tcp_seq_num[0x20];
675 u8 outer_tcp_seq_num[0x20];
677 u8 inner_tcp_ack_num[0x20];
679 u8 outer_tcp_ack_num[0x20];
681 u8 reserved_at_80[0x8];
682 u8 outer_vxlan_gpe_vni[0x18];
684 u8 outer_vxlan_gpe_next_protocol[0x8];
685 u8 outer_vxlan_gpe_flags[0x8];
686 u8 reserved_at_b0[0x10];
688 u8 icmp_header_data[0x20];
690 u8 icmpv6_header_data[0x20];
692 u8 icmp_type[0x8];
693 u8 icmp_code[0x8];
694 u8 icmpv6_type[0x8];
695 u8 icmpv6_code[0x8];
697 u8 geneve_tlv_option_0_data[0x20];
699 u8 gtpu_teid[0x20];
701 u8 gtpu_msg_type[0x8];
702 u8 gtpu_msg_flags[0x8];
703 u8 reserved_at_170[0x10];
705 u8 gtpu_dw_2[0x20];
707 u8 gtpu_first_ext_dw_0[0x20];
709 u8 gtpu_dw_0[0x20];
711 u8 reserved_at_1e0[0x20];
715 u8 prog_sample_field_value_0[0x20];
717 u8 prog_sample_field_id_0[0x20];
719 u8 prog_sample_field_value_1[0x20];
721 u8 prog_sample_field_id_1[0x20];
723 u8 prog_sample_field_value_2[0x20];
725 u8 prog_sample_field_id_2[0x20];
727 u8 prog_sample_field_value_3[0x20];
729 u8 prog_sample_field_id_3[0x20];
731 u8 reserved_at_100[0x100];
735 u8 macsec_tag_0[0x20];
737 u8 macsec_tag_1[0x20];
739 u8 macsec_tag_2[0x20];
741 u8 macsec_tag_3[0x20];
743 u8 tunnel_header_0[0x20];
745 u8 tunnel_header_1[0x20];
747 u8 tunnel_header_2[0x20];
749 u8 tunnel_header_3[0x20];
751 u8 reserved_at_100[0x100];
755 u8 pa_h[0x20];
757 u8 pa_l[0x14];
758 u8 reserved_at_34[0xc];
762 u8 hi[0x20];
764 u8 lo[0x20];
768 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
769 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
770 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
771 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
772 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
773 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
774 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
775 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
776 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
777 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
781 u8 fl[0x1];
782 u8 free_ar[0x1];
783 u8 reserved_at_2[0xe];
784 u8 pkey_index[0x10];
786 u8 reserved_at_20[0x8];
787 u8 grh[0x1];
788 u8 mlid[0x7];
789 u8 rlid[0x10];
791 u8 ack_timeout[0x5];
792 u8 reserved_at_45[0x3];
793 u8 src_addr_index[0x8];
794 u8 reserved_at_50[0x4];
795 u8 stat_rate[0x4];
796 u8 hop_limit[0x8];
798 u8 reserved_at_60[0x4];
799 u8 tclass[0x8];
800 u8 flow_label[0x14];
802 u8 rgid_rip[16][0x8];
804 u8 reserved_at_100[0x4];
805 u8 f_dscp[0x1];
806 u8 f_ecn[0x1];
807 u8 reserved_at_106[0x1];
808 u8 f_eth_prio[0x1];
809 u8 ecn[0x2];
810 u8 dscp[0x6];
811 u8 udp_sport[0x10];
813 u8 dei_cfi[0x1];
814 u8 eth_prio[0x3];
815 u8 sl[0x4];
816 u8 vhca_port_num[0x8];
817 u8 rmac_47_32[0x10];
819 u8 rmac_31_0[0x20];
823 u8 nic_rx_multi_path_tirs[0x1];
824 u8 nic_rx_multi_path_tirs_fts[0x1];
825 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
826 u8 reserved_at_3[0x4];
827 u8 sw_owner_reformat_supported[0x1];
828 u8 reserved_at_8[0x18];
830 u8 encap_general_header[0x1];
831 u8 reserved_at_21[0xa];
832 u8 log_max_packet_reformat_context[0x5];
833 u8 reserved_at_30[0x6];
834 u8 max_encap_header_size[0xa];
835 u8 reserved_at_40[0x1c0];
849 u8 reserved_at_e00[0x700];
853 u8 reserved_at_1580[0x280];
857 u8 reserved_at_1880[0x780];
859 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
861 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
863 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
865 u8 reserved_at_20c0[0x5f40];
869 u8 reserved_at_0[0x10];
870 u8 port_select_flow_table[0x1];
871 u8 reserved_at_11[0x1];
872 u8 port_select_flow_table_bypass[0x1];
873 u8 reserved_at_13[0xd];
875 u8 reserved_at_20[0x1e0];
879 u8 reserved_at_400[0x7c00];
883 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
884 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
885 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
886 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
887 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
888 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
889 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
890 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
894 u8 fdb_to_vport_reg_c_id[0x8];
895 u8 reserved_at_8[0x5];
896 u8 fdb_uplink_hairpin[0x1];
897 u8 fdb_multi_path_any_table_limit_regc[0x1];
898 u8 reserved_at_f[0x3];
899 u8 fdb_multi_path_any_table[0x1];
900 u8 reserved_at_13[0x2];
901 u8 fdb_modify_header_fwd_to_table[0x1];
902 u8 fdb_ipv4_ttl_modify[0x1];
903 u8 flow_source[0x1];
904 u8 reserved_at_18[0x2];
905 u8 multi_fdb_encap[0x1];
906 u8 egress_acl_forward_to_vport[0x1];
907 u8 fdb_multi_path_to_table[0x1];
908 u8 reserved_at_1d[0x3];
910 u8 reserved_at_20[0x1e0];
918 u8 reserved_at_800[0xC00];
924 u8 reserved_at_1500[0x300];
926 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
928 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
930 u8 sw_steering_uplink_icm_address_rx[0x40];
932 u8 sw_steering_uplink_icm_address_tx[0x40];
934 u8 reserved_at_1900[0x6700];
938 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
939 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
943 u8 vport_svlan_strip[0x1];
944 u8 vport_cvlan_strip[0x1];
945 u8 vport_svlan_insert[0x1];
946 u8 vport_cvlan_insert_if_not_exist[0x1];
947 u8 vport_cvlan_insert_overwrite[0x1];
948 u8 reserved_at_5[0x1];
949 u8 vport_cvlan_insert_always[0x1];
950 u8 esw_shared_ingress_acl[0x1];
951 u8 esw_uplink_ingress_acl[0x1];
952 u8 root_ft_on_other_esw[0x1];
953 u8 reserved_at_a[0xf];
954 u8 esw_functions_changed[0x1];
955 u8 reserved_at_1a[0x1];
956 u8 ecpf_vport_exists[0x1];
957 u8 counter_eswitch_affinity[0x1];
958 u8 merged_eswitch[0x1];
959 u8 nic_vport_node_guid_modify[0x1];
960 u8 nic_vport_port_guid_modify[0x1];
962 u8 vxlan_encap_decap[0x1];
963 u8 nvgre_encap_decap[0x1];
964 u8 reserved_at_22[0x1];
965 u8 log_max_fdb_encap_uplink[0x5];
966 u8 reserved_at_21[0x3];
967 u8 log_max_packet_reformat_context[0x5];
968 u8 reserved_2b[0x6];
969 u8 max_encap_header_size[0xa];
971 u8 reserved_at_40[0xb];
972 u8 log_max_esw_sf[0x5];
973 u8 esw_sf_base_id[0x10];
975 u8 reserved_at_60[0x7a0];
980 u8 packet_pacing[0x1];
981 u8 esw_scheduling[0x1];
982 u8 esw_bw_share[0x1];
983 u8 esw_rate_limit[0x1];
984 u8 reserved_at_4[0x1];
985 u8 packet_pacing_burst_bound[0x1];
986 u8 packet_pacing_typical_size[0x1];
987 u8 reserved_at_7[0x1];
988 u8 nic_sq_scheduling[0x1];
989 u8 nic_bw_share[0x1];
990 u8 nic_rate_limit[0x1];
991 u8 packet_pacing_uid[0x1];
992 u8 log_esw_max_sched_depth[0x4];
993 u8 reserved_at_10[0x10];
995 u8 reserved_at_20[0xb];
996 u8 log_max_qos_nic_queue_group[0x5];
997 u8 reserved_at_30[0x10];
999 u8 packet_pacing_max_rate[0x20];
1001 u8 packet_pacing_min_rate[0x20];
1003 u8 reserved_at_80[0x10];
1004 u8 packet_pacing_rate_table_size[0x10];
1006 u8 esw_element_type[0x10];
1007 u8 esw_tsar_type[0x10];
1009 u8 reserved_at_c0[0x10];
1010 u8 max_qos_para_vport[0x10];
1012 u8 max_tsar_bw_share[0x20];
1014 u8 reserved_at_100[0x20];
1016 u8 reserved_at_120[0x3];
1017 u8 log_meter_aso_granularity[0x5];
1018 u8 reserved_at_128[0x3];
1019 u8 log_meter_aso_max_alloc[0x5];
1020 u8 reserved_at_130[0x3];
1021 u8 log_max_num_meter_aso[0x5];
1022 u8 reserved_at_138[0x8];
1024 u8 reserved_at_140[0x6c0];
1028 u8 core_dump_general[0x1];
1029 u8 core_dump_qp[0x1];
1030 u8 reserved_at_2[0x7];
1031 u8 resource_dump[0x1];
1032 u8 reserved_at_a[0x16];
1034 u8 reserved_at_20[0x2];
1035 u8 stall_detect[0x1];
1036 u8 reserved_at_23[0x1d];
1038 u8 reserved_at_40[0x7c0];
1042 u8 csum_cap[0x1];
1043 u8 vlan_cap[0x1];
1044 u8 lro_cap[0x1];
1045 u8 lro_psh_flag[0x1];
1046 u8 lro_time_stamp[0x1];
1047 u8 reserved_at_5[0x2];
1048 u8 wqe_vlan_insert[0x1];
1049 u8 self_lb_en_modifiable[0x1];
1050 u8 reserved_at_9[0x2];
1051 u8 max_lso_cap[0x5];
1052 u8 multi_pkt_send_wqe[0x2];
1053 u8 wqe_inline_mode[0x2];
1054 u8 rss_ind_tbl_cap[0x4];
1055 u8 reg_umr_sq[0x1];
1056 u8 scatter_fcs[0x1];
1057 u8 enhanced_multi_pkt_send_wqe[0x1];
1058 u8 tunnel_lso_const_out_ip_id[0x1];
1059 u8 tunnel_lro_gre[0x1];
1060 u8 tunnel_lro_vxlan[0x1];
1061 u8 tunnel_stateless_gre[0x1];
1062 u8 tunnel_stateless_vxlan[0x1];
1064 u8 swp[0x1];
1065 u8 swp_csum[0x1];
1066 u8 swp_lso[0x1];
1067 u8 cqe_checksum_full[0x1];
1068 u8 tunnel_stateless_geneve_tx[0x1];
1069 u8 tunnel_stateless_mpls_over_udp[0x1];
1070 u8 tunnel_stateless_mpls_over_gre[0x1];
1071 u8 tunnel_stateless_vxlan_gpe[0x1];
1072 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
1073 u8 tunnel_stateless_ip_over_ip[0x1];
1074 u8 insert_trailer[0x1];
1075 u8 reserved_at_2b[0x1];
1076 u8 tunnel_stateless_ip_over_ip_rx[0x1];
1077 u8 tunnel_stateless_ip_over_ip_tx[0x1];
1078 u8 reserved_at_2e[0x2];
1079 u8 max_vxlan_udp_ports[0x8];
1080 u8 reserved_at_38[0x6];
1081 u8 max_geneve_opt_len[0x1];
1082 u8 tunnel_stateless_geneve_rx[0x1];
1084 u8 reserved_at_40[0x10];
1085 u8 lro_min_mss_size[0x10];
1087 u8 reserved_at_60[0x120];
1089 u8 lro_timer_supported_periods[4][0x20];
1091 u8 reserved_at_200[0x600];
1095 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1096 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1097 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1101 u8 roce_apm[0x1];
1102 u8 reserved_at_1[0x3];
1103 u8 sw_r_roce_src_udp_port[0x1];
1104 u8 fl_rc_qp_when_roce_disabled[0x1];
1105 u8 fl_rc_qp_when_roce_enabled[0x1];
1106 u8 roce_cc_general[0x1];
1107 u8 qp_ooo_transmit_default[0x1];
1108 u8 reserved_at_9[0x15];
1109 u8 qp_ts_format[0x2];
1111 u8 reserved_at_20[0x60];
1113 u8 reserved_at_80[0xc];
1114 u8 l3_type[0x4];
1115 u8 reserved_at_90[0x8];
1116 u8 roce_version[0x8];
1118 u8 reserved_at_a0[0x10];
1119 u8 r_roce_dest_udp_port[0x10];
1121 u8 r_roce_max_src_udp_port[0x10];
1122 u8 r_roce_min_src_udp_port[0x10];
1124 u8 reserved_at_e0[0x10];
1125 u8 roce_address_table_size[0x10];
1127 u8 reserved_at_100[0x700];
1131 u8 opcode[0x10];
1132 u8 uid[0x10];
1134 u8 reserved_at_20[0x10];
1135 u8 op_mod[0x10];
1137 u8 reserved_at_40[0xc0];
1141 u8 status[0x8];
1142 u8 reserved_at_8[0x18];
1144 u8 syndrome[0x20];
1146 u8 reserved_at_40[0x40];
1150 u8 opcode[0x10];
1151 u8 uid[0x10];
1153 u8 reserved_at_20[0x10];
1154 u8 op_mod[0x10];
1156 u8 reserved_at_40[0x20];
1158 u8 reserved_at_60[0x10];
1159 u8 crypto_type[0x10];
1161 u8 reserved_at_80[0x80];
1165 u8 status[0x8];
1166 u8 reserved_at_8[0x18];
1168 u8 syndrome[0x20];
1170 u8 reserved_at_40[0x40];
1174 u8 memic[0x1];
1175 u8 reserved_at_1[0x1f];
1177 u8 reserved_at_20[0xb];
1178 u8 log_min_memic_alloc_size[0x5];
1179 u8 reserved_at_30[0x8];
1180 u8 log_max_memic_addr_alignment[0x8];
1182 u8 memic_bar_start_addr[0x40];
1184 u8 memic_bar_size[0x20];
1186 u8 max_memic_size[0x20];
1188 u8 steering_sw_icm_start_address[0x40];
1190 u8 reserved_at_100[0x8];
1191 u8 log_header_modify_sw_icm_size[0x8];
1192 u8 reserved_at_110[0x2];
1193 u8 log_sw_icm_alloc_granularity[0x6];
1194 u8 log_steering_sw_icm_size[0x8];
1196 u8 log_indirect_encap_sw_icm_size[0x8];
1197 u8 reserved_at_128[0x10];
1198 u8 log_header_modify_pattern_sw_icm_size[0x8];
1200 u8 header_modify_sw_icm_start_address[0x40];
1202 u8 reserved_at_180[0x40];
1204 u8 header_modify_pattern_sw_icm_start_address[0x40];
1206 u8 memic_operations[0x20];
1208 u8 reserved_at_220[0x20];
1210 u8 indirect_encap_sw_icm_start_address[0x40];
1212 u8 reserved_at_280[0x580];
1216 u8 user_affiliated_events[4][0x40];
1218 u8 user_unaffiliated_events[4][0x40];
1222 u8 desc_tunnel_offload_type[0x1];
1223 u8 eth_frame_offload_type[0x1];
1224 u8 virtio_version_1_0[0x1];
1225 u8 device_features_bits_mask[0xd];
1226 u8 event_mode[0x8];
1227 u8 virtio_queue_type[0x8];
1229 u8 max_tunnel_desc[0x10];
1230 u8 reserved_at_30[0x3];
1231 u8 log_doorbell_stride[0x5];
1232 u8 reserved_at_38[0x3];
1233 u8 log_doorbell_bar_size[0x5];
1235 u8 doorbell_bar_offset[0x40];
1237 u8 max_emulated_devices[0x8];
1238 u8 max_num_virtio_queues[0x18];
1240 u8 reserved_at_a0[0x20];
1242 u8 reserved_at_c0[0x13];
1243 u8 desc_group_mkey_supported[0x1];
1244 u8 freeze_to_rdy_supported[0x1];
1245 u8 reserved_at_d5[0xb];
1247 u8 reserved_at_e0[0x20];
1249 u8 umem_1_buffer_param_a[0x20];
1251 u8 umem_1_buffer_param_b[0x20];
1253 u8 umem_2_buffer_param_a[0x20];
1255 u8 umem_2_buffer_param_b[0x20];
1257 u8 umem_3_buffer_param_a[0x20];
1259 u8 umem_3_buffer_param_b[0x20];
1261 u8 reserved_at_1c0[0x640];
1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1268 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1269 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1270 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1271 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1272 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1273 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1277 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1278 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1279 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1280 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1281 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1282 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1283 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1284 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1285 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1289 u8 reserved_at_0[0x40];
1291 u8 atomic_req_8B_endianness_mode[0x2];
1292 u8 reserved_at_42[0x4];
1293 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1295 u8 reserved_at_47[0x19];
1297 u8 reserved_at_60[0x20];
1299 u8 reserved_at_80[0x10];
1300 u8 atomic_operations[0x10];
1302 u8 reserved_at_a0[0x10];
1303 u8 atomic_size_qp[0x10];
1305 u8 reserved_at_c0[0x10];
1306 u8 atomic_size_dc[0x10];
1308 u8 reserved_at_e0[0x720];
1312 u8 reserved_at_0[0x40];
1314 u8 sig[0x1];
1315 u8 reserved_at_41[0x1f];
1317 u8 reserved_at_60[0x20];
1329 u8 reserved_at_120[0x6E0];
1333 u8 tls_1_2_aes_gcm_128[0x1];
1334 u8 tls_1_3_aes_gcm_128[0x1];
1335 u8 tls_1_2_aes_gcm_256[0x1];
1336 u8 tls_1_3_aes_gcm_256[0x1];
1337 u8 reserved_at_4[0x1c];
1339 u8 reserved_at_20[0x7e0];
1343 u8 ipsec_full_offload[0x1];
1344 u8 ipsec_crypto_offload[0x1];
1345 u8 ipsec_esn[0x1];
1346 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1347 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1348 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1349 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1350 u8 reserved_at_7[0x4];
1351 u8 log_max_ipsec_offload[0x5];
1352 u8 reserved_at_10[0x10];
1354 u8 min_log_ipsec_full_replay_window[0x8];
1355 u8 max_log_ipsec_full_replay_window[0x8];
1356 u8 reserved_at_30[0x7d0];
1360 u8 macsec_epn[0x1];
1361 u8 reserved_at_1[0x2];
1362 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1363 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1364 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1365 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1366 u8 reserved_at_7[0x4];
1367 u8 log_max_macsec_offload[0x5];
1368 u8 reserved_at_10[0x10];
1370 u8 min_log_macsec_full_replay_window[0x8];
1371 u8 max_log_macsec_full_replay_window[0x8];
1372 u8 reserved_at_30[0x10];
1374 u8 reserved_at_40[0x7c0];
1378 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1379 MLX5_WQ_TYPE_CYCLIC = 0x1,
1380 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1381 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1385 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1386 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1390 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1391 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1392 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1393 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1394 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1398 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1399 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1400 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1401 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1402 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1403 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1407 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1408 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1412 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1413 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1414 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1418 MLX5_CAP_PORT_TYPE_IB = 0x0,
1419 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1423 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1424 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1425 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1444 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1451 MLX5_FC_BULK_128 = (1 << 0),
1466 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1472 u8 reserved_at_0[0x10];
1473 u8 shared_object_to_user_object_allowed[0x1];
1474 u8 reserved_at_13[0xe];
1475 u8 vhca_resource_manager[0x1];
1477 u8 hca_cap_2[0x1];
1478 u8 create_lag_when_not_master_up[0x1];
1479 u8 dtor[0x1];
1480 u8 event_on_vhca_state_teardown_request[0x1];
1481 u8 event_on_vhca_state_in_use[0x1];
1482 u8 event_on_vhca_state_active[0x1];
1483 u8 event_on_vhca_state_allocated[0x1];
1484 u8 event_on_vhca_state_invalid[0x1];
1485 u8 reserved_at_28[0x8];
1486 u8 vhca_id[0x10];
1488 u8 reserved_at_40[0x40];
1490 u8 log_max_srq_sz[0x8];
1491 u8 log_max_qp_sz[0x8];
1492 u8 event_cap[0x1];
1493 u8 reserved_at_91[0x2];
1494 u8 isolate_vl_tc_new[0x1];
1495 u8 reserved_at_94[0x4];
1496 u8 prio_tag_required[0x1];
1497 u8 reserved_at_99[0x2];
1498 u8 log_max_qp[0x5];
1500 u8 reserved_at_a0[0x3];
1501 u8 ece_support[0x1];
1502 u8 reserved_at_a4[0x5];
1503 u8 reg_c_preserve[0x1];
1504 u8 reserved_at_aa[0x1];
1505 u8 log_max_srq[0x5];
1506 u8 reserved_at_b0[0x1];
1507 u8 uplink_follow[0x1];
1508 u8 ts_cqe_to_dest_cqn[0x1];
1509 u8 reserved_at_b3[0x6];
1510 u8 go_back_n[0x1];
1511 u8 shampo[0x1];
1512 u8 reserved_at_bb[0x5];
1514 u8 max_sgl_for_optimized_performance[0x8];
1515 u8 log_max_cq_sz[0x8];
1516 u8 relaxed_ordering_write_umr[0x1];
1517 u8 relaxed_ordering_read_umr[0x1];
1518 u8 reserved_at_d2[0x7];
1519 u8 virtio_net_device_emualtion_manager[0x1];
1520 u8 virtio_blk_device_emualtion_manager[0x1];
1521 u8 log_max_cq[0x5];
1523 u8 log_max_eq_sz[0x8];
1524 u8 relaxed_ordering_write[0x1];
1525 u8 relaxed_ordering_read_pci_enabled[0x1];
1526 u8 log_max_mkey[0x6];
1527 u8 reserved_at_f0[0x6];
1528 u8 terminate_scatter_list_mkey[0x1];
1529 u8 repeated_mkey[0x1];
1530 u8 dump_fill_mkey[0x1];
1531 u8 reserved_at_f9[0x2];
1532 u8 fast_teardown[0x1];
1533 u8 log_max_eq[0x4];
1535 u8 max_indirection[0x8];
1536 u8 fixed_buffer_size[0x1];
1537 u8 log_max_mrw_sz[0x7];
1538 u8 force_teardown[0x1];
1539 u8 reserved_at_111[0x1];
1540 u8 log_max_bsf_list_size[0x6];
1541 u8 umr_extended_translation_offset[0x1];
1542 u8 null_mkey[0x1];
1543 u8 log_max_klm_list_size[0x6];
1545 u8 reserved_at_120[0x2];
1546 u8 qpc_extension[0x1];
1547 u8 reserved_at_123[0x7];
1548 u8 log_max_ra_req_dc[0x6];
1549 u8 reserved_at_130[0x2];
1550 u8 eth_wqe_too_small[0x1];
1551 u8 reserved_at_133[0x6];
1552 u8 vnic_env_cq_overrun[0x1];
1553 u8 log_max_ra_res_dc[0x6];
1555 u8 reserved_at_140[0x5];
1556 u8 release_all_pages[0x1];
1557 u8 must_not_use[0x1];
1558 u8 reserved_at_147[0x2];
1559 u8 roce_accl[0x1];
1560 u8 log_max_ra_req_qp[0x6];
1561 u8 reserved_at_150[0xa];
1562 u8 log_max_ra_res_qp[0x6];
1564 u8 end_pad[0x1];
1565 u8 cc_query_allowed[0x1];
1566 u8 cc_modify_allowed[0x1];
1567 u8 start_pad[0x1];
1568 u8 cache_line_128byte[0x1];
1569 u8 reserved_at_165[0x4];
1570 u8 rts2rts_qp_counters_set_id[0x1];
1571 u8 reserved_at_16a[0x2];
1572 u8 vnic_env_int_rq_oob[0x1];
1573 u8 sbcam_reg[0x1];
1574 u8 reserved_at_16e[0x1];
1575 u8 qcam_reg[0x1];
1576 u8 gid_table_size[0x10];
1578 u8 out_of_seq_cnt[0x1];
1579 u8 vport_counters[0x1];
1580 u8 retransmission_q_counters[0x1];
1581 u8 debug[0x1];
1582 u8 modify_rq_counter_set_id[0x1];
1583 u8 rq_delay_drop[0x1];
1584 u8 max_qp_cnt[0xa];
1585 u8 pkey_table_size[0x10];
1587 u8 vport_group_manager[0x1];
1588 u8 vhca_group_manager[0x1];
1589 u8 ib_virt[0x1];
1590 u8 eth_virt[0x1];
1591 u8 vnic_env_queue_counters[0x1];
1592 u8 ets[0x1];
1593 u8 nic_flow_table[0x1];
1594 u8 eswitch_manager[0x1];
1595 u8 device_memory[0x1];
1596 u8 mcam_reg[0x1];
1597 u8 pcam_reg[0x1];
1598 u8 local_ca_ack_delay[0x5];
1599 u8 port_module_event[0x1];
1600 u8 enhanced_error_q_counters[0x1];
1601 u8 ports_check[0x1];
1602 u8 reserved_at_1b3[0x1];
1603 u8 disable_link_up[0x1];
1604 u8 beacon_led[0x1];
1605 u8 port_type[0x2];
1606 u8 num_ports[0x8];
1608 u8 reserved_at_1c0[0x1];
1609 u8 pps[0x1];
1610 u8 pps_modify[0x1];
1611 u8 log_max_msg[0x5];
1612 u8 reserved_at_1c8[0x4];
1613 u8 max_tc[0x4];
1614 u8 temp_warn_event[0x1];
1615 u8 dcbx[0x1];
1616 u8 general_notification_event[0x1];
1617 u8 reserved_at_1d3[0x2];
1618 u8 fpga[0x1];
1619 u8 rol_s[0x1];
1620 u8 rol_g[0x1];
1621 u8 reserved_at_1d8[0x1];
1622 u8 wol_s[0x1];
1623 u8 wol_g[0x1];
1624 u8 wol_a[0x1];
1625 u8 wol_b[0x1];
1626 u8 wol_m[0x1];
1627 u8 wol_u[0x1];
1628 u8 wol_p[0x1];
1630 u8 stat_rate_support[0x10];
1631 u8 reserved_at_1f0[0x1];
1632 u8 pci_sync_for_fw_update_event[0x1];
1633 u8 reserved_at_1f2[0x6];
1634 u8 init2_lag_tx_port_affinity[0x1];
1635 u8 reserved_at_1fa[0x3];
1636 u8 cqe_version[0x4];
1638 u8 compact_address_vector[0x1];
1639 u8 striding_rq[0x1];
1640 u8 reserved_at_202[0x1];
1641 u8 ipoib_enhanced_offloads[0x1];
1642 u8 ipoib_basic_offloads[0x1];
1643 u8 reserved_at_205[0x1];
1644 u8 repeated_block_disabled[0x1];
1645 u8 umr_modify_entity_size_disabled[0x1];
1646 u8 umr_modify_atomic_disabled[0x1];
1647 u8 umr_indirect_mkey_disabled[0x1];
1648 u8 umr_fence[0x2];
1649 u8 dc_req_scat_data_cqe[0x1];
1650 u8 reserved_at_20d[0x2];
1651 u8 drain_sigerr[0x1];
1652 u8 cmdif_checksum[0x2];
1653 u8 sigerr_cqe[0x1];
1654 u8 reserved_at_213[0x1];
1655 u8 wq_signature[0x1];
1656 u8 sctr_data_cqe[0x1];
1657 u8 reserved_at_216[0x1];
1658 u8 sho[0x1];
1659 u8 tph[0x1];
1660 u8 rf[0x1];
1661 u8 dct[0x1];
1662 u8 qos[0x1];
1663 u8 eth_net_offloads[0x1];
1664 u8 roce[0x1];
1665 u8 atomic[0x1];
1666 u8 reserved_at_21f[0x1];
1668 u8 cq_oi[0x1];
1669 u8 cq_resize[0x1];
1670 u8 cq_moderation[0x1];
1671 u8 reserved_at_223[0x3];
1672 u8 cq_eq_remap[0x1];
1673 u8 pg[0x1];
1674 u8 block_lb_mc[0x1];
1675 u8 reserved_at_229[0x1];
1676 u8 scqe_break_moderation[0x1];
1677 u8 cq_period_start_from_cqe[0x1];
1678 u8 cd[0x1];
1679 u8 reserved_at_22d[0x1];
1680 u8 apm[0x1];
1681 u8 vector_calc[0x1];
1682 u8 umr_ptr_rlky[0x1];
1683 u8 imaicl[0x1];
1684 u8 qp_packet_based[0x1];
1685 u8 reserved_at_233[0x3];
1686 u8 qkv[0x1];
1687 u8 pkv[0x1];
1688 u8 set_deth_sqpn[0x1];
1689 u8 reserved_at_239[0x3];
1690 u8 xrc[0x1];
1691 u8 ud[0x1];
1692 u8 uc[0x1];
1693 u8 rc[0x1];
1695 u8 uar_4k[0x1];
1696 u8 reserved_at_241[0x7];
1697 u8 fl_rc_qp_when_roce_disabled[0x1];
1698 u8 regexp_params[0x1];
1699 u8 uar_sz[0x6];
1700 u8 port_selection_cap[0x1];
1701 u8 reserved_at_251[0x1];
1702 u8 umem_uid_0[0x1];
1703 u8 reserved_at_253[0x5];
1704 u8 log_pg_sz[0x8];
1706 u8 bf[0x1];
1707 u8 driver_version[0x1];
1708 u8 pad_tx_eth_packet[0x1];
1709 u8 reserved_at_263[0x3];
1710 u8 mkey_by_name[0x1];
1711 u8 reserved_at_267[0x4];
1713 u8 log_bf_reg_size[0x5];
1715 u8 reserved_at_270[0x3];
1716 u8 qp_error_syndrome[0x1];
1717 u8 reserved_at_274[0x2];
1718 u8 lag_dct[0x2];
1719 u8 lag_tx_port_affinity[0x1];
1720 u8 lag_native_fdb_selection[0x1];
1721 u8 reserved_at_27a[0x1];
1722 u8 lag_master[0x1];
1723 u8 num_lag_ports[0x4];
1725 u8 reserved_at_280[0x10];
1726 u8 max_wqe_sz_sq[0x10];
1728 u8 reserved_at_2a0[0x10];
1729 u8 max_wqe_sz_rq[0x10];
1731 u8 max_flow_counter_31_16[0x10];
1732 u8 max_wqe_sz_sq_dc[0x10];
1734 u8 reserved_at_2e0[0x7];
1735 u8 max_qp_mcg[0x19];
1737 u8 reserved_at_300[0x10];
1738 u8 flow_counter_bulk_alloc[0x8];
1739 u8 log_max_mcg[0x8];
1741 u8 reserved_at_320[0x3];
1742 u8 log_max_transport_domain[0x5];
1743 u8 reserved_at_328[0x2];
1744 u8 relaxed_ordering_read[0x1];
1745 u8 log_max_pd[0x5];
1746 u8 reserved_at_330[0x6];
1747 u8 pci_sync_for_fw_update_with_driver_unload[0x1];
1748 u8 vnic_env_cnt_steering_fail[0x1];
1749 u8 vport_counter_local_loopback[0x1];
1750 u8 q_counter_aggregation[0x1];
1751 u8 q_counter_other_vport[0x1];
1752 u8 log_max_xrcd[0x5];
1754 u8 nic_receive_steering_discard[0x1];
1755 u8 receive_discard_vport_down[0x1];
1756 u8 transmit_discard_vport_down[0x1];
1757 u8 eq_overrun_count[0x1];
1758 u8 reserved_at_344[0x1];
1759 u8 invalid_command_count[0x1];
1760 u8 quota_exceeded_count[0x1];
1761 u8 reserved_at_347[0x1];
1762 u8 log_max_flow_counter_bulk[0x8];
1763 u8 max_flow_counter_15_0[0x10];
1766 u8 reserved_at_360[0x3];
1767 u8 log_max_rq[0x5];
1768 u8 reserved_at_368[0x3];
1769 u8 log_max_sq[0x5];
1770 u8 reserved_at_370[0x3];
1771 u8 log_max_tir[0x5];
1772 u8 reserved_at_378[0x3];
1773 u8 log_max_tis[0x5];
1775 u8 basic_cyclic_rcv_wqe[0x1];
1776 u8 reserved_at_381[0x2];
1777 u8 log_max_rmp[0x5];
1778 u8 reserved_at_388[0x3];
1779 u8 log_max_rqt[0x5];
1780 u8 reserved_at_390[0x3];
1781 u8 log_max_rqt_size[0x5];
1782 u8 reserved_at_398[0x3];
1783 u8 log_max_tis_per_sq[0x5];
1785 u8 ext_stride_num_range[0x1];
1786 u8 roce_rw_supported[0x1];
1787 u8 log_max_current_uc_list_wr_supported[0x1];
1788 u8 log_max_stride_sz_rq[0x5];
1789 u8 reserved_at_3a8[0x3];
1790 u8 log_min_stride_sz_rq[0x5];
1791 u8 reserved_at_3b0[0x3];
1792 u8 log_max_stride_sz_sq[0x5];
1793 u8 reserved_at_3b8[0x3];
1794 u8 log_min_stride_sz_sq[0x5];
1796 u8 hairpin[0x1];
1797 u8 reserved_at_3c1[0x2];
1798 u8 log_max_hairpin_queues[0x5];
1799 u8 reserved_at_3c8[0x3];
1800 u8 log_max_hairpin_wq_data_sz[0x5];
1801 u8 reserved_at_3d0[0x3];
1802 u8 log_max_hairpin_num_packets[0x5];
1803 u8 reserved_at_3d8[0x3];
1804 u8 log_max_wq_sz[0x5];
1806 u8 nic_vport_change_event[0x1];
1807 u8 disable_local_lb_uc[0x1];
1808 u8 disable_local_lb_mc[0x1];
1809 u8 log_min_hairpin_wq_data_sz[0x5];
1810 u8 reserved_at_3e8[0x1];
1811 u8 silent_mode[0x1];
1812 u8 vhca_state[0x1];
1813 u8 log_max_vlan_list[0x5];
1814 u8 reserved_at_3f0[0x3];
1815 u8 log_max_current_mc_list[0x5];
1816 u8 reserved_at_3f8[0x3];
1817 u8 log_max_current_uc_list[0x5];
1819 u8 general_obj_types[0x40];
1821 u8 sq_ts_format[0x2];
1822 u8 rq_ts_format[0x2];
1823 u8 steering_format_version[0x4];
1824 u8 create_qp_start_hint[0x18];
1826 u8 reserved_at_460[0x1];
1827 u8 ats[0x1];
1828 u8 cross_vhca_rqt[0x1];
1829 u8 log_max_uctx[0x5];
1830 u8 reserved_at_468[0x1];
1831 u8 crypto[0x1];
1832 u8 ipsec_offload[0x1];
1833 u8 log_max_umem[0x5];
1834 u8 max_num_eqs[0x10];
1836 u8 reserved_at_480[0x1];
1837 u8 tls_tx[0x1];
1838 u8 tls_rx[0x1];
1839 u8 log_max_l2_table[0x5];
1840 u8 reserved_at_488[0x8];
1841 u8 log_uar_page_sz[0x10];
1843 u8 reserved_at_4a0[0x20];
1844 u8 device_frequency_mhz[0x20];
1845 u8 device_frequency_khz[0x20];
1847 u8 reserved_at_500[0x20];
1848 u8 num_of_uars_per_page[0x20];
1850 u8 flex_parser_protocols[0x20];
1852 u8 max_geneve_tlv_options[0x8];
1853 u8 reserved_at_568[0x3];
1854 u8 max_geneve_tlv_option_data_len[0x5];
1855 u8 reserved_at_570[0x9];
1856 u8 adv_virtualization[0x1];
1857 u8 reserved_at_57a[0x6];
1859 u8 reserved_at_580[0xb];
1860 u8 log_max_dci_stream_channels[0x5];
1861 u8 reserved_at_590[0x3];
1862 u8 log_max_dci_errored_streams[0x5];
1863 u8 reserved_at_598[0x8];
1865 u8 reserved_at_5a0[0x10];
1866 u8 enhanced_cqe_compression[0x1];
1867 u8 reserved_at_5b1[0x2];
1868 u8 log_max_dek[0x5];
1869 u8 reserved_at_5b8[0x4];
1870 u8 mini_cqe_resp_stride_index[0x1];
1871 u8 cqe_128_always[0x1];
1872 u8 cqe_compression_128[0x1];
1873 u8 cqe_compression[0x1];
1875 u8 cqe_compression_timeout[0x10];
1876 u8 cqe_compression_max_num[0x10];
1878 u8 reserved_at_5e0[0x8];
1879 u8 flex_parser_id_gtpu_dw_0[0x4];
1880 u8 reserved_at_5ec[0x4];
1881 u8 tag_matching[0x1];
1882 u8 rndv_offload_rc[0x1];
1883 u8 rndv_offload_dc[0x1];
1884 u8 log_tag_matching_list_sz[0x5];
1885 u8 reserved_at_5f8[0x3];
1886 u8 log_max_xrq[0x5];
1888 u8 affiliate_nic_vport_criteria[0x8];
1889 u8 native_port_num[0x8];
1890 u8 num_vhca_ports[0x8];
1891 u8 flex_parser_id_gtpu_teid[0x4];
1892 u8 reserved_at_61c[0x2];
1893 u8 sw_owner_id[0x1];
1894 u8 reserved_at_61f[0x1];
1896 u8 max_num_of_monitor_counters[0x10];
1897 u8 num_ppcnt_monitor_counters[0x10];
1899 u8 max_num_sf[0x10];
1900 u8 num_q_monitor_counters[0x10];
1902 u8 reserved_at_660[0x20];
1904 u8 sf[0x1];
1905 u8 sf_set_partition[0x1];
1906 u8 reserved_at_682[0x1];
1907 u8 log_max_sf[0x5];
1908 u8 apu[0x1];
1909 u8 reserved_at_689[0x4];
1910 u8 migration[0x1];
1911 u8 reserved_at_68e[0x2];
1912 u8 log_min_sf_size[0x8];
1913 u8 max_num_sf_partitions[0x8];
1915 u8 uctx_cap[0x20];
1917 u8 reserved_at_6c0[0x4];
1918 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1919 u8 flex_parser_id_icmp_dw1[0x4];
1920 u8 flex_parser_id_icmp_dw0[0x4];
1921 u8 flex_parser_id_icmpv6_dw1[0x4];
1922 u8 flex_parser_id_icmpv6_dw0[0x4];
1923 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1924 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1926 u8 max_num_match_definer[0x10];
1927 u8 sf_base_id[0x10];
1929 u8 flex_parser_id_gtpu_dw_2[0x4];
1930 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
1931 u8 num_total_dynamic_vf_msix[0x18];
1932 u8 reserved_at_720[0x14];
1933 u8 dynamic_msix_table_size[0xc];
1934 u8 reserved_at_740[0xc];
1935 u8 min_dynamic_vf_msix_table_size[0x4];
1936 u8 reserved_at_750[0x4];
1937 u8 max_dynamic_vf_msix_table_size[0xc];
1939 u8 reserved_at_760[0x3];
1940 u8 log_max_num_header_modify_argument[0x5];
1941 u8 reserved_at_768[0x4];
1942 u8 log_header_modify_argument_granularity[0x4];
1943 u8 reserved_at_770[0x3];
1944 u8 log_header_modify_argument_max_alloc[0x5];
1945 u8 reserved_at_778[0x8];
1947 u8 vhca_tunnel_commands[0x40];
1948 u8 match_definer_format_supported[0x40];
1952 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000,
1957 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200,
1961 u8 reserved_at_0[0x80];
1963 u8 migratable[0x1];
1964 u8 reserved_at_81[0x1f];
1966 u8 max_reformat_insert_size[0x8];
1967 u8 max_reformat_insert_offset[0x8];
1968 u8 max_reformat_remove_size[0x8];
1969 u8 max_reformat_remove_offset[0x8];
1971 u8 reserved_at_c0[0x8];
1972 u8 migration_multi_load[0x1];
1973 u8 migration_tracking_state[0x1];
1974 u8 reserved_at_ca[0x6];
1975 u8 migration_in_chunks[0x1];
1976 u8 reserved_at_d1[0xf];
1978 u8 cross_vhca_object_to_object_supported[0x20];
1980 u8 allowed_object_for_other_vhca_access[0x40];
1982 u8 reserved_at_140[0x60];
1984 u8 flow_table_type_2_type[0x8];
1985 u8 reserved_at_1a8[0x3];
1986 u8 log_min_mkey_entity_size[0x5];
1987 u8 reserved_at_1b0[0x10];
1989 u8 reserved_at_1c0[0x60];
1991 u8 reserved_at_220[0x1];
1992 u8 sw_vhca_id_valid[0x1];
1993 u8 sw_vhca_id[0xe];
1994 u8 reserved_at_230[0x10];
1996 u8 reserved_at_240[0xb];
1997 u8 ts_cqe_metadata_size2wqe_counter[0x5];
1998 u8 reserved_at_250[0x10];
2000 u8 reserved_at_260[0x120];
2001 u8 reserved_at_380[0x10];
2002 u8 ec_vf_vport_base[0x10];
2004 u8 reserved_at_3a0[0x10];
2005 u8 max_rqt_vhca_id[0x10];
2007 u8 reserved_at_3c0[0x440];
2011 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
2012 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
2013 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
2014 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2015 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
2016 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA,
2026 u8 destination_type[0x8];
2027 u8 destination_id[0x18];
2029 u8 destination_eswitch_owner_vhca_id_valid[0x1];
2030 u8 packet_reformat[0x1];
2031 u8 reserved_at_22[0x6];
2032 u8 destination_table_type[0x8];
2033 u8 destination_eswitch_owner_vhca_id[0x10];
2037 u8 flow_counter_id[0x20];
2039 u8 reserved_at_20[0x20];
2045 u8 packet_reformat_id[0x20];
2047 u8 reserved_at_60[0x20];
2070 u8 reserved_at_e00[0x200];
2074 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
2075 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
2076 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
2077 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
2078 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
2082 u8 l3_prot_type[0x1];
2083 u8 l4_prot_type[0x1];
2084 u8 selected_fields[0x1e];
2088 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
2089 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
2093 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
2094 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
2098 u8 wq_type[0x4];
2099 u8 wq_signature[0x1];
2100 u8 end_padding_mode[0x2];
2101 u8 cd_slave[0x1];
2102 u8 reserved_at_8[0x18];
2104 u8 hds_skip_first_sge[0x1];
2105 u8 log2_hds_buf_size[0x3];
2106 u8 reserved_at_24[0x7];
2107 u8 page_offset[0x5];
2108 u8 lwm[0x10];
2110 u8 reserved_at_40[0x8];
2111 u8 pd[0x18];
2113 u8 reserved_at_60[0x8];
2114 u8 uar_page[0x18];
2116 u8 dbr_addr[0x40];
2118 u8 hw_counter[0x20];
2120 u8 sw_counter[0x20];
2122 u8 reserved_at_100[0xc];
2123 u8 log_wq_stride[0x4];
2124 u8 reserved_at_110[0x3];
2125 u8 log_wq_pg_sz[0x5];
2126 u8 reserved_at_118[0x3];
2127 u8 log_wq_sz[0x5];
2129 u8 dbr_umem_valid[0x1];
2130 u8 wq_umem_valid[0x1];
2131 u8 reserved_at_122[0x1];
2132 u8 log_hairpin_num_packets[0x5];
2133 u8 reserved_at_128[0x3];
2134 u8 log_hairpin_data_sz[0x5];
2136 u8 reserved_at_130[0x4];
2137 u8 log_wqe_num_of_strides[0x4];
2138 u8 two_byte_shift_en[0x1];
2139 u8 reserved_at_139[0x4];
2140 u8 log_wqe_stride_size[0x3];
2142 u8 reserved_at_140[0x80];
2144 u8 headers_mkey[0x20];
2146 u8 shampo_enable[0x1];
2147 u8 reserved_at_1e1[0x4];
2148 u8 log_reservation_size[0x3];
2149 u8 reserved_at_1e8[0x5];
2150 u8 log_max_num_of_packets_per_reservation[0x3];
2151 u8 reserved_at_1f0[0x6];
2152 u8 log_headers_entry_size[0x2];
2153 u8 reserved_at_1f8[0x4];
2154 u8 log_headers_buffer_entry_num[0x4];
2156 u8 reserved_at_200[0x400];
2162 u8 reserved_at_0[0x8];
2163 u8 rq_num[0x18];
2167 u8 reserved_at_0[0x8];
2168 u8 rq_num[0x18];
2169 u8 reserved_at_20[0x10];
2170 u8 rq_vhca_id[0x10];
2174 u8 reserved_at_0[0x10];
2175 u8 mac_addr_47_32[0x10];
2177 u8 mac_addr_31_0[0x20];
2181 u8 reserved_at_0[0x14];
2182 u8 vlan[0x0c];
2184 u8 reserved_at_20[0x20];
2188 u8 reserved_at_0[0xa0];
2190 u8 min_time_between_cnps[0x20];
2192 u8 reserved_at_c0[0x12];
2193 u8 cnp_dscp[0x6];
2194 u8 reserved_at_d8[0x4];
2195 u8 cnp_prio_mode[0x1];
2196 u8 cnp_802p_prio[0x3];
2198 u8 reserved_at_e0[0x720];
2202 u8 reserved_at_0[0x60];
2204 u8 reserved_at_60[0x4];
2205 u8 clamp_tgt_rate[0x1];
2206 u8 reserved_at_65[0x3];
2207 u8 clamp_tgt_rate_after_time_inc[0x1];
2208 u8 reserved_at_69[0x17];
2210 u8 reserved_at_80[0x20];
2212 u8 rpg_time_reset[0x20];
2214 u8 rpg_byte_reset[0x20];
2216 u8 rpg_threshold[0x20];
2218 u8 rpg_max_rate[0x20];
2220 u8 rpg_ai_rate[0x20];
2222 u8 rpg_hai_rate[0x20];
2224 u8 rpg_gd[0x20];
2226 u8 rpg_min_dec_fac[0x20];
2228 u8 rpg_min_rate[0x20];
2230 u8 reserved_at_1c0[0xe0];
2232 u8 rate_to_set_on_first_cnp[0x20];
2234 u8 dce_tcp_g[0x20];
2236 u8 dce_tcp_rtt[0x20];
2238 u8 rate_reduce_monitor_period[0x20];
2240 u8 reserved_at_320[0x20];
2242 u8 initial_alpha_value[0x20];
2244 u8 reserved_at_360[0x4a0];
2248 u8 reserved_at_0[0x80];
2250 u8 reserved_at_80[0x10];
2251 u8 rtt_resp_dscp_valid[0x1];
2252 u8 reserved_at_91[0x9];
2253 u8 rtt_resp_dscp[0x6];
2255 u8 reserved_at_a0[0x760];
2259 u8 reserved_at_0[0x80];
2261 u8 rppp_max_rps[0x20];
2263 u8 rpg_time_reset[0x20];
2265 u8 rpg_byte_reset[0x20];
2267 u8 rpg_threshold[0x20];
2269 u8 rpg_max_rate[0x20];
2271 u8 rpg_ai_rate[0x20];
2273 u8 rpg_hai_rate[0x20];
2275 u8 rpg_gd[0x20];
2277 u8 rpg_min_dec_fac[0x20];
2279 u8 rpg_min_rate[0x20];
2281 u8 reserved_at_1c0[0x640];
2285 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
2286 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
2287 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
2291 u8 resize_field_select[0x20];
2295 u8 more_dump[0x1];
2296 u8 inline_dump[0x1];
2297 u8 reserved_at_2[0xa];
2298 u8 seq_num[0x4];
2299 u8 segment_type[0x10];
2301 u8 reserved_at_20[0x10];
2302 u8 vhca_id[0x10];
2304 u8 index1[0x20];
2306 u8 index2[0x20];
2308 u8 num_of_obj1[0x10];
2309 u8 num_of_obj2[0x10];
2311 u8 reserved_at_a0[0x20];
2313 u8 device_opaque[0x40];
2315 u8 mkey[0x20];
2317 u8 size[0x20];
2319 u8 address[0x40];
2321 u8 inline_data[52][0x20];
2325 u8 reserved_at_0[0x4];
2326 u8 num_of_obj2_supports_active[0x1];
2327 u8 num_of_obj2_supports_all[0x1];
2328 u8 must_have_num_of_obj2[0x1];
2329 u8 support_num_of_obj2[0x1];
2330 u8 num_of_obj1_supports_active[0x1];
2331 u8 num_of_obj1_supports_all[0x1];
2332 u8 must_have_num_of_obj1[0x1];
2333 u8 support_num_of_obj1[0x1];
2334 u8 must_have_index2[0x1];
2335 u8 support_index2[0x1];
2336 u8 must_have_index1[0x1];
2337 u8 support_index1[0x1];
2338 u8 segment_type[0x10];
2340 u8 segment_name[4][0x20];
2342 u8 index1_name[4][0x20];
2344 u8 index2_name[4][0x20];
2348 u8 length_dw[0x10];
2349 u8 segment_type[0x10];
2355 u8 segment_called[0x10];
2356 u8 vhca_id[0x10];
2358 u8 index1[0x20];
2360 u8 index2[0x20];
2362 u8 num_of_obj1[0x10];
2363 u8 num_of_obj2[0x10];
2369 u8 reserved_at_20[0x10];
2370 u8 syndrome_id[0x10];
2372 u8 reserved_at_40[0x40];
2374 u8 error[8][0x20];
2380 u8 reserved_at_20[0x18];
2381 u8 dump_version[0x8];
2383 u8 hw_version[0x20];
2385 u8 fw_version[0x20];
2391 u8 reserved_at_20[0x10];
2392 u8 num_of_records[0x10];
2400 u8 reserved_at_20[0x20];
2402 u8 index1[0x20];
2404 u8 index2[0x20];
2406 u8 payload[][0x20];
2421 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2422 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2423 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2424 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2428 u8 modify_field_select[0x20];
2432 u8 field_select_r_roce_np[0x20];
2436 u8 field_select_r_roce_rp[0x20];
2440 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2441 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2442 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2443 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2444 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2445 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2446 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2447 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2448 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2449 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2453 u8 field_select_8021qaurp[0x20];
2457 u8 time_since_last_clear_high[0x20];
2459 u8 time_since_last_clear_low[0x20];
2461 u8 symbol_errors_high[0x20];
2463 u8 symbol_errors_low[0x20];
2465 u8 sync_headers_errors_high[0x20];
2467 u8 sync_headers_errors_low[0x20];
2469 u8 edpl_bip_errors_lane0_high[0x20];
2471 u8 edpl_bip_errors_lane0_low[0x20];
2473 u8 edpl_bip_errors_lane1_high[0x20];
2475 u8 edpl_bip_errors_lane1_low[0x20];
2477 u8 edpl_bip_errors_lane2_high[0x20];
2479 u8 edpl_bip_errors_lane2_low[0x20];
2481 u8 edpl_bip_errors_lane3_high[0x20];
2483 u8 edpl_bip_errors_lane3_low[0x20];
2485 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2487 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2489 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2491 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2493 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2495 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2497 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2499 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2501 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2503 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2505 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2507 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2509 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2511 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2513 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2515 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2517 u8 rs_fec_corrected_blocks_high[0x20];
2519 u8 rs_fec_corrected_blocks_low[0x20];
2521 u8 rs_fec_uncorrectable_blocks_high[0x20];
2523 u8 rs_fec_uncorrectable_blocks_low[0x20];
2525 u8 rs_fec_no_errors_blocks_high[0x20];
2527 u8 rs_fec_no_errors_blocks_low[0x20];
2529 u8 rs_fec_single_error_blocks_high[0x20];
2531 u8 rs_fec_single_error_blocks_low[0x20];
2533 u8 rs_fec_corrected_symbols_total_high[0x20];
2535 u8 rs_fec_corrected_symbols_total_low[0x20];
2537 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2539 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2541 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2543 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2545 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2547 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2549 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2551 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2553 u8 link_down_events[0x20];
2555 u8 successful_recovery_events[0x20];
2557 u8 reserved_at_640[0x180];
2561 u8 time_since_last_clear_high[0x20];
2563 u8 time_since_last_clear_low[0x20];
2565 u8 phy_received_bits_high[0x20];
2567 u8 phy_received_bits_low[0x20];
2569 u8 phy_symbol_errors_high[0x20];
2571 u8 phy_symbol_errors_low[0x20];
2573 u8 phy_corrected_bits_high[0x20];
2575 u8 phy_corrected_bits_low[0x20];
2577 u8 phy_corrected_bits_lane0_high[0x20];
2579 u8 phy_corrected_bits_lane0_low[0x20];
2581 u8 phy_corrected_bits_lane1_high[0x20];
2583 u8 phy_corrected_bits_lane1_low[0x20];
2585 u8 phy_corrected_bits_lane2_high[0x20];
2587 u8 phy_corrected_bits_lane2_low[0x20];
2589 u8 phy_corrected_bits_lane3_high[0x20];
2591 u8 phy_corrected_bits_lane3_low[0x20];
2593 u8 reserved_at_200[0x5c0];
2597 u8 symbol_error_counter[0x10];
2599 u8 link_error_recovery_counter[0x8];
2601 u8 link_downed_counter[0x8];
2603 u8 port_rcv_errors[0x10];
2605 u8 port_rcv_remote_physical_errors[0x10];
2607 u8 port_rcv_switch_relay_errors[0x10];
2609 u8 port_xmit_discards[0x10];
2611 u8 port_xmit_constraint_errors[0x8];
2613 u8 port_rcv_constraint_errors[0x8];
2615 u8 reserved_at_70[0x8];
2617 u8 link_overrun_errors[0x8];
2619 u8 reserved_at_80[0x10];
2621 u8 vl_15_dropped[0x10];
2623 u8 reserved_at_a0[0x80];
2625 u8 port_xmit_wait[0x20];
2629 u8 transmit_queue_high[0x20];
2631 u8 transmit_queue_low[0x20];
2633 u8 no_buffer_discard_uc_high[0x20];
2635 u8 no_buffer_discard_uc_low[0x20];
2637 u8 reserved_at_80[0x740];
2641 u8 wred_discard_high[0x20];
2643 u8 wred_discard_low[0x20];
2645 u8 ecn_marked_tc_high[0x20];
2647 u8 ecn_marked_tc_low[0x20];
2649 u8 reserved_at_80[0x740];
2653 u8 rx_octets_high[0x20];
2655 u8 rx_octets_low[0x20];
2657 u8 reserved_at_40[0xc0];
2659 u8 rx_frames_high[0x20];
2661 u8 rx_frames_low[0x20];
2663 u8 tx_octets_high[0x20];
2665 u8 tx_octets_low[0x20];
2667 u8 reserved_at_180[0xc0];
2669 u8 tx_frames_high[0x20];
2671 u8 tx_frames_low[0x20];
2673 u8 rx_pause_high[0x20];
2675 u8 rx_pause_low[0x20];
2677 u8 rx_pause_duration_high[0x20];
2679 u8 rx_pause_duration_low[0x20];
2681 u8 tx_pause_high[0x20];
2683 u8 tx_pause_low[0x20];
2685 u8 tx_pause_duration_high[0x20];
2687 u8 tx_pause_duration_low[0x20];
2689 u8 rx_pause_transition_high[0x20];
2691 u8 rx_pause_transition_low[0x20];
2693 u8 rx_discards_high[0x20];
2695 u8 rx_discards_low[0x20];
2697 u8 device_stall_minor_watermark_cnt_high[0x20];
2699 u8 device_stall_minor_watermark_cnt_low[0x20];
2701 u8 device_stall_critical_watermark_cnt_high[0x20];
2703 u8 device_stall_critical_watermark_cnt_low[0x20];
2705 u8 reserved_at_480[0x340];
2709 u8 port_transmit_wait_high[0x20];
2711 u8 port_transmit_wait_low[0x20];
2713 u8 reserved_at_40[0x100];
2715 u8 rx_buffer_almost_full_high[0x20];
2717 u8 rx_buffer_almost_full_low[0x20];
2719 u8 rx_buffer_full_high[0x20];
2721 u8 rx_buffer_full_low[0x20];
2723 u8 rx_icrc_encapsulated_high[0x20];
2725 u8 rx_icrc_encapsulated_low[0x20];
2727 u8 reserved_at_200[0x5c0];
2731 u8 dot3stats_alignment_errors_high[0x20];
2733 u8 dot3stats_alignment_errors_low[0x20];
2735 u8 dot3stats_fcs_errors_high[0x20];
2737 u8 dot3stats_fcs_errors_low[0x20];
2739 u8 dot3stats_single_collision_frames_high[0x20];
2741 u8 dot3stats_single_collision_frames_low[0x20];
2743 u8 dot3stats_multiple_collision_frames_high[0x20];
2745 u8 dot3stats_multiple_collision_frames_low[0x20];
2747 u8 dot3stats_sqe_test_errors_high[0x20];
2749 u8 dot3stats_sqe_test_errors_low[0x20];
2751 u8 dot3stats_deferred_transmissions_high[0x20];
2753 u8 dot3stats_deferred_transmissions_low[0x20];
2755 u8 dot3stats_late_collisions_high[0x20];
2757 u8 dot3stats_late_collisions_low[0x20];
2759 u8 dot3stats_excessive_collisions_high[0x20];
2761 u8 dot3stats_excessive_collisions_low[0x20];
2763 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2765 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2767 u8 dot3stats_carrier_sense_errors_high[0x20];
2769 u8 dot3stats_carrier_sense_errors_low[0x20];
2771 u8 dot3stats_frame_too_longs_high[0x20];
2773 u8 dot3stats_frame_too_longs_low[0x20];
2775 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2777 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2779 u8 dot3stats_symbol_errors_high[0x20];
2781 u8 dot3stats_symbol_errors_low[0x20];
2783 u8 dot3control_in_unknown_opcodes_high[0x20];
2785 u8 dot3control_in_unknown_opcodes_low[0x20];
2787 u8 dot3in_pause_frames_high[0x20];
2789 u8 dot3in_pause_frames_low[0x20];
2791 u8 dot3out_pause_frames_high[0x20];
2793 u8 dot3out_pause_frames_low[0x20];
2795 u8 reserved_at_400[0x3c0];
2799 u8 ether_stats_drop_events_high[0x20];
2801 u8 ether_stats_drop_events_low[0x20];
2803 u8 ether_stats_octets_high[0x20];
2805 u8 ether_stats_octets_low[0x20];
2807 u8 ether_stats_pkts_high[0x20];
2809 u8 ether_stats_pkts_low[0x20];
2811 u8 ether_stats_broadcast_pkts_high[0x20];
2813 u8 ether_stats_broadcast_pkts_low[0x20];
2815 u8 ether_stats_multicast_pkts_high[0x20];
2817 u8 ether_stats_multicast_pkts_low[0x20];
2819 u8 ether_stats_crc_align_errors_high[0x20];
2821 u8 ether_stats_crc_align_errors_low[0x20];
2823 u8 ether_stats_undersize_pkts_high[0x20];
2825 u8 ether_stats_undersize_pkts_low[0x20];
2827 u8 ether_stats_oversize_pkts_high[0x20];
2829 u8 ether_stats_oversize_pkts_low[0x20];
2831 u8 ether_stats_fragments_high[0x20];
2833 u8 ether_stats_fragments_low[0x20];
2835 u8 ether_stats_jabbers_high[0x20];
2837 u8 ether_stats_jabbers_low[0x20];
2839 u8 ether_stats_collisions_high[0x20];
2841 u8 ether_stats_collisions_low[0x20];
2843 u8 ether_stats_pkts64octets_high[0x20];
2845 u8 ether_stats_pkts64octets_low[0x20];
2847 u8 ether_stats_pkts65to127octets_high[0x20];
2849 u8 ether_stats_pkts65to127octets_low[0x20];
2851 u8 ether_stats_pkts128to255octets_high[0x20];
2853 u8 ether_stats_pkts128to255octets_low[0x20];
2855 u8 ether_stats_pkts256to511octets_high[0x20];
2857 u8 ether_stats_pkts256to511octets_low[0x20];
2859 u8 ether_stats_pkts512to1023octets_high[0x20];
2861 u8 ether_stats_pkts512to1023octets_low[0x20];
2863 u8 ether_stats_pkts1024to1518octets_high[0x20];
2865 u8 ether_stats_pkts1024to1518octets_low[0x20];
2867 u8 ether_stats_pkts1519to2047octets_high[0x20];
2869 u8 ether_stats_pkts1519to2047octets_low[0x20];
2871 u8 ether_stats_pkts2048to4095octets_high[0x20];
2873 u8 ether_stats_pkts2048to4095octets_low[0x20];
2875 u8 ether_stats_pkts4096to8191octets_high[0x20];
2877 u8 ether_stats_pkts4096to8191octets_low[0x20];
2879 u8 ether_stats_pkts8192to10239octets_high[0x20];
2881 u8 ether_stats_pkts8192to10239octets_low[0x20];
2883 u8 reserved_at_540[0x280];
2887 u8 if_in_octets_high[0x20];
2889 u8 if_in_octets_low[0x20];
2891 u8 if_in_ucast_pkts_high[0x20];
2893 u8 if_in_ucast_pkts_low[0x20];
2895 u8 if_in_discards_high[0x20];
2897 u8 if_in_discards_low[0x20];
2899 u8 if_in_errors_high[0x20];
2901 u8 if_in_errors_low[0x20];
2903 u8 if_in_unknown_protos_high[0x20];
2905 u8 if_in_unknown_protos_low[0x20];
2907 u8 if_out_octets_high[0x20];
2909 u8 if_out_octets_low[0x20];
2911 u8 if_out_ucast_pkts_high[0x20];
2913 u8 if_out_ucast_pkts_low[0x20];
2915 u8 if_out_discards_high[0x20];
2917 u8 if_out_discards_low[0x20];
2919 u8 if_out_errors_high[0x20];
2921 u8 if_out_errors_low[0x20];
2923 u8 if_in_multicast_pkts_high[0x20];
2925 u8 if_in_multicast_pkts_low[0x20];
2927 u8 if_in_broadcast_pkts_high[0x20];
2929 u8 if_in_broadcast_pkts_low[0x20];
2931 u8 if_out_multicast_pkts_high[0x20];
2933 u8 if_out_multicast_pkts_low[0x20];
2935 u8 if_out_broadcast_pkts_high[0x20];
2937 u8 if_out_broadcast_pkts_low[0x20];
2939 u8 reserved_at_340[0x480];
2943 u8 a_frames_transmitted_ok_high[0x20];
2945 u8 a_frames_transmitted_ok_low[0x20];
2947 u8 a_frames_received_ok_high[0x20];
2949 u8 a_frames_received_ok_low[0x20];
2951 u8 a_frame_check_sequence_errors_high[0x20];
2953 u8 a_frame_check_sequence_errors_low[0x20];
2955 u8 a_alignment_errors_high[0x20];
2957 u8 a_alignment_errors_low[0x20];
2959 u8 a_octets_transmitted_ok_high[0x20];
2961 u8 a_octets_transmitted_ok_low[0x20];
2963 u8 a_octets_received_ok_high[0x20];
2965 u8 a_octets_received_ok_low[0x20];
2967 u8 a_multicast_frames_xmitted_ok_high[0x20];
2969 u8 a_multicast_frames_xmitted_ok_low[0x20];
2971 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2973 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2975 u8 a_multicast_frames_received_ok_high[0x20];
2977 u8 a_multicast_frames_received_ok_low[0x20];
2979 u8 a_broadcast_frames_received_ok_high[0x20];
2981 u8 a_broadcast_frames_received_ok_low[0x20];
2983 u8 a_in_range_length_errors_high[0x20];
2985 u8 a_in_range_length_errors_low[0x20];
2987 u8 a_out_of_range_length_field_high[0x20];
2989 u8 a_out_of_range_length_field_low[0x20];
2991 u8 a_frame_too_long_errors_high[0x20];
2993 u8 a_frame_too_long_errors_low[0x20];
2995 u8 a_symbol_error_during_carrier_high[0x20];
2997 u8 a_symbol_error_during_carrier_low[0x20];
2999 u8 a_mac_control_frames_transmitted_high[0x20];
3001 u8 a_mac_control_frames_transmitted_low[0x20];
3003 u8 a_mac_control_frames_received_high[0x20];
3005 u8 a_mac_control_frames_received_low[0x20];
3007 u8 a_unsupported_opcodes_received_high[0x20];
3009 u8 a_unsupported_opcodes_received_low[0x20];
3011 u8 a_pause_mac_ctrl_frames_received_high[0x20];
3013 u8 a_pause_mac_ctrl_frames_received_low[0x20];
3015 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
3017 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
3019 u8 reserved_at_4c0[0x300];
3023 u8 life_time_counter_high[0x20];
3025 u8 life_time_counter_low[0x20];
3027 u8 rx_errors[0x20];
3029 u8 tx_errors[0x20];
3031 u8 l0_to_recovery_eieos[0x20];
3033 u8 l0_to_recovery_ts[0x20];
3035 u8 l0_to_recovery_framing[0x20];
3037 u8 l0_to_recovery_retrain[0x20];
3039 u8 crc_error_dllp[0x20];
3041 u8 crc_error_tlp[0x20];
3043 u8 tx_overflow_buffer_pkt_high[0x20];
3045 u8 tx_overflow_buffer_pkt_low[0x20];
3047 u8 outbound_stalled_reads[0x20];
3049 u8 outbound_stalled_writes[0x20];
3051 u8 outbound_stalled_reads_events[0x20];
3053 u8 outbound_stalled_writes_events[0x20];
3055 u8 reserved_at_200[0x5c0];
3059 u8 command_completion_vector[0x20];
3061 u8 reserved_at_20[0xc0];
3065 u8 reserved_at_0[0x18];
3066 u8 port_num[0x1];
3067 u8 reserved_at_19[0x3];
3068 u8 vl[0x4];
3070 u8 reserved_at_20[0xa0];
3074 u8 event_subtype[0x8];
3075 u8 reserved_at_8[0x8];
3076 u8 congestion_level[0x8];
3077 u8 reserved_at_18[0x8];
3079 u8 reserved_at_20[0xa0];
3083 u8 reserved_at_0[0x60];
3085 u8 gpio_event_hi[0x20];
3087 u8 gpio_event_lo[0x20];
3089 u8 reserved_at_a0[0x40];
3093 u8 reserved_at_0[0x40];
3095 u8 port_num[0x4];
3096 u8 reserved_at_44[0x1c];
3098 u8 reserved_at_60[0x80];
3102 u8 reserved_at_0[0xe0];
3106 u8 to_multiplier[0x3];
3107 u8 reserved_at_3[0x9];
3108 u8 to_value[0x14];
3112 u8 reserved_at_0[0x20];
3116 u8 reserved_at_40[0x60];
3138 u8 reserved_at_1c0[0x20];
3142 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
3143 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
3147 u8 reserved_at_0[0x8];
3148 u8 cqn[0x18];
3150 u8 reserved_at_20[0x20];
3152 u8 reserved_at_40[0x18];
3153 u8 syndrome[0x8];
3155 u8 reserved_at_60[0x80];
3159 u8 bytes_committed[0x20];
3161 u8 r_key[0x20];
3163 u8 reserved_at_40[0x10];
3164 u8 packet_len[0x10];
3166 u8 rdma_op_len[0x20];
3168 u8 rdma_va[0x40];
3170 u8 reserved_at_c0[0x5];
3171 u8 rdma[0x1];
3172 u8 write[0x1];
3173 u8 requestor[0x1];
3174 u8 qp_number[0x18];
3178 u8 bytes_committed[0x20];
3180 u8 reserved_at_20[0x10];
3181 u8 wqe_index[0x10];
3183 u8 reserved_at_40[0x10];
3184 u8 len[0x10];
3186 u8 reserved_at_60[0x60];
3188 u8 reserved_at_c0[0x5];
3189 u8 rdma[0x1];
3190 u8 write_read[0x1];
3191 u8 requestor[0x1];
3192 u8 qpn[0x18];
3196 u8 reserved_at_0[0xa0];
3198 u8 type[0x8];
3199 u8 reserved_at_a8[0x18];
3201 u8 reserved_at_c0[0x8];
3202 u8 qpn_rqn_sqn[0x18];
3206 u8 reserved_at_0[0xc0];
3208 u8 reserved_at_c0[0x8];
3209 u8 dct_number[0x18];
3213 u8 reserved_at_0[0xc0];
3215 u8 reserved_at_c0[0x8];
3216 u8 cq_number[0x18];
3220 MLX5_QPC_STATE_RST = 0x0,
3221 MLX5_QPC_STATE_INIT = 0x1,
3222 MLX5_QPC_STATE_RTR = 0x2,
3223 MLX5_QPC_STATE_RTS = 0x3,
3224 MLX5_QPC_STATE_SQER = 0x4,
3225 MLX5_QPC_STATE_ERR = 0x6,
3226 MLX5_QPC_STATE_SQD = 0x7,
3227 MLX5_QPC_STATE_SUSPENDED = 0x9,
3231 MLX5_QPC_ST_RC = 0x0,
3232 MLX5_QPC_ST_UC = 0x1,
3233 MLX5_QPC_ST_UD = 0x2,
3234 MLX5_QPC_ST_XRC = 0x3,
3235 MLX5_QPC_ST_DCI = 0x5,
3236 MLX5_QPC_ST_QP0 = 0x7,
3237 MLX5_QPC_ST_QP1 = 0x8,
3238 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
3239 MLX5_QPC_ST_REG_UMR = 0xc,
3243 MLX5_QPC_PM_STATE_ARMED = 0x0,
3244 MLX5_QPC_PM_STATE_REARM = 0x1,
3245 MLX5_QPC_PM_STATE_RESERVED = 0x2,
3246 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
3250 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
3254 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
3255 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
3259 MLX5_QPC_MTU_256_BYTES = 0x1,
3260 MLX5_QPC_MTU_512_BYTES = 0x2,
3261 MLX5_QPC_MTU_1K_BYTES = 0x3,
3262 MLX5_QPC_MTU_2K_BYTES = 0x4,
3263 MLX5_QPC_MTU_4K_BYTES = 0x5,
3264 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
3268 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
3269 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
3270 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
3271 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
3272 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
3273 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
3274 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
3275 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
3279 MLX5_QPC_CS_REQ_DISABLE = 0x0,
3280 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
3281 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
3285 MLX5_QPC_CS_RES_DISABLE = 0x0,
3286 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
3287 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
3291 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3292 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3293 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
3297 u8 state[0x4];
3298 u8 lag_tx_port_affinity[0x4];
3299 u8 st[0x8];
3300 u8 reserved_at_10[0x2];
3301 u8 isolate_vl_tc[0x1];
3302 u8 pm_state[0x2];
3303 u8 reserved_at_15[0x1];
3304 u8 req_e2e_credit_mode[0x2];
3305 u8 offload_type[0x4];
3306 u8 end_padding_mode[0x2];
3307 u8 reserved_at_1e[0x2];
3309 u8 wq_signature[0x1];
3310 u8 block_lb_mc[0x1];
3311 u8 atomic_like_write_en[0x1];
3312 u8 latency_sensitive[0x1];
3313 u8 reserved_at_24[0x1];
3314 u8 drain_sigerr[0x1];
3315 u8 reserved_at_26[0x2];
3316 u8 pd[0x18];
3318 u8 mtu[0x3];
3319 u8 log_msg_max[0x5];
3320 u8 reserved_at_48[0x1];
3321 u8 log_rq_size[0x4];
3322 u8 log_rq_stride[0x3];
3323 u8 no_sq[0x1];
3324 u8 log_sq_size[0x4];
3325 u8 reserved_at_55[0x1];
3326 u8 retry_mode[0x2];
3327 u8 ts_format[0x2];
3328 u8 reserved_at_5a[0x1];
3329 u8 rlky[0x1];
3330 u8 ulp_stateless_offload_mode[0x4];
3332 u8 counter_set_id[0x8];
3333 u8 uar_page[0x18];
3335 u8 reserved_at_80[0x8];
3336 u8 user_index[0x18];
3338 u8 reserved_at_a0[0x3];
3339 u8 log_page_size[0x5];
3340 u8 remote_qpn[0x18];
3346 u8 log_ack_req_freq[0x4];
3347 u8 reserved_at_384[0x4];
3348 u8 log_sra_max[0x3];
3349 u8 reserved_at_38b[0x2];
3350 u8 retry_count[0x3];
3351 u8 rnr_retry[0x3];
3352 u8 reserved_at_393[0x1];
3353 u8 fre[0x1];
3354 u8 cur_rnr_retry[0x3];
3355 u8 cur_retry_count[0x3];
3356 u8 reserved_at_39b[0x5];
3358 u8 reserved_at_3a0[0x20];
3360 u8 reserved_at_3c0[0x8];
3361 u8 next_send_psn[0x18];
3363 u8 reserved_at_3e0[0x3];
3364 u8 log_num_dci_stream_channels[0x5];
3365 u8 cqn_snd[0x18];
3367 u8 reserved_at_400[0x3];
3368 u8 log_num_dci_errored_streams[0x5];
3369 u8 deth_sqpn[0x18];
3371 u8 reserved_at_420[0x20];
3373 u8 reserved_at_440[0x8];
3374 u8 last_acked_psn[0x18];
3376 u8 reserved_at_460[0x8];
3377 u8 ssn[0x18];
3379 u8 reserved_at_480[0x8];
3380 u8 log_rra_max[0x3];
3381 u8 reserved_at_48b[0x1];
3382 u8 atomic_mode[0x4];
3383 u8 rre[0x1];
3384 u8 rwe[0x1];
3385 u8 rae[0x1];
3386 u8 reserved_at_493[0x1];
3387 u8 page_offset[0x6];
3388 u8 reserved_at_49a[0x3];
3389 u8 cd_slave_receive[0x1];
3390 u8 cd_slave_send[0x1];
3391 u8 cd_master[0x1];
3393 u8 reserved_at_4a0[0x3];
3394 u8 min_rnr_nak[0x5];
3395 u8 next_rcv_psn[0x18];
3397 u8 reserved_at_4c0[0x8];
3398 u8 xrcd[0x18];
3400 u8 reserved_at_4e0[0x8];
3401 u8 cqn_rcv[0x18];
3403 u8 dbr_addr[0x40];
3405 u8 q_key[0x20];
3407 u8 reserved_at_560[0x5];
3408 u8 rq_type[0x3];
3409 u8 srqn_rmpn_xrqn[0x18];
3411 u8 reserved_at_580[0x8];
3412 u8 rmsn[0x18];
3414 u8 hw_sq_wqebb_counter[0x10];
3415 u8 sw_sq_wqebb_counter[0x10];
3417 u8 hw_rq_counter[0x20];
3419 u8 sw_rq_counter[0x20];
3421 u8 reserved_at_600[0x20];
3423 u8 reserved_at_620[0xf];
3424 u8 cgs[0x1];
3425 u8 cs_req[0x8];
3426 u8 cs_res[0x8];
3428 u8 dc_access_key[0x40];
3430 u8 reserved_at_680[0x3];
3431 u8 dbr_umem_valid[0x1];
3433 u8 reserved_at_684[0xbc];
3437 u8 source_l3_address[16][0x8];
3439 u8 reserved_at_80[0x3];
3440 u8 vlan_valid[0x1];
3441 u8 vlan_id[0xc];
3442 u8 source_mac_47_32[0x10];
3444 u8 source_mac_31_0[0x20];
3446 u8 reserved_at_c0[0x14];
3447 u8 roce_l3_type[0x4];
3448 u8 roce_version[0x8];
3450 u8 reserved_at_e0[0x20];
3454 u8 reserved_at_0[0x3];
3455 u8 synchronize_dek[0x1];
3456 u8 int_kek_manual[0x1];
3457 u8 int_kek_auto[0x1];
3458 u8 reserved_at_6[0x1a];
3460 u8 reserved_at_20[0x3];
3461 u8 log_dek_max_alloc[0x5];
3462 u8 reserved_at_28[0x3];
3463 u8 log_max_num_deks[0x5];
3464 u8 reserved_at_30[0x10];
3466 u8 reserved_at_40[0x20];
3468 u8 reserved_at_60[0x3];
3469 u8 log_dek_granularity[0x5];
3470 u8 reserved_at_68[0x3];
3471 u8 log_max_num_int_kek[0x5];
3472 u8 sw_wrapped_dek[0x10];
3474 u8 reserved_at_80[0x780];
3497 u8 reserved_at_0[0x8000];
3501 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3502 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3503 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
3504 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
3505 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3506 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3507 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3508 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3509 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3510 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3511 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3512 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3513 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3514 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3518 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3519 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3520 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3524 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0,
3525 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1,
3529 u8 ethtype[0x10];
3530 u8 prio[0x3];
3531 u8 cfi[0x1];
3532 u8 vid[0xc];
3536 MLX5_FLOW_METER_COLOR_RED = 0x0,
3537 MLX5_FLOW_METER_COLOR_YELLOW = 0x1,
3538 MLX5_FLOW_METER_COLOR_GREEN = 0x2,
3539 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3543 MLX5_EXE_ASO_FLOW_METER = 0x2,
3547 u8 return_reg_id[0x4];
3548 u8 aso_type[0x4];
3549 u8 reserved_at_8[0x14];
3550 u8 action[0x1];
3551 u8 init_color[0x2];
3552 u8 meter_id[0x1];
3560 u8 valid[0x1];
3561 u8 reserved_at_1[0x7];
3562 u8 aso_object_id[0x18];
3570 u8 group_id[0x20];
3572 u8 reserved_at_40[0x8];
3573 u8 flow_tag[0x18];
3575 u8 reserved_at_60[0x10];
3576 u8 action[0x10];
3578 u8 extended_destination[0x1];
3579 u8 uplink_hairpin_en[0x1];
3580 u8 flow_source[0x2];
3581 u8 encrypt_decrypt_type[0x4];
3582 u8 destination_list_size[0x18];
3584 u8 reserved_at_a0[0x8];
3585 u8 flow_counter_list_size[0x18];
3587 u8 packet_reformat_id[0x20];
3589 u8 modify_header_id[0x20];
3593 u8 encrypt_decrypt_obj_id[0x20];
3594 u8 reserved_at_140[0xc0];
3600 u8 reserved_at_1300[0x500];
3606 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3607 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3611 u8 state[0x4];
3612 u8 log_xrc_srq_size[0x4];
3613 u8 reserved_at_8[0x18];
3615 u8 wq_signature[0x1];
3616 u8 cont_srq[0x1];
3617 u8 reserved_at_22[0x1];
3618 u8 rlky[0x1];
3619 u8 basic_cyclic_rcv_wqe[0x1];
3620 u8 log_rq_stride[0x3];
3621 u8 xrcd[0x18];
3623 u8 page_offset[0x6];
3624 u8 reserved_at_46[0x1];
3625 u8 dbr_umem_valid[0x1];
3626 u8 cqn[0x18];
3628 u8 reserved_at_60[0x20];
3630 u8 user_index_equal_xrc_srqn[0x1];
3631 u8 reserved_at_81[0x1];
3632 u8 log_page_size[0x6];
3633 u8 user_index[0x18];
3635 u8 reserved_at_a0[0x20];
3637 u8 reserved_at_c0[0x8];
3638 u8 pd[0x18];
3640 u8 lwm[0x10];
3641 u8 wqe_cnt[0x10];
3643 u8 reserved_at_100[0x40];
3645 u8 db_record_addr_h[0x20];
3647 u8 db_record_addr_l[0x1e];
3648 u8 reserved_at_17e[0x2];
3650 u8 reserved_at_180[0x80];
3654 u8 counter_error_queues[0x20];
3656 u8 total_error_queues[0x20];
3658 u8 send_queue_priority_update_flow[0x20];
3660 u8 reserved_at_60[0x20];
3662 u8 nic_receive_steering_discard[0x40];
3664 u8 receive_discard_vport_down[0x40];
3666 u8 transmit_discard_vport_down[0x40];
3668 u8 async_eq_overrun[0x20];
3670 u8 comp_eq_overrun[0x20];
3672 u8 reserved_at_180[0x20];
3674 u8 invalid_command[0x20];
3676 u8 quota_exceeded_command[0x20];
3678 u8 internal_rq_out_of_buffer[0x20];
3680 u8 cq_overrun[0x20];
3682 u8 eth_wqe_too_small[0x20];
3684 u8 reserved_at_220[0xc0];
3686 u8 generated_pkt_steering_fail[0x40];
3688 u8 handled_pkt_steering_fail[0x40];
3690 u8 reserved_at_360[0xc80];
3694 u8 packets[0x40];
3696 u8 octets[0x40];
3700 u8 strict_lag_tx_port_affinity[0x1];
3701 u8 tls_en[0x1];
3702 u8 reserved_at_2[0x2];
3703 u8 lag_tx_port_affinity[0x04];
3705 u8 reserved_at_8[0x4];
3706 u8 prio[0x4];
3707 u8 reserved_at_10[0x10];
3709 u8 reserved_at_20[0x100];
3711 u8 reserved_at_120[0x8];
3712 u8 transport_domain[0x18];
3714 u8 reserved_at_140[0x8];
3715 u8 underlay_qpn[0x18];
3717 u8 reserved_at_160[0x8];
3718 u8 pd[0x18];
3720 u8 reserved_at_180[0x380];
3724 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3725 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3729 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
3734 MLX5_RX_HASH_FN_NONE = 0x0,
3735 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3736 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3740 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3741 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3745 u8 reserved_at_0[0x20];
3747 u8 disp_type[0x4];
3748 u8 tls_en[0x1];
3749 u8 reserved_at_25[0x1b];
3751 u8 reserved_at_40[0x40];
3753 u8 reserved_at_80[0x4];
3754 u8 lro_timeout_period_usecs[0x10];
3755 u8 packet_merge_mask[0x4];
3756 u8 lro_max_ip_payload_size[0x8];
3758 u8 reserved_at_a0[0x40];
3760 u8 reserved_at_e0[0x8];
3761 u8 inline_rqn[0x18];
3763 u8 rx_hash_symmetric[0x1];
3764 u8 reserved_at_101[0x1];
3765 u8 tunneled_offload_en[0x1];
3766 u8 reserved_at_103[0x5];
3767 u8 indirect_table[0x18];
3769 u8 rx_hash_fn[0x4];
3770 u8 reserved_at_124[0x2];
3771 u8 self_lb_block[0x2];
3772 u8 transport_domain[0x18];
3774 u8 rx_hash_toeplitz_key[10][0x20];
3780 u8 reserved_at_2c0[0x4c0];
3784 MLX5_SRQC_STATE_GOOD = 0x0,
3785 MLX5_SRQC_STATE_ERROR = 0x1,
3789 u8 state[0x4];
3790 u8 log_srq_size[0x4];
3791 u8 reserved_at_8[0x18];
3793 u8 wq_signature[0x1];
3794 u8 cont_srq[0x1];
3795 u8 reserved_at_22[0x1];
3796 u8 rlky[0x1];
3797 u8 reserved_at_24[0x1];
3798 u8 log_rq_stride[0x3];
3799 u8 xrcd[0x18];
3801 u8 page_offset[0x6];
3802 u8 reserved_at_46[0x2];
3803 u8 cqn[0x18];
3805 u8 reserved_at_60[0x20];
3807 u8 reserved_at_80[0x2];
3808 u8 log_page_size[0x6];
3809 u8 reserved_at_88[0x18];
3811 u8 reserved_at_a0[0x20];
3813 u8 reserved_at_c0[0x8];
3814 u8 pd[0x18];
3816 u8 lwm[0x10];
3817 u8 wqe_cnt[0x10];
3819 u8 reserved_at_100[0x40];
3821 u8 dbr_addr[0x40];
3823 u8 reserved_at_180[0x80];
3827 MLX5_SQC_STATE_RST = 0x0,
3828 MLX5_SQC_STATE_RDY = 0x1,
3829 MLX5_SQC_STATE_ERR = 0x3,
3833 u8 rlky[0x1];
3834 u8 cd_master[0x1];
3835 u8 fre[0x1];
3836 u8 flush_in_error_en[0x1];
3837 u8 allow_multi_pkt_send_wqe[0x1];
3838 u8 min_wqe_inline_mode[0x3];
3839 u8 state[0x4];
3840 u8 reg_umr[0x1];
3841 u8 allow_swp[0x1];
3842 u8 hairpin[0x1];
3843 u8 reserved_at_f[0xb];
3844 u8 ts_format[0x2];
3845 u8 reserved_at_1c[0x4];
3847 u8 reserved_at_20[0x8];
3848 u8 user_index[0x18];
3850 u8 reserved_at_40[0x8];
3851 u8 cqn[0x18];
3853 u8 reserved_at_60[0x8];
3854 u8 hairpin_peer_rq[0x18];
3856 u8 reserved_at_80[0x10];
3857 u8 hairpin_peer_vhca[0x10];
3859 u8 reserved_at_a0[0x20];
3861 u8 reserved_at_c0[0x8];
3862 u8 ts_cqe_to_dest_cqn[0x18];
3864 u8 reserved_at_e0[0x10];
3865 u8 packet_pacing_rate_limit_index[0x10];
3866 u8 tis_lst_sz[0x10];
3867 u8 qos_queue_group_id[0x10];
3869 u8 reserved_at_120[0x40];
3871 u8 reserved_at_160[0x8];
3872 u8 tis_num_0[0x18];
3878 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3879 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3880 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3881 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3882 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3886 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3893 u8 element_type[0x8];
3894 u8 reserved_at_8[0x18];
3896 u8 element_attributes[0x20];
3898 u8 parent_element_id[0x20];
3900 u8 reserved_at_60[0x40];
3902 u8 bw_share[0x20];
3904 u8 max_average_bw[0x20];
3906 u8 reserved_at_e0[0x120];
3910 u8 reserved_at_0[0xa0];
3912 u8 reserved_at_a0[0x5];
3913 u8 list_q_type[0x3];
3914 u8 reserved_at_a8[0x8];
3915 u8 rqt_max_size[0x10];
3917 u8 rq_vhca_id_format[0x1];
3918 u8 reserved_at_c1[0xf];
3919 u8 rqt_actual_size[0x10];
3921 u8 reserved_at_e0[0x6a0];
3930 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3931 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3935 MLX5_RQC_STATE_RST = 0x0,
3936 MLX5_RQC_STATE_RDY = 0x1,
3937 MLX5_RQC_STATE_ERR = 0x3,
3941 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0,
3942 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1,
3943 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2,
3947 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0,
3948 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1,
3949 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2,
3953 u8 rlky[0x1];
3954 u8 delay_drop_en[0x1];
3955 u8 scatter_fcs[0x1];
3956 u8 vsd[0x1];
3957 u8 mem_rq_type[0x4];
3958 u8 state[0x4];
3959 u8 reserved_at_c[0x1];
3960 u8 flush_in_error_en[0x1];
3961 u8 hairpin[0x1];
3962 u8 reserved_at_f[0xb];
3963 u8 ts_format[0x2];
3964 u8 reserved_at_1c[0x4];
3966 u8 reserved_at_20[0x8];
3967 u8 user_index[0x18];
3969 u8 reserved_at_40[0x8];
3970 u8 cqn[0x18];
3972 u8 counter_set_id[0x8];
3973 u8 reserved_at_68[0x18];
3975 u8 reserved_at_80[0x8];
3976 u8 rmpn[0x18];
3978 u8 reserved_at_a0[0x8];
3979 u8 hairpin_peer_sq[0x18];
3981 u8 reserved_at_c0[0x10];
3982 u8 hairpin_peer_vhca[0x10];
3984 u8 reserved_at_e0[0x46];
3985 u8 shampo_no_match_alignment_granularity[0x2];
3986 u8 reserved_at_128[0x6];
3987 u8 shampo_match_criteria_type[0x2];
3988 u8 reservation_timeout[0x10];
3990 u8 reserved_at_140[0x40];
3996 MLX5_RMPC_STATE_RDY = 0x1,
3997 MLX5_RMPC_STATE_ERR = 0x3,
4001 u8 reserved_at_0[0x8];
4002 u8 state[0x4];
4003 u8 reserved_at_c[0x14];
4005 u8 basic_cyclic_rcv_wqe[0x1];
4006 u8 reserved_at_21[0x1f];
4008 u8 reserved_at_40[0x140];
4014 VHCA_ID_TYPE_HW = 0,
4019 u8 reserved_at_0[0x5];
4020 u8 min_wqe_inline_mode[0x3];
4021 u8 reserved_at_8[0x15];
4022 u8 disable_mc_local_lb[0x1];
4023 u8 disable_uc_local_lb[0x1];
4024 u8 roce_en[0x1];
4026 u8 arm_change_event[0x1];
4027 u8 reserved_at_21[0x1a];
4028 u8 event_on_mtu[0x1];
4029 u8 event_on_promisc_change[0x1];
4030 u8 event_on_vlan_change[0x1];
4031 u8 event_on_mc_address_change[0x1];
4032 u8 event_on_uc_address_change[0x1];
4034 u8 vhca_id_type[0x1];
4035 u8 reserved_at_41[0xb];
4036 u8 affiliation_criteria[0x4];
4037 u8 affiliated_vhca_id[0x10];
4039 u8 reserved_at_60[0xa0];
4041 u8 reserved_at_100[0x1];
4042 u8 sd_group[0x3];
4043 u8 reserved_at_104[0x1c];
4045 u8 reserved_at_120[0x10];
4046 u8 mtu[0x10];
4048 u8 system_image_guid[0x40];
4049 u8 port_guid[0x40];
4050 u8 node_guid[0x40];
4052 u8 reserved_at_200[0x140];
4053 u8 qkey_violation_counter[0x10];
4054 u8 reserved_at_350[0x430];
4056 u8 promisc_uc[0x1];
4057 u8 promisc_mc[0x1];
4058 u8 promisc_all[0x1];
4059 u8 reserved_at_783[0x2];
4060 u8 allowed_list_type[0x3];
4061 u8 reserved_at_788[0xc];
4062 u8 allowed_list_size[0xc];
4066 u8 reserved_at_7e0[0x20];
4068 u8 current_uc_mac_address[][0x40];
4072 MLX5_MKC_ACCESS_MODE_PA = 0x0,
4073 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
4074 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
4075 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
4076 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4077 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4081 u8 reserved_at_0[0x1];
4082 u8 free[0x1];
4083 u8 reserved_at_2[0x1];
4084 u8 access_mode_4_2[0x3];
4085 u8 reserved_at_6[0x7];
4086 u8 relaxed_ordering_write[0x1];
4087 u8 reserved_at_e[0x1];
4088 u8 small_fence_on_rdma_read_response[0x1];
4089 u8 umr_en[0x1];
4090 u8 a[0x1];
4091 u8 rw[0x1];
4092 u8 rr[0x1];
4093 u8 lw[0x1];
4094 u8 lr[0x1];
4095 u8 access_mode_1_0[0x2];
4096 u8 reserved_at_18[0x2];
4097 u8 ma_translation_mode[0x2];
4098 u8 reserved_at_1c[0x4];
4100 u8 qpn[0x18];
4101 u8 mkey_7_0[0x8];
4103 u8 reserved_at_40[0x20];
4105 u8 length64[0x1];
4106 u8 bsf_en[0x1];
4107 u8 sync_umr[0x1];
4108 u8 reserved_at_63[0x2];
4109 u8 expected_sigerr_count[0x1];
4110 u8 reserved_at_66[0x1];
4111 u8 en_rinval[0x1];
4112 u8 pd[0x18];
4114 u8 start_addr[0x40];
4116 u8 len[0x40];
4118 u8 bsf_octword_size[0x20];
4120 u8 reserved_at_120[0x80];
4122 u8 translations_octword_size[0x20];
4124 u8 reserved_at_1c0[0x19];
4125 u8 relaxed_ordering_read[0x1];
4126 u8 reserved_at_1d9[0x1];
4127 u8 log_page_size[0x5];
4129 u8 reserved_at_1e0[0x20];
4133 u8 reserved_at_0[0x10];
4134 u8 pkey[0x10];
4138 u8 array128_auto[16][0x8];
4142 u8 field_select[0x20];
4144 u8 reserved_at_20[0xe0];
4146 u8 sm_virt_aware[0x1];
4147 u8 has_smi[0x1];
4148 u8 has_raw[0x1];
4149 u8 grh_required[0x1];
4150 u8 reserved_at_104[0xc];
4151 u8 port_physical_state[0x4];
4152 u8 vport_state_policy[0x4];
4153 u8 port_state[0x4];
4154 u8 vport_state[0x4];
4156 u8 reserved_at_120[0x20];
4158 u8 system_image_guid[0x40];
4160 u8 port_guid[0x40];
4162 u8 node_guid[0x40];
4164 u8 cap_mask1[0x20];
4166 u8 cap_mask1_field_select[0x20];
4168 u8 cap_mask2[0x20];
4170 u8 cap_mask2_field_select[0x20];
4172 u8 reserved_at_280[0x80];
4174 u8 lid[0x10];
4175 u8 reserved_at_310[0x4];
4176 u8 init_type_reply[0x4];
4177 u8 lmc[0x3];
4178 u8 subnet_timeout[0x5];
4180 u8 sm_lid[0x10];
4181 u8 sm_sl[0x4];
4182 u8 reserved_at_334[0xc];
4184 u8 qkey_violation_counter[0x10];
4185 u8 pkey_violation_counter[0x10];
4187 u8 reserved_at_360[0xca0];
4191 u8 fdb_to_vport_reg_c[0x1];
4192 u8 reserved_at_1[0x2];
4193 u8 vport_svlan_strip[0x1];
4194 u8 vport_cvlan_strip[0x1];
4195 u8 vport_svlan_insert[0x1];
4196 u8 vport_cvlan_insert[0x2];
4197 u8 fdb_to_vport_reg_c_id[0x8];
4198 u8 reserved_at_10[0x10];
4200 u8 reserved_at_20[0x20];
4202 u8 svlan_cfi[0x1];
4203 u8 svlan_pcp[0x3];
4204 u8 svlan_id[0xc];
4205 u8 cvlan_cfi[0x1];
4206 u8 cvlan_pcp[0x3];
4207 u8 cvlan_id[0xc];
4209 u8 reserved_at_60[0x720];
4211 u8 sw_steering_vport_icm_address_rx[0x40];
4213 u8 sw_steering_vport_icm_address_tx[0x40];
4217 MLX5_EQC_STATUS_OK = 0x0,
4218 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
4222 MLX5_EQC_ST_ARMED = 0x9,
4223 MLX5_EQC_ST_FIRED = 0xa,
4227 u8 status[0x4];
4228 u8 reserved_at_4[0x9];
4229 u8 ec[0x1];
4230 u8 oi[0x1];
4231 u8 reserved_at_f[0x5];
4232 u8 st[0x4];
4233 u8 reserved_at_18[0x8];
4235 u8 reserved_at_20[0x20];
4237 u8 reserved_at_40[0x14];
4238 u8 page_offset[0x6];
4239 u8 reserved_at_5a[0x6];
4241 u8 reserved_at_60[0x3];
4242 u8 log_eq_size[0x5];
4243 u8 uar_page[0x18];
4245 u8 reserved_at_80[0x20];
4247 u8 reserved_at_a0[0x14];
4248 u8 intr[0xc];
4250 u8 reserved_at_c0[0x3];
4251 u8 log_page_size[0x5];
4252 u8 reserved_at_c8[0x18];
4254 u8 reserved_at_e0[0x60];
4256 u8 reserved_at_140[0x8];
4257 u8 consumer_counter[0x18];
4259 u8 reserved_at_160[0x8];
4260 u8 producer_counter[0x18];
4262 u8 reserved_at_180[0x80];
4266 MLX5_DCTC_STATE_ACTIVE = 0x0,
4267 MLX5_DCTC_STATE_DRAINING = 0x1,
4268 MLX5_DCTC_STATE_DRAINED = 0x2,
4272 MLX5_DCTC_CS_RES_DISABLE = 0x0,
4273 MLX5_DCTC_CS_RES_NA = 0x1,
4274 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
4278 MLX5_DCTC_MTU_256_BYTES = 0x1,
4279 MLX5_DCTC_MTU_512_BYTES = 0x2,
4280 MLX5_DCTC_MTU_1K_BYTES = 0x3,
4281 MLX5_DCTC_MTU_2K_BYTES = 0x4,
4282 MLX5_DCTC_MTU_4K_BYTES = 0x5,
4286 u8 reserved_at_0[0x4];
4287 u8 state[0x4];
4288 u8 reserved_at_8[0x18];
4290 u8 reserved_at_20[0x8];
4291 u8 user_index[0x18];
4293 u8 reserved_at_40[0x8];
4294 u8 cqn[0x18];
4296 u8 counter_set_id[0x8];
4297 u8 atomic_mode[0x4];
4298 u8 rre[0x1];
4299 u8 rwe[0x1];
4300 u8 rae[0x1];
4301 u8 atomic_like_write_en[0x1];
4302 u8 latency_sensitive[0x1];
4303 u8 rlky[0x1];
4304 u8 free_ar[0x1];
4305 u8 reserved_at_73[0xd];
4307 u8 reserved_at_80[0x8];
4308 u8 cs_res[0x8];
4309 u8 reserved_at_90[0x3];
4310 u8 min_rnr_nak[0x5];
4311 u8 reserved_at_98[0x8];
4313 u8 reserved_at_a0[0x8];
4314 u8 srqn_xrqn[0x18];
4316 u8 reserved_at_c0[0x8];
4317 u8 pd[0x18];
4319 u8 tclass[0x8];
4320 u8 reserved_at_e8[0x4];
4321 u8 flow_label[0x14];
4323 u8 dc_access_key[0x40];
4325 u8 reserved_at_140[0x5];
4326 u8 mtu[0x3];
4327 u8 port[0x8];
4328 u8 pkey_index[0x10];
4330 u8 reserved_at_160[0x8];
4331 u8 my_addr_index[0x8];
4332 u8 reserved_at_170[0x8];
4333 u8 hop_limit[0x8];
4335 u8 dc_access_key_violation_count[0x20];
4337 u8 reserved_at_1a0[0x14];
4338 u8 dei_cfi[0x1];
4339 u8 eth_prio[0x3];
4340 u8 ecn[0x2];
4341 u8 dscp[0x6];
4343 u8 reserved_at_1c0[0x20];
4344 u8 ece[0x20];
4348 MLX5_CQC_STATUS_OK = 0x0,
4349 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
4350 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
4354 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
4355 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
4359 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
4360 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
4361 MLX5_CQC_ST_FIRED = 0xa,
4365 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4366 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4371 u8 status[0x4];
4372 u8 reserved_at_4[0x2];
4373 u8 dbr_umem_valid[0x1];
4374 u8 apu_cq[0x1];
4375 u8 cqe_sz[0x3];
4376 u8 cc[0x1];
4377 u8 reserved_at_c[0x1];
4378 u8 scqe_break_moderation_en[0x1];
4379 u8 oi[0x1];
4380 u8 cq_period_mode[0x2];
4381 u8 cqe_comp_en[0x1];
4382 u8 mini_cqe_res_format[0x2];
4383 u8 st[0x4];
4384 u8 reserved_at_18[0x6];
4385 u8 cqe_compression_layout[0x2];
4387 u8 reserved_at_20[0x20];
4389 u8 reserved_at_40[0x14];
4390 u8 page_offset[0x6];
4391 u8 reserved_at_5a[0x6];
4393 u8 reserved_at_60[0x3];
4394 u8 log_cq_size[0x5];
4395 u8 uar_page[0x18];
4397 u8 reserved_at_80[0x4];
4398 u8 cq_period[0xc];
4399 u8 cq_max_count[0x10];
4401 u8 c_eqn_or_apu_element[0x20];
4403 u8 reserved_at_c0[0x3];
4404 u8 log_page_size[0x5];
4405 u8 reserved_at_c8[0x18];
4407 u8 reserved_at_e0[0x20];
4409 u8 reserved_at_100[0x8];
4410 u8 last_notified_index[0x18];
4412 u8 reserved_at_120[0x8];
4413 u8 last_solicit_index[0x18];
4415 u8 reserved_at_140[0x8];
4416 u8 consumer_counter[0x18];
4418 u8 reserved_at_160[0x8];
4419 u8 producer_counter[0x18];
4421 u8 reserved_at_180[0x40];
4423 u8 dbr_addr[0x40];
4431 u8 reserved_at_0[0x800];
4435 u8 reserved_at_0[0xc0];
4437 u8 reserved_at_c0[0x8];
4438 u8 ieee_vendor_id[0x18];
4440 u8 reserved_at_e0[0x10];
4441 u8 vsd_vendor_id[0x10];
4443 u8 vsd[208][0x8];
4445 u8 vsd_contd_psid[16][0x8];
4449 MLX5_XRQC_STATE_GOOD = 0x0,
4450 MLX5_XRQC_STATE_ERROR = 0x1,
4454 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4455 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4459 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4463 u8 log_matching_list_sz[0x4];
4464 u8 reserved_at_4[0xc];
4465 u8 append_next_index[0x10];
4467 u8 sw_phase_cnt[0x10];
4468 u8 hw_phase_cnt[0x10];
4470 u8 reserved_at_40[0x40];
4474 u8 state[0x4];
4475 u8 rlkey[0x1];
4476 u8 reserved_at_5[0xf];
4477 u8 topology[0x4];
4478 u8 reserved_at_18[0x4];
4479 u8 offload[0x4];
4481 u8 reserved_at_20[0x8];
4482 u8 user_index[0x18];
4484 u8 reserved_at_40[0x8];
4485 u8 cqn[0x18];
4487 u8 reserved_at_60[0xa0];
4491 u8 reserved_at_180[0x280];
4499 u8 reserved_at_0[0x20];
4506 u8 reserved_at_0[0x20];
4521 u8 reserved_at_0[0x7c0];
4526 u8 reserved_at_0[0x7c0];
4542 u8 reserved_at_0[0xe0];
4546 u8 reserved_at_0[0x100];
4548 u8 assert_existptr[0x20];
4550 u8 assert_callra[0x20];
4552 u8 reserved_at_140[0x20];
4554 u8 time[0x20];
4556 u8 fw_version[0x20];
4558 u8 hw_id[0x20];
4560 u8 rfr[0x1];
4561 u8 reserved_at_1c1[0x3];
4562 u8 valid[0x1];
4563 u8 severity[0x3];
4564 u8 reserved_at_1c8[0x18];
4566 u8 irisc_index[0x8];
4567 u8 synd[0x8];
4568 u8 ext_synd[0x10];
4572 u8 no_lb[0x1];
4573 u8 reserved_at_1[0x7];
4574 u8 port[0x8];
4575 u8 reserved_at_10[0x10];
4577 u8 reserved_at_20[0x60];
4581 u8 traffic_class[0x4];
4582 u8 reserved_at_4[0xc];
4583 u8 vport_number[0x10];
4587 u8 reserved_at_0[0x10];
4588 u8 vport_number[0x10];
4592 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4593 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4594 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4598 u8 reserved_at_0[0x8];
4599 u8 tsar_type[0x8];
4600 u8 reserved_at_10[0x10];
4604 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4605 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4609 u8 status[0x8];
4610 u8 reserved_at_8[0x18];
4612 u8 syndrome[0x20];
4614 u8 reserved_at_40[0x3f];
4616 u8 state[0x1];
4620 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
4621 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
4622 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4626 u8 opcode[0x10];
4627 u8 reserved_at_10[0x10];
4629 u8 reserved_at_20[0x10];
4630 u8 op_mod[0x10];
4632 u8 reserved_at_40[0x10];
4633 u8 profile[0x10];
4635 u8 reserved_at_60[0x20];
4639 u8 status[0x8];
4640 u8 reserved_at_8[0x18];
4642 u8 syndrome[0x20];
4644 u8 reserved_at_40[0x40];
4648 u8 opcode[0x10];
4649 u8 uid[0x10];
4651 u8 reserved_at_20[0x10];
4652 u8 op_mod[0x10];
4654 u8 reserved_at_40[0x8];
4655 u8 qpn[0x18];
4657 u8 reserved_at_60[0x20];
4659 u8 opt_param_mask[0x20];
4661 u8 reserved_at_a0[0x20];
4665 u8 reserved_at_800[0x80];
4669 u8 status[0x8];
4670 u8 reserved_at_8[0x18];
4672 u8 syndrome[0x20];
4674 u8 reserved_at_40[0x40];
4678 u8 opcode[0x10];
4679 u8 uid[0x10];
4681 u8 reserved_at_20[0x10];
4682 u8 op_mod[0x10];
4684 u8 reserved_at_40[0x8];
4685 u8 qpn[0x18];
4687 u8 reserved_at_60[0x20];
4689 u8 opt_param_mask[0x20];
4691 u8 reserved_at_a0[0x20];
4695 u8 reserved_at_800[0x80];
4699 u8 status[0x8];
4700 u8 reserved_at_8[0x18];
4702 u8 syndrome[0x20];
4704 u8 reserved_at_40[0x40];
4708 u8 opcode[0x10];
4709 u8 reserved_at_10[0x10];
4711 u8 reserved_at_20[0x10];
4712 u8 op_mod[0x10];
4714 u8 roce_address_index[0x10];
4715 u8 reserved_at_50[0xc];
4716 u8 vhca_port_num[0x4];
4718 u8 reserved_at_60[0x20];
4724 u8 status[0x8];
4725 u8 reserved_at_8[0x18];
4727 u8 syndrome[0x20];
4729 u8 reserved_at_40[0x40];
4733 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4734 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4738 u8 opcode[0x10];
4739 u8 reserved_at_10[0x10];
4741 u8 reserved_at_20[0x10];
4742 u8 op_mod[0x10];
4744 u8 reserved_at_40[0x20];
4746 u8 reserved_at_60[0x6];
4747 u8 demux_mode[0x2];
4748 u8 reserved_at_68[0x18];
4752 u8 status[0x8];
4753 u8 reserved_at_8[0x18];
4755 u8 syndrome[0x20];
4757 u8 reserved_at_40[0x40];
4761 u8 opcode[0x10];
4762 u8 reserved_at_10[0x10];
4764 u8 reserved_at_20[0x10];
4765 u8 op_mod[0x10];
4767 u8 reserved_at_40[0x60];
4769 u8 reserved_at_a0[0x8];
4770 u8 table_index[0x18];
4772 u8 reserved_at_c0[0x20];
4774 u8 reserved_at_e0[0x10];
4775 u8 silent_mode_valid[0x1];
4776 u8 silent_mode[0x1];
4777 u8 reserved_at_f2[0x1];
4778 u8 vlan_valid[0x1];
4779 u8 vlan[0xc];
4783 u8 reserved_at_140[0xc0];
4787 u8 status[0x8];
4788 u8 reserved_at_8[0x18];
4790 u8 syndrome[0x20];
4792 u8 reserved_at_40[0x40];
4796 u8 opcode[0x10];
4797 u8 reserved_at_10[0x10];
4799 u8 reserved_at_20[0x10];
4800 u8 op_mod[0x10];
4802 u8 reserved_at_40[0x10];
4803 u8 current_issi[0x10];
4805 u8 reserved_at_60[0x20];
4809 u8 status[0x8];
4810 u8 reserved_at_8[0x18];
4812 u8 syndrome[0x20];
4814 u8 reserved_at_40[0x40];
4818 u8 opcode[0x10];
4819 u8 reserved_at_10[0x10];
4821 u8 reserved_at_20[0x10];
4822 u8 op_mod[0x10];
4824 u8 other_function[0x1];
4825 u8 ec_vf_function[0x1];
4826 u8 reserved_at_42[0xe];
4827 u8 function_id[0x10];
4829 u8 reserved_at_60[0x20];
4835 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4836 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4837 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4838 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4839 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
4843 u8 status[0x8];
4844 u8 reserved_at_8[0x18];
4846 u8 syndrome[0x20];
4848 u8 reserved_at_40[0x40];
4852 u8 opcode[0x10];
4853 u8 reserved_at_10[0x10];
4855 u8 reserved_at_20[0x10];
4856 u8 op_mod[0x10];
4858 u8 other_vport[0x1];
4859 u8 reserved_at_41[0xf];
4860 u8 vport_number[0x10];
4862 u8 reserved_at_60[0x20];
4864 u8 table_type[0x8];
4865 u8 reserved_at_88[0x18];
4867 u8 reserved_at_a0[0x8];
4868 u8 table_id[0x18];
4870 u8 ignore_flow_level[0x1];
4871 u8 reserved_at_c1[0x17];
4872 u8 modify_enable_mask[0x8];
4874 u8 reserved_at_e0[0x20];
4876 u8 flow_index[0x20];
4878 u8 reserved_at_120[0xe0];
4884 u8 status[0x8];
4885 u8 reserved_at_8[0x18];
4887 u8 syndrome[0x20];
4889 u8 reserved_at_40[0x20];
4890 u8 ece[0x20];
4894 u8 opcode[0x10];
4895 u8 uid[0x10];
4897 u8 reserved_at_20[0x10];
4898 u8 op_mod[0x10];
4900 u8 reserved_at_40[0x8];
4901 u8 qpn[0x18];
4903 u8 reserved_at_60[0x20];
4905 u8 opt_param_mask[0x20];
4907 u8 ece[0x20];
4911 u8 reserved_at_800[0x80];
4915 u8 status[0x8];
4916 u8 reserved_at_8[0x18];
4918 u8 syndrome[0x20];
4920 u8 reserved_at_40[0x20];
4921 u8 ece[0x20];
4925 u8 opcode[0x10];
4926 u8 uid[0x10];
4928 u8 reserved_at_20[0x10];
4929 u8 op_mod[0x10];
4931 u8 reserved_at_40[0x8];
4932 u8 qpn[0x18];
4934 u8 reserved_at_60[0x20];
4936 u8 opt_param_mask[0x20];
4938 u8 ece[0x20];
4942 u8 reserved_at_800[0x80];
4946 u8 status[0x8];
4947 u8 reserved_at_8[0x18];
4949 u8 syndrome[0x20];
4951 u8 reserved_at_40[0x20];
4952 u8 ece[0x20];
4956 u8 opcode[0x10];
4957 u8 uid[0x10];
4959 u8 reserved_at_20[0x10];
4960 u8 op_mod[0x10];
4962 u8 reserved_at_40[0x8];
4963 u8 qpn[0x18];
4965 u8 reserved_at_60[0x20];
4967 u8 opt_param_mask[0x20];
4969 u8 ece[0x20];
4973 u8 reserved_at_800[0x80];
4977 u8 status[0x8];
4978 u8 reserved_at_8[0x18];
4980 u8 syndrome[0x20];
4982 u8 reserved_at_40[0x40];
4988 u8 opcode[0x10];
4989 u8 reserved_at_10[0x10];
4991 u8 reserved_at_20[0x10];
4992 u8 op_mod[0x10];
4994 u8 reserved_at_40[0x8];
4995 u8 xrqn[0x18];
4997 u8 reserved_at_60[0x20];
5001 u8 status[0x8];
5002 u8 reserved_at_8[0x18];
5004 u8 syndrome[0x20];
5006 u8 reserved_at_40[0x40];
5010 u8 reserved_at_280[0x600];
5012 u8 pas[][0x40];
5016 u8 opcode[0x10];
5017 u8 reserved_at_10[0x10];
5019 u8 reserved_at_20[0x10];
5020 u8 op_mod[0x10];
5022 u8 reserved_at_40[0x8];
5023 u8 xrc_srqn[0x18];
5025 u8 reserved_at_60[0x20];
5029 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
5030 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
5034 u8 status[0x8];
5035 u8 reserved_at_8[0x18];
5037 u8 syndrome[0x20];
5039 u8 reserved_at_40[0x20];
5041 u8 reserved_at_60[0x18];
5042 u8 admin_state[0x4];
5043 u8 state[0x4];
5047 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
5048 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
5049 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
5053 u8 opcode[0x10];
5054 u8 uid[0x10];
5056 u8 reserved_at_20[0x10];
5057 u8 op_mod[0x10];
5059 u8 reserved_at_40[0x20];
5061 u8 reserved_at_60[0x20];
5065 u8 status[0x8];
5066 u8 reserved_at_8[0x18];
5068 u8 syndrome[0x20];
5070 u8 reserved_at_40[0x40];
5074 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
5075 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5079 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
5080 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
5081 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
5082 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5083 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
5084 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
5088 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
5092 u8 reserved_at_0[0x4];
5093 u8 type[0x4];
5094 u8 reserved_at_8[0x8];
5095 u8 counter[0x10];
5097 u8 counter_group_id[0x20];
5106 u8 opcode[0x10];
5107 u8 uid[0x10];
5109 u8 reserved_at_20[0x10];
5110 u8 op_mod[0x10];
5112 u8 reserved_at_40[0x10];
5113 u8 num_of_counters[0x10];
5115 u8 reserved_at_60[0x20];
5121 u8 status[0x8];
5122 u8 reserved_at_8[0x18];
5124 u8 syndrome[0x20];
5126 u8 reserved_at_40[0x40];
5130 u8 opcode[0x10];
5131 u8 reserved_at_10[0x10];
5133 u8 reserved_at_20[0x10];
5134 u8 op_mod[0x10];
5136 u8 other_vport[0x1];
5137 u8 reserved_at_41[0xf];
5138 u8 vport_number[0x10];
5140 u8 reserved_at_60[0x20];
5144 u8 status[0x8];
5145 u8 reserved_at_8[0x18];
5147 u8 syndrome[0x20];
5149 u8 reserved_at_40[0x40];
5155 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
5159 u8 opcode[0x10];
5160 u8 reserved_at_10[0x10];
5162 u8 reserved_at_20[0x10];
5163 u8 op_mod[0x10];
5165 u8 other_vport[0x1];
5166 u8 reserved_at_41[0xf];
5167 u8 vport_number[0x10];
5169 u8 reserved_at_60[0x20];
5173 u8 status[0x8];
5174 u8 reserved_at_8[0x18];
5176 u8 syndrome[0x20];
5178 u8 reserved_at_40[0x40];
5206 u8 reserved_at_700[0x980];
5210 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
5214 u8 opcode[0x10];
5215 u8 reserved_at_10[0x10];
5217 u8 reserved_at_20[0x10];
5218 u8 op_mod[0x10];
5220 u8 other_vport[0x1];
5221 u8 reserved_at_41[0xb];
5222 u8 port_num[0x4];
5223 u8 vport_number[0x10];
5225 u8 reserved_at_60[0x60];
5227 u8 clear[0x1];
5228 u8 reserved_at_c1[0x1f];
5230 u8 reserved_at_e0[0x20];
5234 u8 status[0x8];
5235 u8 reserved_at_8[0x18];
5237 u8 syndrome[0x20];
5239 u8 reserved_at_40[0x40];
5245 u8 opcode[0x10];
5246 u8 reserved_at_10[0x10];
5248 u8 reserved_at_20[0x10];
5249 u8 op_mod[0x10];
5251 u8 reserved_at_40[0x8];
5252 u8 tisn[0x18];
5254 u8 reserved_at_60[0x20];
5258 u8 status[0x8];
5259 u8 reserved_at_8[0x18];
5261 u8 syndrome[0x20];
5263 u8 reserved_at_40[0xc0];
5269 u8 opcode[0x10];
5270 u8 reserved_at_10[0x10];
5272 u8 reserved_at_20[0x10];
5273 u8 op_mod[0x10];
5275 u8 reserved_at_40[0x8];
5276 u8 tirn[0x18];
5278 u8 reserved_at_60[0x20];
5282 u8 status[0x8];
5283 u8 reserved_at_8[0x18];
5285 u8 syndrome[0x20];
5287 u8 reserved_at_40[0x40];
5291 u8 reserved_at_280[0x600];
5293 u8 pas[][0x40];
5297 u8 opcode[0x10];
5298 u8 reserved_at_10[0x10];
5300 u8 reserved_at_20[0x10];
5301 u8 op_mod[0x10];
5303 u8 reserved_at_40[0x8];
5304 u8 srqn[0x18];
5306 u8 reserved_at_60[0x20];
5310 u8 status[0x8];
5311 u8 reserved_at_8[0x18];
5313 u8 syndrome[0x20];
5315 u8 reserved_at_40[0xc0];
5321 u8 opcode[0x10];
5322 u8 reserved_at_10[0x10];
5324 u8 reserved_at_20[0x10];
5325 u8 op_mod[0x10];
5327 u8 reserved_at_40[0x8];
5328 u8 sqn[0x18];
5330 u8 reserved_at_60[0x20];
5334 u8 status[0x8];
5335 u8 reserved_at_8[0x18];
5337 u8 syndrome[0x20];
5339 u8 dump_fill_mkey[0x20];
5341 u8 resd_lkey[0x20];
5343 u8 null_mkey[0x20];
5345 u8 terminate_scatter_list_mkey[0x20];
5347 u8 repeated_mkey[0x20];
5349 u8 reserved_at_a0[0x20];
5353 u8 opcode[0x10];
5354 u8 reserved_at_10[0x10];
5356 u8 reserved_at_20[0x10];
5357 u8 op_mod[0x10];
5359 u8 reserved_at_40[0x40];
5363 u8 opcode[0x10];
5364 u8 reserved_at_10[0x10];
5366 u8 reserved_at_20[0x10];
5367 u8 op_mod[0x10];
5369 u8 reserved_at_40[0xc0];
5373 u8 reserved_at_300[0x100];
5377 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5378 SCHEDULING_HIERARCHY_NIC = 0x3,
5382 u8 opcode[0x10];
5383 u8 reserved_at_10[0x10];
5385 u8 reserved_at_20[0x10];
5386 u8 op_mod[0x10];
5388 u8 scheduling_hierarchy[0x8];
5389 u8 reserved_at_48[0x18];
5391 u8 scheduling_element_id[0x20];
5393 u8 reserved_at_80[0x180];
5397 u8 status[0x8];
5398 u8 reserved_at_8[0x18];
5400 u8 syndrome[0x20];
5402 u8 reserved_at_40[0xc0];
5408 u8 opcode[0x10];
5409 u8 reserved_at_10[0x10];
5411 u8 reserved_at_20[0x10];
5412 u8 op_mod[0x10];
5414 u8 reserved_at_40[0x8];
5415 u8 rqtn[0x18];
5417 u8 reserved_at_60[0x20];
5421 u8 status[0x8];
5422 u8 reserved_at_8[0x18];
5424 u8 syndrome[0x20];
5426 u8 reserved_at_40[0xc0];
5432 u8 opcode[0x10];
5433 u8 reserved_at_10[0x10];
5435 u8 reserved_at_20[0x10];
5436 u8 op_mod[0x10];
5438 u8 reserved_at_40[0x8];
5439 u8 rqn[0x18];
5441 u8 reserved_at_60[0x20];
5445 u8 status[0x8];
5446 u8 reserved_at_8[0x18];
5448 u8 syndrome[0x20];
5450 u8 reserved_at_40[0x40];
5456 u8 opcode[0x10];
5457 u8 reserved_at_10[0x10];
5459 u8 reserved_at_20[0x10];
5460 u8 op_mod[0x10];
5462 u8 roce_address_index[0x10];
5463 u8 reserved_at_50[0xc];
5464 u8 vhca_port_num[0x4];
5466 u8 reserved_at_60[0x20];
5470 u8 status[0x8];
5471 u8 reserved_at_8[0x18];
5473 u8 syndrome[0x20];
5475 u8 reserved_at_40[0xc0];
5481 u8 opcode[0x10];
5482 u8 reserved_at_10[0x10];
5484 u8 reserved_at_20[0x10];
5485 u8 op_mod[0x10];
5487 u8 reserved_at_40[0x8];
5488 u8 rmpn[0x18];
5490 u8 reserved_at_60[0x20];
5494 u8 hw_error_syndrome[0x8];
5495 u8 hw_syndrome_type[0x4];
5496 u8 reserved_at_c[0x4];
5497 u8 vendor_error_syndrome[0x8];
5498 u8 syndrome[0x8];
5502 u8 reserved_at_0[0x60];
5506 u8 reserved_at_80[0x580];
5512 u8 pas[0][0x40];
5516 struct mlx5_ifc_cmd_pas_bits pas[0];
5525 u8 status[0x8];
5526 u8 reserved_at_8[0x18];
5528 u8 syndrome[0x20];
5530 u8 reserved_at_40[0x40];
5532 u8 opt_param_mask[0x20];
5534 u8 ece[0x20];
5538 u8 reserved_at_800[0x80];
5544 u8 opcode[0x10];
5545 u8 reserved_at_10[0x10];
5547 u8 reserved_at_20[0x10];
5548 u8 op_mod[0x10];
5550 u8 qpc_ext[0x1];
5551 u8 reserved_at_41[0x7];
5552 u8 qpn[0x18];
5554 u8 reserved_at_60[0x20];
5558 u8 status[0x8];
5559 u8 reserved_at_8[0x18];
5561 u8 syndrome[0x20];
5563 u8 reserved_at_40[0x40];
5565 u8 rx_write_requests[0x20];
5567 u8 reserved_at_a0[0x20];
5569 u8 rx_read_requests[0x20];
5571 u8 reserved_at_e0[0x20];
5573 u8 rx_atomic_requests[0x20];
5575 u8 reserved_at_120[0x20];
5577 u8 rx_dct_connect[0x20];
5579 u8 reserved_at_160[0x20];
5581 u8 out_of_buffer[0x20];
5583 u8 reserved_at_1a0[0x20];
5585 u8 out_of_sequence[0x20];
5587 u8 reserved_at_1e0[0x20];
5589 u8 duplicate_request[0x20];
5591 u8 reserved_at_220[0x20];
5593 u8 rnr_nak_retry_err[0x20];
5595 u8 reserved_at_260[0x20];
5597 u8 packet_seq_err[0x20];
5599 u8 reserved_at_2a0[0x20];
5601 u8 implied_nak_seq_err[0x20];
5603 u8 reserved_at_2e0[0x20];
5605 u8 local_ack_timeout_err[0x20];
5607 u8 reserved_at_320[0xa0];
5609 u8 resp_local_length_error[0x20];
5611 u8 req_local_length_error[0x20];
5613 u8 resp_local_qp_error[0x20];
5615 u8 local_operation_error[0x20];
5617 u8 resp_local_protection[0x20];
5619 u8 req_local_protection[0x20];
5621 u8 resp_cqe_error[0x20];
5623 u8 req_cqe_error[0x20];
5625 u8 req_mw_binding[0x20];
5627 u8 req_bad_response[0x20];
5629 u8 req_remote_invalid_request[0x20];
5631 u8 resp_remote_invalid_request[0x20];
5633 u8 req_remote_access_errors[0x20];
5635 u8 resp_remote_access_errors[0x20];
5637 u8 req_remote_operation_errors[0x20];
5639 u8 req_transport_retries_exceeded[0x20];
5641 u8 cq_overflow[0x20];
5643 u8 resp_cqe_flush_error[0x20];
5645 u8 req_cqe_flush_error[0x20];
5647 u8 reserved_at_620[0x20];
5649 u8 roce_adp_retrans[0x20];
5651 u8 roce_adp_retrans_to[0x20];
5653 u8 roce_slow_restart[0x20];
5655 u8 roce_slow_restart_cnps[0x20];
5657 u8 roce_slow_restart_trans[0x20];
5659 u8 reserved_at_6e0[0x120];
5663 u8 opcode[0x10];
5664 u8 reserved_at_10[0x10];
5666 u8 reserved_at_20[0x10];
5667 u8 op_mod[0x10];
5669 u8 other_vport[0x1];
5670 u8 reserved_at_41[0xf];
5671 u8 vport_number[0x10];
5673 u8 reserved_at_60[0x60];
5675 u8 clear[0x1];
5676 u8 aggregate[0x1];
5677 u8 reserved_at_c2[0x1e];
5679 u8 reserved_at_e0[0x18];
5680 u8 counter_set_id[0x8];
5684 u8 status[0x8];
5685 u8 reserved_at_8[0x18];
5687 u8 syndrome[0x20];
5689 u8 embedded_cpu_function[0x1];
5690 u8 reserved_at_41[0xf];
5691 u8 function_id[0x10];
5693 u8 num_pages[0x20];
5697 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5698 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5699 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5703 u8 opcode[0x10];
5704 u8 reserved_at_10[0x10];
5706 u8 reserved_at_20[0x10];
5707 u8 op_mod[0x10];
5709 u8 embedded_cpu_function[0x1];
5710 u8 reserved_at_41[0xf];
5711 u8 function_id[0x10];
5713 u8 reserved_at_60[0x20];
5717 u8 status[0x8];
5718 u8 reserved_at_8[0x18];
5720 u8 syndrome[0x20];
5722 u8 reserved_at_40[0x40];
5728 u8 opcode[0x10];
5729 u8 reserved_at_10[0x10];
5731 u8 reserved_at_20[0x10];
5732 u8 op_mod[0x10];
5734 u8 other_vport[0x1];
5735 u8 reserved_at_41[0xf];
5736 u8 vport_number[0x10];
5738 u8 reserved_at_60[0x5];
5739 u8 allowed_list_type[0x3];
5740 u8 reserved_at_68[0x18];
5744 u8 status[0x8];
5745 u8 reserved_at_8[0x18];
5747 u8 syndrome[0x20];
5749 u8 reserved_at_40[0x40];
5753 u8 reserved_at_280[0x600];
5755 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5757 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5761 u8 opcode[0x10];
5762 u8 reserved_at_10[0x10];
5764 u8 reserved_at_20[0x10];
5765 u8 op_mod[0x10];
5767 u8 reserved_at_40[0x8];
5768 u8 mkey_index[0x18];
5770 u8 pg_access[0x1];
5771 u8 reserved_at_61[0x1f];
5775 u8 status[0x8];
5776 u8 reserved_at_8[0x18];
5778 u8 syndrome[0x20];
5780 u8 reserved_at_40[0x40];
5782 u8 mad_dumux_parameters_block[0x20];
5786 u8 opcode[0x10];
5787 u8 reserved_at_10[0x10];
5789 u8 reserved_at_20[0x10];
5790 u8 op_mod[0x10];
5792 u8 reserved_at_40[0x40];
5796 u8 status[0x8];
5797 u8 reserved_at_8[0x18];
5799 u8 syndrome[0x20];
5801 u8 reserved_at_40[0xa0];
5803 u8 reserved_at_e0[0x13];
5804 u8 vlan_valid[0x1];
5805 u8 vlan[0xc];
5809 u8 reserved_at_140[0xc0];
5813 u8 opcode[0x10];
5814 u8 reserved_at_10[0x10];
5816 u8 reserved_at_20[0x10];
5817 u8 op_mod[0x10];
5819 u8 reserved_at_40[0x60];
5821 u8 reserved_at_a0[0x8];
5822 u8 table_index[0x18];
5824 u8 reserved_at_c0[0x140];
5828 u8 status[0x8];
5829 u8 reserved_at_8[0x18];
5831 u8 syndrome[0x20];
5833 u8 reserved_at_40[0x10];
5834 u8 current_issi[0x10];
5836 u8 reserved_at_60[0xa0];
5838 u8 reserved_at_100[76][0x8];
5839 u8 supported_issi_dw0[0x20];
5843 u8 opcode[0x10];
5844 u8 reserved_at_10[0x10];
5846 u8 reserved_at_20[0x10];
5847 u8 op_mod[0x10];
5849 u8 reserved_at_40[0x40];
5853 u8 status[0x8];
5854 u8 reserved_0[0x18];
5856 u8 syndrome[0x20];
5857 u8 reserved_1[0x40];
5861 u8 opcode[0x10];
5862 u8 reserved_0[0x10];
5864 u8 reserved_1[0x10];
5865 u8 op_mod[0x10];
5867 u8 reserved_2[0x40];
5868 u8 driver_version[64][0x8];
5872 u8 status[0x8];
5873 u8 reserved_at_8[0x18];
5875 u8 syndrome[0x20];
5877 u8 reserved_at_40[0x40];
5883 u8 opcode[0x10];
5884 u8 reserved_at_10[0x10];
5886 u8 reserved_at_20[0x10];
5887 u8 op_mod[0x10];
5889 u8 other_vport[0x1];
5890 u8 reserved_at_41[0xb];
5891 u8 port_num[0x4];
5892 u8 vport_number[0x10];
5894 u8 reserved_at_60[0x10];
5895 u8 pkey_index[0x10];
5899 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5905 u8 status[0x8];
5906 u8 reserved_at_8[0x18];
5908 u8 syndrome[0x20];
5910 u8 reserved_at_40[0x20];
5912 u8 gids_num[0x10];
5913 u8 reserved_at_70[0x10];
5919 u8 opcode[0x10];
5920 u8 reserved_at_10[0x10];
5922 u8 reserved_at_20[0x10];
5923 u8 op_mod[0x10];
5925 u8 other_vport[0x1];
5926 u8 reserved_at_41[0xb];
5927 u8 port_num[0x4];
5928 u8 vport_number[0x10];
5930 u8 reserved_at_60[0x10];
5931 u8 gid_index[0x10];
5935 u8 status[0x8];
5936 u8 reserved_at_8[0x18];
5938 u8 syndrome[0x20];
5940 u8 reserved_at_40[0x40];
5946 u8 opcode[0x10];
5947 u8 reserved_at_10[0x10];
5949 u8 reserved_at_20[0x10];
5950 u8 op_mod[0x10];
5952 u8 other_vport[0x1];
5953 u8 reserved_at_41[0xb];
5954 u8 port_num[0x4];
5955 u8 vport_number[0x10];
5957 u8 reserved_at_60[0x20];
5961 u8 status[0x8];
5962 u8 reserved_at_8[0x18];
5964 u8 syndrome[0x20];
5966 u8 reserved_at_40[0x40];
5972 u8 opcode[0x10];
5973 u8 reserved_at_10[0x10];
5975 u8 reserved_at_20[0x10];
5976 u8 op_mod[0x10];
5978 u8 other_function[0x1];
5979 u8 ec_vf_function[0x1];
5980 u8 reserved_at_42[0xe];
5981 u8 function_id[0x10];
5983 u8 reserved_at_60[0x20];
5987 u8 roce[0x1];
5988 u8 reserved_at_1[0x27f];
5992 u8 status[0x8];
5993 u8 reserved_at_8[0x18];
5995 u8 syndrome[0x20];
5997 u8 reserved_at_40[0x40];
6003 u8 opcode[0x10];
6004 u8 reserved_at_10[0x10];
6006 u8 reserved_at_20[0x10];
6007 u8 op_mod[0x10];
6009 u8 reserved_at_40[0x10];
6010 u8 function_id[0x10];
6012 u8 reserved_at_60[0x20];
6016 u8 status[0x8];
6017 u8 reserved_at_8[0x18];
6019 u8 syndrome[0x20];
6021 u8 reserved_at_40[0x40];
6025 u8 opcode[0x10];
6026 u8 reserved_at_10[0x10];
6028 u8 reserved_at_20[0x10];
6029 u8 op_mod[0x10];
6031 u8 reserved_at_40[0x10];
6032 u8 function_id[0x10];
6033 u8 field_select[0x20];
6039 u8 reformat_en[0x1];
6040 u8 decap_en[0x1];
6041 u8 sw_owner[0x1];
6042 u8 termination_table[0x1];
6043 u8 table_miss_action[0x4];
6044 u8 level[0x8];
6045 u8 reserved_at_10[0x8];
6046 u8 log_size[0x8];
6048 u8 reserved_at_20[0x8];
6049 u8 table_miss_id[0x18];
6051 u8 reserved_at_40[0x8];
6052 u8 lag_master_next_table_id[0x18];
6054 u8 reserved_at_60[0x60];
6056 u8 sw_owner_icm_root_1[0x40];
6058 u8 sw_owner_icm_root_0[0x40];
6063 u8 status[0x8];
6064 u8 reserved_at_8[0x18];
6066 u8 syndrome[0x20];
6068 u8 reserved_at_40[0x80];
6074 u8 opcode[0x10];
6075 u8 reserved_at_10[0x10];
6077 u8 reserved_at_20[0x10];
6078 u8 op_mod[0x10];
6080 u8 reserved_at_40[0x40];
6082 u8 table_type[0x8];
6083 u8 reserved_at_88[0x18];
6085 u8 reserved_at_a0[0x8];
6086 u8 table_id[0x18];
6088 u8 reserved_at_c0[0x140];
6092 u8 status[0x8];
6093 u8 reserved_at_8[0x18];
6095 u8 syndrome[0x20];
6097 u8 reserved_at_40[0x1c0];
6103 u8 opcode[0x10];
6104 u8 reserved_at_10[0x10];
6106 u8 reserved_at_20[0x10];
6107 u8 op_mod[0x10];
6109 u8 reserved_at_40[0x40];
6111 u8 table_type[0x8];
6112 u8 reserved_at_88[0x18];
6114 u8 reserved_at_a0[0x8];
6115 u8 table_id[0x18];
6117 u8 reserved_at_c0[0x40];
6119 u8 flow_index[0x20];
6121 u8 reserved_at_120[0xe0];
6125 u8 reserved_at_0[0x100];
6127 u8 metadata_reg_c_0[0x20];
6129 u8 metadata_reg_c_1[0x20];
6131 u8 outer_dmac_47_16[0x20];
6133 u8 outer_dmac_15_0[0x10];
6134 u8 outer_ethertype[0x10];
6136 u8 reserved_at_180[0x1];
6137 u8 sx_sniffer[0x1];
6138 u8 functional_lb[0x1];
6139 u8 outer_ip_frag[0x1];
6140 u8 outer_qp_type[0x2];
6141 u8 outer_encap_type[0x2];
6142 u8 port_number[0x2];
6143 u8 outer_l3_type[0x2];
6144 u8 outer_l4_type[0x2];
6145 u8 outer_first_vlan_type[0x2];
6146 u8 outer_first_vlan_prio[0x3];
6147 u8 outer_first_vlan_cfi[0x1];
6148 u8 outer_first_vlan_vid[0xc];
6150 u8 outer_l4_type_ext[0x4];
6151 u8 reserved_at_1a4[0x2];
6152 u8 outer_ipsec_layer[0x2];
6153 u8 outer_l2_type[0x2];
6154 u8 force_lb[0x1];
6155 u8 outer_l2_ok[0x1];
6156 u8 outer_l3_ok[0x1];
6157 u8 outer_l4_ok[0x1];
6158 u8 outer_second_vlan_type[0x2];
6159 u8 outer_second_vlan_prio[0x3];
6160 u8 outer_second_vlan_cfi[0x1];
6161 u8 outer_second_vlan_vid[0xc];
6163 u8 outer_smac_47_16[0x20];
6165 u8 outer_smac_15_0[0x10];
6166 u8 inner_ipv4_checksum_ok[0x1];
6167 u8 inner_l4_checksum_ok[0x1];
6168 u8 outer_ipv4_checksum_ok[0x1];
6169 u8 outer_l4_checksum_ok[0x1];
6170 u8 inner_l3_ok[0x1];
6171 u8 inner_l4_ok[0x1];
6172 u8 outer_l3_ok_duplicate[0x1];
6173 u8 outer_l4_ok_duplicate[0x1];
6174 u8 outer_tcp_cwr[0x1];
6175 u8 outer_tcp_ece[0x1];
6176 u8 outer_tcp_urg[0x1];
6177 u8 outer_tcp_ack[0x1];
6178 u8 outer_tcp_psh[0x1];
6179 u8 outer_tcp_rst[0x1];
6180 u8 outer_tcp_syn[0x1];
6181 u8 outer_tcp_fin[0x1];
6185 u8 reserved_at_0[0x100];
6187 u8 outer_ip_src_addr[0x20];
6189 u8 outer_ip_dest_addr[0x20];
6191 u8 outer_l4_sport[0x10];
6192 u8 outer_l4_dport[0x10];
6194 u8 reserved_at_160[0x1];
6195 u8 sx_sniffer[0x1];
6196 u8 functional_lb[0x1];
6197 u8 outer_ip_frag[0x1];
6198 u8 outer_qp_type[0x2];
6199 u8 outer_encap_type[0x2];
6200 u8 port_number[0x2];
6201 u8 outer_l3_type[0x2];
6202 u8 outer_l4_type[0x2];
6203 u8 outer_first_vlan_type[0x2];
6204 u8 outer_first_vlan_prio[0x3];
6205 u8 outer_first_vlan_cfi[0x1];
6206 u8 outer_first_vlan_vid[0xc];
6208 u8 metadata_reg_c_0[0x20];
6210 u8 outer_dmac_47_16[0x20];
6212 u8 outer_smac_47_16[0x20];
6214 u8 outer_smac_15_0[0x10];
6215 u8 outer_dmac_15_0[0x10];
6219 u8 reserved_at_0[0x100];
6221 u8 inner_ip_src_addr[0x20];
6223 u8 inner_ip_dest_addr[0x20];
6225 u8 inner_l4_sport[0x10];
6226 u8 inner_l4_dport[0x10];
6228 u8 reserved_at_160[0x1];
6229 u8 sx_sniffer[0x1];
6230 u8 functional_lb[0x1];
6231 u8 inner_ip_frag[0x1];
6232 u8 inner_qp_type[0x2];
6233 u8 inner_encap_type[0x2];
6234 u8 port_number[0x2];
6235 u8 inner_l3_type[0x2];
6236 u8 inner_l4_type[0x2];
6237 u8 inner_first_vlan_type[0x2];
6238 u8 inner_first_vlan_prio[0x3];
6239 u8 inner_first_vlan_cfi[0x1];
6240 u8 inner_first_vlan_vid[0xc];
6242 u8 tunnel_header_0[0x20];
6244 u8 inner_dmac_47_16[0x20];
6246 u8 inner_smac_47_16[0x20];
6248 u8 inner_smac_15_0[0x10];
6249 u8 inner_dmac_15_0[0x10];
6253 u8 reserved_at_0[0xc0];
6255 u8 outer_ip_dest_addr[0x80];
6257 u8 outer_ip_src_addr[0x80];
6259 u8 outer_l4_sport[0x10];
6260 u8 outer_l4_dport[0x10];
6262 u8 reserved_at_1e0[0x20];
6266 u8 reserved_at_0[0xa0];
6268 u8 outer_ip_dest_addr[0x80];
6270 u8 outer_ip_src_addr[0x80];
6272 u8 outer_dmac_47_16[0x20];
6274 u8 outer_smac_47_16[0x20];
6276 u8 outer_smac_15_0[0x10];
6277 u8 outer_dmac_15_0[0x10];
6281 u8 reserved_at_0[0xc0];
6283 u8 inner_ip_dest_addr[0x80];
6285 u8 inner_ip_src_addr[0x80];
6287 u8 inner_l4_sport[0x10];
6288 u8 inner_l4_dport[0x10];
6290 u8 reserved_at_1e0[0x20];
6294 u8 reserved_at_0[0xa0];
6296 u8 inner_ip_dest_addr[0x80];
6298 u8 inner_ip_src_addr[0x80];
6300 u8 inner_dmac_47_16[0x20];
6302 u8 inner_smac_47_16[0x20];
6304 u8 inner_smac_15_0[0x10];
6305 u8 inner_dmac_15_0[0x10];
6312 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6313 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6318 u8 reserved_at_1c0[5][0x20];
6319 u8 match_dw_8[0x20];
6320 u8 match_dw_7[0x20];
6321 u8 match_dw_6[0x20];
6322 u8 match_dw_5[0x20];
6323 u8 match_dw_4[0x20];
6324 u8 match_dw_3[0x20];
6325 u8 match_dw_2[0x20];
6326 u8 match_dw_1[0x20];
6327 u8 match_dw_0[0x20];
6329 u8 match_byte_7[0x8];
6330 u8 match_byte_6[0x8];
6331 u8 match_byte_5[0x8];
6332 u8 match_byte_4[0x8];
6334 u8 match_byte_3[0x8];
6335 u8 match_byte_2[0x8];
6336 u8 match_byte_1[0x8];
6337 u8 match_byte_0[0x8];
6341 u8 modify_field_select[0x40];
6343 u8 reserved_at_40[0x40];
6345 u8 reserved_at_80[0x10];
6346 u8 format_id[0x10];
6348 u8 reserved_at_a0[0x60];
6350 u8 format_select_dw3[0x8];
6351 u8 format_select_dw2[0x8];
6352 u8 format_select_dw1[0x8];
6353 u8 format_select_dw0[0x8];
6355 u8 format_select_dw7[0x8];
6356 u8 format_select_dw6[0x8];
6357 u8 format_select_dw5[0x8];
6358 u8 format_select_dw4[0x8];
6360 u8 reserved_at_100[0x18];
6361 u8 format_select_dw8[0x8];
6363 u8 reserved_at_120[0x20];
6365 u8 format_select_byte3[0x8];
6366 u8 format_select_byte2[0x8];
6367 u8 format_select_byte1[0x8];
6368 u8 format_select_byte0[0x8];
6370 u8 format_select_byte7[0x8];
6371 u8 format_select_byte6[0x8];
6372 u8 format_select_byte5[0x8];
6373 u8 format_select_byte4[0x8];
6375 u8 reserved_at_180[0x40];
6379 u8 match_mask[16][0x20];
6386 u8 alias_object[0x1];
6387 u8 reserved_at_1[0x2];
6388 u8 log_obj_range[0x5];
6389 u8 reserved_at_8[0x18];
6393 u8 alias_object[0x1];
6394 u8 obj_offset[0x1f];
6398 u8 opcode[0x10];
6399 u8 uid[0x10];
6401 u8 vhca_tunnel_id[0x10];
6402 u8 obj_type[0x10];
6404 u8 obj_id[0x20];
6413 u8 status[0x8];
6414 u8 reserved_at_8[0x18];
6416 u8 syndrome[0x20];
6418 u8 obj_id[0x20];
6420 u8 reserved_at_60[0x20];
6424 u8 opcode[0x10];
6425 u8 uid[0x10];
6426 u8 reserved_at_20[0x10];
6427 u8 op_mod[0x10];
6428 u8 reserved_at_40[0x50];
6429 u8 object_type_to_be_accessed[0x10];
6430 u8 object_id_to_be_accessed[0x20];
6431 u8 reserved_at_c0[0x40];
6433 u8 access_key_raw[0x100];
6434 u8 access_key[8][0x20];
6439 u8 status[0x8];
6440 u8 reserved_at_8[0x18];
6441 u8 syndrome[0x20];
6442 u8 reserved_at_40[0x40];
6446 u8 reserved_at_0[0x80];
6448 u8 reserved_at_80[0x8];
6449 u8 access_pd[0x18];
6468 u8 vhca_id_to_be_accessed[0x10];
6469 u8 reserved_at_10[0xd];
6470 u8 status[0x3];
6471 u8 object_id_to_be_accessed[0x20];
6472 u8 reserved_at_40[0x40];
6474 u8 access_key_raw[0x100];
6475 u8 access_key[8][0x20];
6477 u8 metadata[0x80];
6486 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6487 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6488 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6489 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6490 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6491 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6492 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6496 u8 status[0x8];
6497 u8 reserved_at_8[0x18];
6499 u8 syndrome[0x20];
6501 u8 reserved_at_40[0xa0];
6503 u8 start_flow_index[0x20];
6505 u8 reserved_at_100[0x20];
6507 u8 end_flow_index[0x20];
6509 u8 reserved_at_140[0xa0];
6511 u8 reserved_at_1e0[0x18];
6512 u8 match_criteria_enable[0x8];
6516 u8 reserved_at_1200[0xe00];
6520 u8 opcode[0x10];
6521 u8 reserved_at_10[0x10];
6523 u8 reserved_at_20[0x10];
6524 u8 op_mod[0x10];
6526 u8 reserved_at_40[0x40];
6528 u8 table_type[0x8];
6529 u8 reserved_at_88[0x18];
6531 u8 reserved_at_a0[0x8];
6532 u8 table_id[0x18];
6534 u8 group_id[0x20];
6536 u8 reserved_at_e0[0x120];
6540 u8 status[0x8];
6541 u8 reserved_at_8[0x18];
6543 u8 syndrome[0x20];
6545 u8 reserved_at_40[0x40];
6551 u8 opcode[0x10];
6552 u8 reserved_at_10[0x10];
6554 u8 reserved_at_20[0x10];
6555 u8 op_mod[0x10];
6557 u8 reserved_at_40[0x80];
6559 u8 clear[0x1];
6560 u8 reserved_at_c1[0xf];
6561 u8 num_of_counters[0x10];
6563 u8 flow_counter_id[0x20];
6567 u8 status[0x8];
6568 u8 reserved_at_8[0x18];
6570 u8 syndrome[0x20];
6572 u8 reserved_at_40[0x40];
6578 u8 opcode[0x10];
6579 u8 reserved_at_10[0x10];
6581 u8 reserved_at_20[0x10];
6582 u8 op_mod[0x10];
6584 u8 other_vport[0x1];
6585 u8 reserved_at_41[0xf];
6586 u8 vport_number[0x10];
6588 u8 reserved_at_60[0x20];
6592 u8 status[0x8];
6593 u8 reserved_at_8[0x18];
6595 u8 syndrome[0x20];
6597 u8 reserved_at_40[0x40];
6601 u8 reserved_at_0[0x1b];
6602 u8 fdb_to_vport_reg_c_id[0x1];
6603 u8 vport_cvlan_insert[0x1];
6604 u8 vport_svlan_insert[0x1];
6605 u8 vport_cvlan_strip[0x1];
6606 u8 vport_svlan_strip[0x1];
6610 u8 opcode[0x10];
6611 u8 reserved_at_10[0x10];
6613 u8 reserved_at_20[0x10];
6614 u8 op_mod[0x10];
6616 u8 other_vport[0x1];
6617 u8 reserved_at_41[0xf];
6618 u8 vport_number[0x10];
6626 u8 status[0x8];
6627 u8 reserved_at_8[0x18];
6629 u8 syndrome[0x20];
6631 u8 reserved_at_40[0x40];
6635 u8 reserved_at_280[0x40];
6637 u8 event_bitmask[0x40];
6639 u8 reserved_at_300[0x580];
6641 u8 pas[][0x40];
6645 u8 opcode[0x10];
6646 u8 reserved_at_10[0x10];
6648 u8 reserved_at_20[0x10];
6649 u8 op_mod[0x10];
6651 u8 reserved_at_40[0x18];
6652 u8 eq_number[0x8];
6654 u8 reserved_at_60[0x20];
6658 u8 reformat_type[0x8];
6659 u8 reserved_at_8[0x4];
6660 u8 reformat_param_0[0x4];
6661 u8 reserved_at_10[0x6];
6662 u8 reformat_data_size[0xa];
6664 u8 reformat_param_1[0x8];
6665 u8 reserved_at_28[0x8];
6666 u8 reformat_data[2][0x8];
6668 u8 more_reformat_data[][0x8];
6672 u8 status[0x8];
6673 u8 reserved_at_8[0x18];
6675 u8 syndrome[0x20];
6677 u8 reserved_at_40[0xa0];
6683 u8 opcode[0x10];
6684 u8 reserved_at_10[0x10];
6686 u8 reserved_at_20[0x10];
6687 u8 op_mod[0x10];
6689 u8 packet_reformat_id[0x20];
6691 u8 reserved_at_60[0xa0];
6695 u8 status[0x8];
6696 u8 reserved_at_8[0x18];
6698 u8 syndrome[0x20];
6700 u8 packet_reformat_id[0x20];
6702 u8 reserved_at_60[0x20];
6706 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6707 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6708 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6712 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6713 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6714 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6715 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6716 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6717 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6718 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
6719 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
6720 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6721 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
6722 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
6723 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
6724 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
6725 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6726 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6727 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6728 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6732 u8 opcode[0x10];
6733 u8 reserved_at_10[0x10];
6735 u8 reserved_at_20[0x10];
6736 u8 op_mod[0x10];
6738 u8 reserved_at_40[0xa0];
6744 u8 status[0x8];
6745 u8 reserved_at_8[0x18];
6747 u8 syndrome[0x20];
6749 u8 reserved_at_40[0x40];
6753 u8 opcode[0x10];
6754 u8 reserved_at_10[0x10];
6756 u8 reserved_20[0x10];
6757 u8 op_mod[0x10];
6759 u8 packet_reformat_id[0x20];
6761 u8 reserved_60[0x20];
6765 u8 action_type[0x4];
6766 u8 field[0xc];
6767 u8 reserved_at_10[0x3];
6768 u8 offset[0x5];
6769 u8 reserved_at_18[0x3];
6770 u8 length[0x5];
6772 u8 data[0x20];
6776 u8 action_type[0x4];
6777 u8 field[0xc];
6778 u8 reserved_at_10[0x10];
6780 u8 data[0x20];
6784 u8 action_type[0x4];
6785 u8 src_field[0xc];
6786 u8 reserved_at_10[0x3];
6787 u8 src_offset[0x5];
6788 u8 reserved_at_18[0x3];
6789 u8 length[0x5];
6791 u8 reserved_at_20[0x4];
6792 u8 dst_field[0xc];
6793 u8 reserved_at_30[0x3];
6794 u8 dst_offset[0x5];
6795 u8 reserved_at_38[0x8];
6802 u8 reserved_at_0[0x40];
6806 MLX5_ACTION_TYPE_SET = 0x1,
6807 MLX5_ACTION_TYPE_ADD = 0x2,
6808 MLX5_ACTION_TYPE_COPY = 0x3,
6812 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
6813 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
6814 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
6815 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
6816 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
6817 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
6818 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
6819 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
6820 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
6821 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
6822 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
6823 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
6824 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
6825 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
6826 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
6827 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
6828 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
6829 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
6830 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
6831 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
6832 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
6833 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
6834 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
6835 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6836 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
6837 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
6838 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
6839 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
6840 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
6841 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
6842 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
6843 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
6844 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
6845 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
6846 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
6847 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
6848 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
6849 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
6850 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
6854 u8 status[0x8];
6855 u8 reserved_at_8[0x18];
6857 u8 syndrome[0x20];
6859 u8 modify_header_id[0x20];
6861 u8 reserved_at_60[0x20];
6865 u8 opcode[0x10];
6866 u8 reserved_at_10[0x10];
6868 u8 reserved_at_20[0x10];
6869 u8 op_mod[0x10];
6871 u8 reserved_at_40[0x20];
6873 u8 table_type[0x8];
6874 u8 reserved_at_68[0x10];
6875 u8 num_of_actions[0x8];
6881 u8 status[0x8];
6882 u8 reserved_at_8[0x18];
6884 u8 syndrome[0x20];
6886 u8 reserved_at_40[0x40];
6890 u8 opcode[0x10];
6891 u8 reserved_at_10[0x10];
6893 u8 reserved_at_20[0x10];
6894 u8 op_mod[0x10];
6896 u8 modify_header_id[0x20];
6898 u8 reserved_at_60[0x20];
6902 u8 opcode[0x10];
6903 u8 uid[0x10];
6905 u8 reserved_at_20[0x10];
6906 u8 op_mod[0x10];
6908 u8 modify_header_id[0x20];
6910 u8 reserved_at_60[0xa0];
6914 u8 status[0x8];
6915 u8 reserved_at_8[0x18];
6917 u8 syndrome[0x20];
6919 u8 reserved_at_40[0x40];
6923 u8 reserved_at_280[0x180];
6927 u8 opcode[0x10];
6928 u8 reserved_at_10[0x10];
6930 u8 reserved_at_20[0x10];
6931 u8 op_mod[0x10];
6933 u8 reserved_at_40[0x8];
6934 u8 dctn[0x18];
6936 u8 reserved_at_60[0x20];
6940 u8 status[0x8];
6941 u8 reserved_at_8[0x18];
6943 u8 syndrome[0x20];
6945 u8 reserved_at_40[0x40];
6949 u8 reserved_at_280[0x600];
6951 u8 pas[][0x40];
6955 u8 opcode[0x10];
6956 u8 reserved_at_10[0x10];
6958 u8 reserved_at_20[0x10];
6959 u8 op_mod[0x10];
6961 u8 reserved_at_40[0x8];
6962 u8 cqn[0x18];
6964 u8 reserved_at_60[0x20];
6968 u8 status[0x8];
6969 u8 reserved_at_8[0x18];
6971 u8 syndrome[0x20];
6973 u8 reserved_at_40[0x20];
6975 u8 enable[0x1];
6976 u8 tag_enable[0x1];
6977 u8 reserved_at_62[0x1e];
6981 u8 opcode[0x10];
6982 u8 reserved_at_10[0x10];
6984 u8 reserved_at_20[0x10];
6985 u8 op_mod[0x10];
6987 u8 reserved_at_40[0x18];
6988 u8 priority[0x4];
6989 u8 cong_protocol[0x4];
6991 u8 reserved_at_60[0x20];
6995 u8 status[0x8];
6996 u8 reserved_at_8[0x18];
6998 u8 syndrome[0x20];
7000 u8 reserved_at_40[0x40];
7002 u8 rp_cur_flows[0x20];
7004 u8 sum_flows[0x20];
7006 u8 rp_cnp_ignored_high[0x20];
7008 u8 rp_cnp_ignored_low[0x20];
7010 u8 rp_cnp_handled_high[0x20];
7012 u8 rp_cnp_handled_low[0x20];
7014 u8 reserved_at_140[0x100];
7016 u8 time_stamp_high[0x20];
7018 u8 time_stamp_low[0x20];
7020 u8 accumulators_period[0x20];
7022 u8 np_ecn_marked_roce_packets_high[0x20];
7024 u8 np_ecn_marked_roce_packets_low[0x20];
7026 u8 np_cnp_sent_high[0x20];
7028 u8 np_cnp_sent_low[0x20];
7030 u8 reserved_at_320[0x560];
7034 u8 opcode[0x10];
7035 u8 reserved_at_10[0x10];
7037 u8 reserved_at_20[0x10];
7038 u8 op_mod[0x10];
7040 u8 clear[0x1];
7041 u8 reserved_at_41[0x1f];
7043 u8 reserved_at_60[0x20];
7047 u8 status[0x8];
7048 u8 reserved_at_8[0x18];
7050 u8 syndrome[0x20];
7052 u8 reserved_at_40[0x40];
7058 u8 opcode[0x10];
7059 u8 reserved_at_10[0x10];
7061 u8 reserved_at_20[0x10];
7062 u8 op_mod[0x10];
7064 u8 reserved_at_40[0x1c];
7065 u8 cong_protocol[0x4];
7067 u8 reserved_at_60[0x20];
7071 u8 status[0x8];
7072 u8 reserved_at_8[0x18];
7074 u8 syndrome[0x20];
7076 u8 reserved_at_40[0x40];
7082 u8 opcode[0x10];
7083 u8 reserved_at_10[0x10];
7085 u8 reserved_at_20[0x10];
7086 u8 op_mod[0x10];
7088 u8 reserved_at_40[0x40];
7092 u8 status[0x8];
7093 u8 reserved_at_8[0x18];
7095 u8 syndrome[0x20];
7097 u8 reserved_at_40[0x40];
7101 u8 opcode[0x10];
7102 u8 uid[0x10];
7104 u8 reserved_at_20[0x10];
7105 u8 op_mod[0x10];
7107 u8 reserved_at_40[0x8];
7108 u8 qpn[0x18];
7110 u8 reserved_at_60[0x20];
7114 u8 status[0x8];
7115 u8 reserved_at_8[0x18];
7117 u8 syndrome[0x20];
7119 u8 reserved_at_40[0x40];
7123 u8 opcode[0x10];
7124 u8 uid[0x10];
7126 u8 reserved_at_20[0x10];
7127 u8 op_mod[0x10];
7129 u8 reserved_at_40[0x8];
7130 u8 qpn[0x18];
7132 u8 reserved_at_60[0x20];
7136 u8 status[0x8];
7137 u8 reserved_at_8[0x18];
7139 u8 syndrome[0x20];
7141 u8 reserved_at_40[0x40];
7145 u8 opcode[0x10];
7146 u8 reserved_at_10[0x10];
7148 u8 reserved_at_20[0x10];
7149 u8 op_mod[0x10];
7151 u8 error[0x1];
7152 u8 reserved_at_41[0x4];
7153 u8 page_fault_type[0x3];
7154 u8 wq_number[0x18];
7156 u8 reserved_at_60[0x8];
7157 u8 token[0x18];
7161 u8 status[0x8];
7162 u8 reserved_at_8[0x18];
7164 u8 syndrome[0x20];
7166 u8 reserved_at_40[0x40];
7170 u8 opcode[0x10];
7171 u8 reserved_at_10[0x10];
7173 u8 reserved_at_20[0x10];
7174 u8 op_mod[0x10];
7176 u8 reserved_at_40[0x40];
7180 u8 status[0x8];
7181 u8 reserved_at_8[0x18];
7183 u8 syndrome[0x20];
7185 u8 reserved_at_40[0x40];
7189 u8 opcode[0x10];
7190 u8 reserved_at_10[0x10];
7192 u8 reserved_at_20[0x10];
7193 u8 op_mod[0x10];
7195 u8 other_vport[0x1];
7196 u8 reserved_at_41[0xf];
7197 u8 vport_number[0x10];
7199 u8 reserved_at_60[0x18];
7200 u8 admin_state[0x4];
7201 u8 reserved_at_7c[0x4];
7205 u8 status[0x8];
7206 u8 reserved_at_8[0x18];
7208 u8 syndrome[0x20];
7210 u8 reserved_at_40[0x40];
7214 u8 reserved_at_0[0x20];
7216 u8 reserved_at_20[0x1d];
7217 u8 lag_tx_port_affinity[0x1];
7218 u8 strict_lag_tx_port_affinity[0x1];
7219 u8 prio[0x1];
7223 u8 opcode[0x10];
7224 u8 uid[0x10];
7226 u8 reserved_at_20[0x10];
7227 u8 op_mod[0x10];
7229 u8 reserved_at_40[0x8];
7230 u8 tisn[0x18];
7232 u8 reserved_at_60[0x20];
7236 u8 reserved_at_c0[0x40];
7242 u8 reserved_at_0[0x20];
7244 u8 reserved_at_20[0x1b];
7245 u8 self_lb_en[0x1];
7246 u8 reserved_at_3c[0x1];
7247 u8 hash[0x1];
7248 u8 reserved_at_3e[0x1];
7249 u8 packet_merge[0x1];
7253 u8 status[0x8];
7254 u8 reserved_at_8[0x18];
7256 u8 syndrome[0x20];
7258 u8 reserved_at_40[0x40];
7262 u8 opcode[0x10];
7263 u8 uid[0x10];
7265 u8 reserved_at_20[0x10];
7266 u8 op_mod[0x10];
7268 u8 reserved_at_40[0x8];
7269 u8 tirn[0x18];
7271 u8 reserved_at_60[0x20];
7275 u8 reserved_at_c0[0x40];
7281 u8 status[0x8];
7282 u8 reserved_at_8[0x18];
7284 u8 syndrome[0x20];
7286 u8 reserved_at_40[0x40];
7290 u8 opcode[0x10];
7291 u8 uid[0x10];
7293 u8 reserved_at_20[0x10];
7294 u8 op_mod[0x10];
7296 u8 sq_state[0x4];
7297 u8 reserved_at_44[0x4];
7298 u8 sqn[0x18];
7300 u8 reserved_at_60[0x20];
7302 u8 modify_bitmask[0x40];
7304 u8 reserved_at_c0[0x40];
7310 u8 status[0x8];
7311 u8 reserved_at_8[0x18];
7313 u8 syndrome[0x20];
7315 u8 reserved_at_40[0x1c0];
7319 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7320 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7324 u8 opcode[0x10];
7325 u8 reserved_at_10[0x10];
7327 u8 reserved_at_20[0x10];
7328 u8 op_mod[0x10];
7330 u8 scheduling_hierarchy[0x8];
7331 u8 reserved_at_48[0x18];
7333 u8 scheduling_element_id[0x20];
7335 u8 reserved_at_80[0x20];
7337 u8 modify_bitmask[0x20];
7339 u8 reserved_at_c0[0x40];
7343 u8 reserved_at_300[0x100];
7347 u8 status[0x8];
7348 u8 reserved_at_8[0x18];
7350 u8 syndrome[0x20];
7352 u8 reserved_at_40[0x40];
7356 u8 reserved_at_0[0x20];
7358 u8 reserved_at_20[0x1f];
7359 u8 rqn_list[0x1];
7363 u8 opcode[0x10];
7364 u8 uid[0x10];
7366 u8 reserved_at_20[0x10];
7367 u8 op_mod[0x10];
7369 u8 reserved_at_40[0x8];
7370 u8 rqtn[0x18];
7372 u8 reserved_at_60[0x20];
7376 u8 reserved_at_c0[0x40];
7382 u8 status[0x8];
7383 u8 reserved_at_8[0x18];
7385 u8 syndrome[0x20];
7387 u8 reserved_at_40[0x40];
7397 u8 opcode[0x10];
7398 u8 uid[0x10];
7400 u8 reserved_at_20[0x10];
7401 u8 op_mod[0x10];
7403 u8 rq_state[0x4];
7404 u8 reserved_at_44[0x4];
7405 u8 rqn[0x18];
7407 u8 reserved_at_60[0x20];
7409 u8 modify_bitmask[0x40];
7411 u8 reserved_at_c0[0x40];
7417 u8 status[0x8];
7418 u8 reserved_at_8[0x18];
7420 u8 syndrome[0x20];
7422 u8 reserved_at_40[0x40];
7426 u8 reserved_at_0[0x20];
7428 u8 reserved_at_20[0x1f];
7429 u8 lwm[0x1];
7433 u8 opcode[0x10];
7434 u8 uid[0x10];
7436 u8 reserved_at_20[0x10];
7437 u8 op_mod[0x10];
7439 u8 rmp_state[0x4];
7440 u8 reserved_at_44[0x4];
7441 u8 rmpn[0x18];
7443 u8 reserved_at_60[0x20];
7447 u8 reserved_at_c0[0x40];
7453 u8 status[0x8];
7454 u8 reserved_at_8[0x18];
7456 u8 syndrome[0x20];
7458 u8 reserved_at_40[0x40];
7462 u8 reserved_at_0[0x12];
7463 u8 affiliation[0x1];
7464 u8 reserved_at_13[0x1];
7465 u8 disable_uc_local_lb[0x1];
7466 u8 disable_mc_local_lb[0x1];
7467 u8 node_guid[0x1];
7468 u8 port_guid[0x1];
7469 u8 min_inline[0x1];
7470 u8 mtu[0x1];
7471 u8 change_event[0x1];
7472 u8 promisc[0x1];
7473 u8 permanent_address[0x1];
7474 u8 addresses_list[0x1];
7475 u8 roce_en[0x1];
7476 u8 reserved_at_1f[0x1];
7480 u8 opcode[0x10];
7481 u8 reserved_at_10[0x10];
7483 u8 reserved_at_20[0x10];
7484 u8 op_mod[0x10];
7486 u8 other_vport[0x1];
7487 u8 reserved_at_41[0xf];
7488 u8 vport_number[0x10];
7492 u8 reserved_at_80[0x780];
7498 u8 status[0x8];
7499 u8 reserved_at_8[0x18];
7501 u8 syndrome[0x20];
7503 u8 reserved_at_40[0x40];
7507 u8 opcode[0x10];
7508 u8 reserved_at_10[0x10];
7510 u8 reserved_at_20[0x10];
7511 u8 op_mod[0x10];
7513 u8 other_vport[0x1];
7514 u8 reserved_at_41[0xb];
7515 u8 port_num[0x4];
7516 u8 vport_number[0x10];
7518 u8 reserved_at_60[0x20];
7524 u8 status[0x8];
7525 u8 reserved_at_8[0x18];
7527 u8 syndrome[0x20];
7529 u8 reserved_at_40[0x40];
7533 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
7534 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
7538 u8 opcode[0x10];
7539 u8 uid[0x10];
7541 u8 reserved_at_20[0x10];
7542 u8 op_mod[0x10];
7544 u8 reserved_at_40[0x8];
7545 u8 cqn[0x18];
7551 u8 reserved_at_280[0x60];
7553 u8 cq_umem_valid[0x1];
7554 u8 reserved_at_2e1[0x1f];
7556 u8 reserved_at_300[0x580];
7558 u8 pas[][0x40];
7562 u8 status[0x8];
7563 u8 reserved_at_8[0x18];
7565 u8 syndrome[0x20];
7567 u8 reserved_at_40[0x40];
7571 u8 opcode[0x10];
7572 u8 reserved_at_10[0x10];
7574 u8 reserved_at_20[0x10];
7575 u8 op_mod[0x10];
7577 u8 reserved_at_40[0x18];
7578 u8 priority[0x4];
7579 u8 cong_protocol[0x4];
7581 u8 enable[0x1];
7582 u8 tag_enable[0x1];
7583 u8 reserved_at_62[0x1e];
7587 u8 status[0x8];
7588 u8 reserved_at_8[0x18];
7590 u8 syndrome[0x20];
7592 u8 reserved_at_40[0x40];
7596 u8 opcode[0x10];
7597 u8 reserved_at_10[0x10];
7599 u8 reserved_at_20[0x10];
7600 u8 op_mod[0x10];
7602 u8 reserved_at_40[0x1c];
7603 u8 cong_protocol[0x4];
7607 u8 reserved_at_80[0x80];
7613 u8 status[0x8];
7614 u8 reserved_at_8[0x18];
7616 u8 syndrome[0x20];
7618 u8 output_num_entries[0x20];
7620 u8 reserved_at_60[0x20];
7622 u8 pas[][0x40];
7626 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
7627 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
7628 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
7632 u8 opcode[0x10];
7633 u8 reserved_at_10[0x10];
7635 u8 reserved_at_20[0x10];
7636 u8 op_mod[0x10];
7638 u8 embedded_cpu_function[0x1];
7639 u8 reserved_at_41[0xf];
7640 u8 function_id[0x10];
7642 u8 input_num_entries[0x20];
7644 u8 pas[][0x40];
7648 u8 status[0x8];
7649 u8 reserved_at_8[0x18];
7651 u8 syndrome[0x20];
7653 u8 reserved_at_40[0x40];
7655 u8 response_mad_packet[256][0x8];
7659 u8 opcode[0x10];
7660 u8 reserved_at_10[0x10];
7662 u8 reserved_at_20[0x10];
7663 u8 op_mod[0x10];
7665 u8 remote_lid[0x10];
7666 u8 reserved_at_50[0x8];
7667 u8 port[0x8];
7669 u8 reserved_at_60[0x20];
7671 u8 mad[256][0x8];
7675 u8 status[0x8];
7676 u8 reserved_at_8[0x18];
7678 u8 syndrome[0x20];
7680 u8 reserved_at_40[0x40];
7684 u8 opcode[0x10];
7685 u8 reserved_at_10[0x10];
7687 u8 reserved_at_20[0x10];
7688 u8 op_mod[0x10];
7690 u8 reserved_at_40[0x20];
7692 u8 reserved_at_60[0x2];
7693 u8 sw_vhca_id[0xe];
7694 u8 reserved_at_70[0x10];
7696 u8 sw_owner_id[4][0x20];
7700 u8 status[0x8];
7701 u8 reserved_at_8[0x18];
7703 u8 syndrome[0x20];
7705 u8 reserved_at_40[0x20];
7706 u8 ece[0x20];
7710 u8 opcode[0x10];
7711 u8 uid[0x10];
7713 u8 reserved_at_20[0x10];
7714 u8 op_mod[0x10];
7716 u8 reserved_at_40[0x8];
7717 u8 qpn[0x18];
7719 u8 reserved_at_60[0x20];
7721 u8 opt_param_mask[0x20];
7723 u8 ece[0x20];
7727 u8 reserved_at_800[0x80];
7731 u8 status[0x8];
7732 u8 reserved_at_8[0x18];
7734 u8 syndrome[0x20];
7736 u8 reserved_at_40[0x20];
7737 u8 ece[0x20];
7741 u8 opcode[0x10];
7742 u8 uid[0x10];
7744 u8 reserved_at_20[0x10];
7745 u8 op_mod[0x10];
7747 u8 reserved_at_40[0x8];
7748 u8 qpn[0x18];
7750 u8 reserved_at_60[0x20];
7752 u8 opt_param_mask[0x20];
7754 u8 ece[0x20];
7758 u8 reserved_at_800[0x80];
7762 u8 status[0x8];
7763 u8 reserved_at_8[0x18];
7765 u8 syndrome[0x20];
7767 u8 reserved_at_40[0x40];
7769 u8 packet_headers_log[128][0x8];
7771 u8 packet_syndrome[64][0x8];
7775 u8 opcode[0x10];
7776 u8 reserved_at_10[0x10];
7778 u8 reserved_at_20[0x10];
7779 u8 op_mod[0x10];
7781 u8 reserved_at_40[0x40];
7785 u8 opcode[0x10];
7786 u8 reserved_at_10[0x10];
7788 u8 reserved_at_20[0x10];
7789 u8 op_mod[0x10];
7791 u8 reserved_at_40[0x18];
7792 u8 eq_number[0x8];
7794 u8 reserved_at_60[0x20];
7796 u8 eqe[64][0x8];
7800 u8 status[0x8];
7801 u8 reserved_at_8[0x18];
7803 u8 syndrome[0x20];
7805 u8 reserved_at_40[0x40];
7809 u8 status[0x8];
7810 u8 reserved_at_8[0x18];
7812 u8 syndrome[0x20];
7814 u8 reserved_at_40[0x20];
7818 u8 opcode[0x10];
7819 u8 reserved_at_10[0x10];
7821 u8 reserved_at_20[0x10];
7822 u8 op_mod[0x10];
7824 u8 embedded_cpu_function[0x1];
7825 u8 reserved_at_41[0xf];
7826 u8 function_id[0x10];
7828 u8 reserved_at_60[0x20];
7832 u8 status[0x8];
7833 u8 reserved_at_8[0x18];
7835 u8 syndrome[0x20];
7837 u8 reserved_at_40[0x40];
7841 u8 opcode[0x10];
7842 u8 uid[0x10];
7844 u8 reserved_at_20[0x10];
7845 u8 op_mod[0x10];
7847 u8 reserved_at_40[0x8];
7848 u8 dctn[0x18];
7850 u8 reserved_at_60[0x20];
7854 u8 status[0x8];
7855 u8 reserved_at_8[0x18];
7857 u8 syndrome[0x20];
7859 u8 reserved_at_40[0x20];
7863 u8 opcode[0x10];
7864 u8 reserved_at_10[0x10];
7866 u8 reserved_at_20[0x10];
7867 u8 op_mod[0x10];
7869 u8 embedded_cpu_function[0x1];
7870 u8 reserved_at_41[0xf];
7871 u8 function_id[0x10];
7873 u8 reserved_at_60[0x20];
7877 u8 status[0x8];
7878 u8 reserved_at_8[0x18];
7880 u8 syndrome[0x20];
7882 u8 reserved_at_40[0x40];
7886 u8 opcode[0x10];
7887 u8 uid[0x10];
7889 u8 reserved_at_20[0x10];
7890 u8 op_mod[0x10];
7892 u8 reserved_at_40[0x8];
7893 u8 qpn[0x18];
7895 u8 reserved_at_60[0x20];
7897 u8 multicast_gid[16][0x8];
7901 u8 status[0x8];
7902 u8 reserved_at_8[0x18];
7904 u8 syndrome[0x20];
7906 u8 reserved_at_40[0x40];
7910 u8 opcode[0x10];
7911 u8 uid[0x10];
7913 u8 reserved_at_20[0x10];
7914 u8 op_mod[0x10];
7916 u8 reserved_at_40[0x8];
7917 u8 xrqn[0x18];
7919 u8 reserved_at_60[0x20];
7923 u8 status[0x8];
7924 u8 reserved_at_8[0x18];
7926 u8 syndrome[0x20];
7928 u8 reserved_at_40[0x40];
7932 u8 opcode[0x10];
7933 u8 uid[0x10];
7935 u8 reserved_at_20[0x10];
7936 u8 op_mod[0x10];
7938 u8 reserved_at_40[0x8];
7939 u8 xrc_srqn[0x18];
7941 u8 reserved_at_60[0x20];
7945 u8 status[0x8];
7946 u8 reserved_at_8[0x18];
7948 u8 syndrome[0x20];
7950 u8 reserved_at_40[0x40];
7954 u8 opcode[0x10];
7955 u8 uid[0x10];
7957 u8 reserved_at_20[0x10];
7958 u8 op_mod[0x10];
7960 u8 reserved_at_40[0x8];
7961 u8 tisn[0x18];
7963 u8 reserved_at_60[0x20];
7967 u8 status[0x8];
7968 u8 reserved_at_8[0x18];
7970 u8 syndrome[0x20];
7972 u8 reserved_at_40[0x40];
7976 u8 opcode[0x10];
7977 u8 uid[0x10];
7979 u8 reserved_at_20[0x10];
7980 u8 op_mod[0x10];
7982 u8 reserved_at_40[0x8];
7983 u8 tirn[0x18];
7985 u8 reserved_at_60[0x20];
7989 u8 status[0x8];
7990 u8 reserved_at_8[0x18];
7992 u8 syndrome[0x20];
7994 u8 reserved_at_40[0x40];
7998 u8 opcode[0x10];
7999 u8 uid[0x10];
8001 u8 reserved_at_20[0x10];
8002 u8 op_mod[0x10];
8004 u8 reserved_at_40[0x8];
8005 u8 srqn[0x18];
8007 u8 reserved_at_60[0x20];
8011 u8 status[0x8];
8012 u8 reserved_at_8[0x18];
8014 u8 syndrome[0x20];
8016 u8 reserved_at_40[0x40];
8020 u8 opcode[0x10];
8021 u8 uid[0x10];
8023 u8 reserved_at_20[0x10];
8024 u8 op_mod[0x10];
8026 u8 reserved_at_40[0x8];
8027 u8 sqn[0x18];
8029 u8 reserved_at_60[0x20];
8033 u8 status[0x8];
8034 u8 reserved_at_8[0x18];
8036 u8 syndrome[0x20];
8038 u8 reserved_at_40[0x1c0];
8042 u8 opcode[0x10];
8043 u8 reserved_at_10[0x10];
8045 u8 reserved_at_20[0x10];
8046 u8 op_mod[0x10];
8048 u8 scheduling_hierarchy[0x8];
8049 u8 reserved_at_48[0x18];
8051 u8 scheduling_element_id[0x20];
8053 u8 reserved_at_80[0x180];
8057 u8 status[0x8];
8058 u8 reserved_at_8[0x18];
8060 u8 syndrome[0x20];
8062 u8 reserved_at_40[0x40];
8066 u8 opcode[0x10];
8067 u8 uid[0x10];
8069 u8 reserved_at_20[0x10];
8070 u8 op_mod[0x10];
8072 u8 reserved_at_40[0x8];
8073 u8 rqtn[0x18];
8075 u8 reserved_at_60[0x20];
8079 u8 status[0x8];
8080 u8 reserved_at_8[0x18];
8082 u8 syndrome[0x20];
8084 u8 reserved_at_40[0x40];
8088 u8 opcode[0x10];
8089 u8 uid[0x10];
8091 u8 reserved_at_20[0x10];
8092 u8 op_mod[0x10];
8094 u8 reserved_at_40[0x8];
8095 u8 rqn[0x18];
8097 u8 reserved_at_60[0x20];
8101 u8 opcode[0x10];
8102 u8 reserved_at_10[0x10];
8104 u8 reserved_at_20[0x10];
8105 u8 op_mod[0x10];
8107 u8 reserved_at_40[0x20];
8109 u8 reserved_at_60[0x10];
8110 u8 delay_drop_timeout[0x10];
8114 u8 status[0x8];
8115 u8 reserved_at_8[0x18];
8117 u8 syndrome[0x20];
8119 u8 reserved_at_40[0x40];
8123 u8 status[0x8];
8124 u8 reserved_at_8[0x18];
8126 u8 syndrome[0x20];
8128 u8 reserved_at_40[0x40];
8132 u8 opcode[0x10];
8133 u8 uid[0x10];
8135 u8 reserved_at_20[0x10];
8136 u8 op_mod[0x10];
8138 u8 reserved_at_40[0x8];
8139 u8 rmpn[0x18];
8141 u8 reserved_at_60[0x20];
8145 u8 status[0x8];
8146 u8 reserved_at_8[0x18];
8148 u8 syndrome[0x20];
8150 u8 reserved_at_40[0x40];
8154 u8 opcode[0x10];
8155 u8 uid[0x10];
8157 u8 reserved_at_20[0x10];
8158 u8 op_mod[0x10];
8160 u8 reserved_at_40[0x8];
8161 u8 qpn[0x18];
8163 u8 reserved_at_60[0x20];
8167 u8 status[0x8];
8168 u8 reserved_at_8[0x18];
8170 u8 syndrome[0x20];
8172 u8 reserved_at_40[0x40];
8176 u8 opcode[0x10];
8177 u8 reserved_at_10[0x10];
8179 u8 reserved_at_20[0x10];
8180 u8 op_mod[0x10];
8182 u8 reserved_at_40[0x8];
8183 u8 psvn[0x18];
8185 u8 reserved_at_60[0x20];
8189 u8 status[0x8];
8190 u8 reserved_at_8[0x18];
8192 u8 syndrome[0x20];
8194 u8 reserved_at_40[0x40];
8198 u8 opcode[0x10];
8199 u8 uid[0x10];
8201 u8 reserved_at_20[0x10];
8202 u8 op_mod[0x10];
8204 u8 reserved_at_40[0x8];
8205 u8 mkey_index[0x18];
8207 u8 reserved_at_60[0x20];
8211 u8 status[0x8];
8212 u8 reserved_at_8[0x18];
8214 u8 syndrome[0x20];
8216 u8 reserved_at_40[0x40];
8220 u8 opcode[0x10];
8221 u8 reserved_at_10[0x10];
8223 u8 reserved_at_20[0x10];
8224 u8 op_mod[0x10];
8226 u8 other_vport[0x1];
8227 u8 reserved_at_41[0xf];
8228 u8 vport_number[0x10];
8230 u8 reserved_at_60[0x20];
8232 u8 table_type[0x8];
8233 u8 reserved_at_88[0x18];
8235 u8 reserved_at_a0[0x8];
8236 u8 table_id[0x18];
8238 u8 reserved_at_c0[0x140];
8242 u8 status[0x8];
8243 u8 reserved_at_8[0x18];
8245 u8 syndrome[0x20];
8247 u8 reserved_at_40[0x40];
8251 u8 opcode[0x10];
8252 u8 reserved_at_10[0x10];
8254 u8 reserved_at_20[0x10];
8255 u8 op_mod[0x10];
8257 u8 other_vport[0x1];
8258 u8 reserved_at_41[0xf];
8259 u8 vport_number[0x10];
8261 u8 reserved_at_60[0x20];
8263 u8 table_type[0x8];
8264 u8 reserved_at_88[0x18];
8266 u8 reserved_at_a0[0x8];
8267 u8 table_id[0x18];
8269 u8 group_id[0x20];
8271 u8 reserved_at_e0[0x120];
8275 u8 status[0x8];
8276 u8 reserved_at_8[0x18];
8278 u8 syndrome[0x20];
8280 u8 reserved_at_40[0x40];
8284 u8 opcode[0x10];
8285 u8 reserved_at_10[0x10];
8287 u8 reserved_at_20[0x10];
8288 u8 op_mod[0x10];
8290 u8 reserved_at_40[0x18];
8291 u8 eq_number[0x8];
8293 u8 reserved_at_60[0x20];
8297 u8 status[0x8];
8298 u8 reserved_at_8[0x18];
8300 u8 syndrome[0x20];
8302 u8 reserved_at_40[0x40];
8306 u8 opcode[0x10];
8307 u8 uid[0x10];
8309 u8 reserved_at_20[0x10];
8310 u8 op_mod[0x10];
8312 u8 reserved_at_40[0x8];
8313 u8 dctn[0x18];
8315 u8 reserved_at_60[0x20];
8319 u8 status[0x8];
8320 u8 reserved_at_8[0x18];
8322 u8 syndrome[0x20];
8324 u8 reserved_at_40[0x40];
8328 u8 opcode[0x10];
8329 u8 uid[0x10];
8331 u8 reserved_at_20[0x10];
8332 u8 op_mod[0x10];
8334 u8 reserved_at_40[0x8];
8335 u8 cqn[0x18];
8337 u8 reserved_at_60[0x20];
8341 u8 status[0x8];
8342 u8 reserved_at_8[0x18];
8344 u8 syndrome[0x20];
8346 u8 reserved_at_40[0x40];
8350 u8 opcode[0x10];
8351 u8 reserved_at_10[0x10];
8353 u8 reserved_at_20[0x10];
8354 u8 op_mod[0x10];
8356 u8 reserved_at_40[0x20];
8358 u8 reserved_at_60[0x10];
8359 u8 vxlan_udp_port[0x10];
8363 u8 status[0x8];
8364 u8 reserved_at_8[0x18];
8366 u8 syndrome[0x20];
8368 u8 reserved_at_40[0x40];
8372 u8 opcode[0x10];
8373 u8 reserved_at_10[0x10];
8375 u8 reserved_at_20[0x10];
8376 u8 op_mod[0x10];
8378 u8 reserved_at_40[0x60];
8380 u8 reserved_at_a0[0x8];
8381 u8 table_index[0x18];
8383 u8 reserved_at_c0[0x140];
8387 u8 status[0x8];
8388 u8 reserved_at_8[0x18];
8390 u8 syndrome[0x20];
8392 u8 reserved_at_40[0x40];
8396 u8 opcode[0x10];
8397 u8 reserved_at_10[0x10];
8399 u8 reserved_at_20[0x10];
8400 u8 op_mod[0x10];
8402 u8 other_vport[0x1];
8403 u8 reserved_at_41[0xf];
8404 u8 vport_number[0x10];
8406 u8 reserved_at_60[0x20];
8408 u8 table_type[0x8];
8409 u8 reserved_at_88[0x18];
8411 u8 reserved_at_a0[0x8];
8412 u8 table_id[0x18];
8414 u8 reserved_at_c0[0x40];
8416 u8 flow_index[0x20];
8418 u8 reserved_at_120[0xe0];
8422 u8 status[0x8];
8423 u8 reserved_at_8[0x18];
8425 u8 syndrome[0x20];
8427 u8 reserved_at_40[0x40];
8431 u8 opcode[0x10];
8432 u8 uid[0x10];
8434 u8 reserved_at_20[0x10];
8435 u8 op_mod[0x10];
8437 u8 reserved_at_40[0x8];
8438 u8 xrcd[0x18];
8440 u8 reserved_at_60[0x20];
8444 u8 status[0x8];
8445 u8 reserved_at_8[0x18];
8447 u8 syndrome[0x20];
8449 u8 reserved_at_40[0x40];
8453 u8 opcode[0x10];
8454 u8 uid[0x10];
8456 u8 reserved_at_20[0x10];
8457 u8 op_mod[0x10];
8459 u8 reserved_at_40[0x8];
8460 u8 uar[0x18];
8462 u8 reserved_at_60[0x20];
8466 u8 status[0x8];
8467 u8 reserved_at_8[0x18];
8469 u8 syndrome[0x20];
8471 u8 reserved_at_40[0x40];
8475 u8 opcode[0x10];
8476 u8 uid[0x10];
8478 u8 reserved_at_20[0x10];
8479 u8 op_mod[0x10];
8481 u8 reserved_at_40[0x8];
8482 u8 transport_domain[0x18];
8484 u8 reserved_at_60[0x20];
8488 u8 status[0x8];
8489 u8 reserved_at_8[0x18];
8491 u8 syndrome[0x20];
8493 u8 reserved_at_40[0x40];
8497 u8 opcode[0x10];
8498 u8 reserved_at_10[0x10];
8500 u8 reserved_at_20[0x10];
8501 u8 op_mod[0x10];
8503 u8 reserved_at_40[0x18];
8504 u8 counter_set_id[0x8];
8506 u8 reserved_at_60[0x20];
8510 u8 status[0x8];
8511 u8 reserved_at_8[0x18];
8513 u8 syndrome[0x20];
8515 u8 reserved_at_40[0x40];
8519 u8 opcode[0x10];
8520 u8 uid[0x10];
8522 u8 reserved_at_20[0x10];
8523 u8 op_mod[0x10];
8525 u8 reserved_at_40[0x8];
8526 u8 pd[0x18];
8528 u8 reserved_at_60[0x20];
8532 u8 status[0x8];
8533 u8 reserved_at_8[0x18];
8535 u8 syndrome[0x20];
8537 u8 reserved_at_40[0x40];
8541 u8 opcode[0x10];
8542 u8 reserved_at_10[0x10];
8544 u8 reserved_at_20[0x10];
8545 u8 op_mod[0x10];
8547 u8 flow_counter_id[0x20];
8549 u8 reserved_at_60[0x20];
8553 u8 status[0x8];
8554 u8 reserved_at_8[0x18];
8556 u8 syndrome[0x20];
8558 u8 reserved_at_40[0x8];
8559 u8 xrqn[0x18];
8561 u8 reserved_at_60[0x20];
8565 u8 opcode[0x10];
8566 u8 uid[0x10];
8568 u8 reserved_at_20[0x10];
8569 u8 op_mod[0x10];
8571 u8 reserved_at_40[0x40];
8577 u8 status[0x8];
8578 u8 reserved_at_8[0x18];
8580 u8 syndrome[0x20];
8582 u8 reserved_at_40[0x8];
8583 u8 xrc_srqn[0x18];
8585 u8 reserved_at_60[0x20];
8589 u8 opcode[0x10];
8590 u8 uid[0x10];
8592 u8 reserved_at_20[0x10];
8593 u8 op_mod[0x10];
8595 u8 reserved_at_40[0x40];
8599 u8 reserved_at_280[0x60];
8601 u8 xrc_srq_umem_valid[0x1];
8602 u8 reserved_at_2e1[0x1f];
8604 u8 reserved_at_300[0x580];
8606 u8 pas[][0x40];
8610 u8 status[0x8];
8611 u8 reserved_at_8[0x18];
8613 u8 syndrome[0x20];
8615 u8 reserved_at_40[0x8];
8616 u8 tisn[0x18];
8618 u8 reserved_at_60[0x20];
8622 u8 opcode[0x10];
8623 u8 uid[0x10];
8625 u8 reserved_at_20[0x10];
8626 u8 op_mod[0x10];
8628 u8 reserved_at_40[0xc0];
8634 u8 status[0x8];
8635 u8 icm_address_63_40[0x18];
8637 u8 syndrome[0x20];
8639 u8 icm_address_39_32[0x8];
8640 u8 tirn[0x18];
8642 u8 icm_address_31_0[0x20];
8646 u8 opcode[0x10];
8647 u8 uid[0x10];
8649 u8 reserved_at_20[0x10];
8650 u8 op_mod[0x10];
8652 u8 reserved_at_40[0xc0];
8658 u8 status[0x8];
8659 u8 reserved_at_8[0x18];
8661 u8 syndrome[0x20];
8663 u8 reserved_at_40[0x8];
8664 u8 srqn[0x18];
8666 u8 reserved_at_60[0x20];
8670 u8 opcode[0x10];
8671 u8 uid[0x10];
8673 u8 reserved_at_20[0x10];
8674 u8 op_mod[0x10];
8676 u8 reserved_at_40[0x40];
8680 u8 reserved_at_280[0x600];
8682 u8 pas[][0x40];
8686 u8 status[0x8];
8687 u8 reserved_at_8[0x18];
8689 u8 syndrome[0x20];
8691 u8 reserved_at_40[0x8];
8692 u8 sqn[0x18];
8694 u8 reserved_at_60[0x20];
8698 u8 opcode[0x10];
8699 u8 uid[0x10];
8701 u8 reserved_at_20[0x10];
8702 u8 op_mod[0x10];
8704 u8 reserved_at_40[0xc0];
8710 u8 status[0x8];
8711 u8 reserved_at_8[0x18];
8713 u8 syndrome[0x20];
8715 u8 reserved_at_40[0x40];
8717 u8 scheduling_element_id[0x20];
8719 u8 reserved_at_a0[0x160];
8723 u8 opcode[0x10];
8724 u8 reserved_at_10[0x10];
8726 u8 reserved_at_20[0x10];
8727 u8 op_mod[0x10];
8729 u8 scheduling_hierarchy[0x8];
8730 u8 reserved_at_48[0x18];
8732 u8 reserved_at_60[0xa0];
8736 u8 reserved_at_300[0x100];
8740 u8 status[0x8];
8741 u8 reserved_at_8[0x18];
8743 u8 syndrome[0x20];
8745 u8 reserved_at_40[0x8];
8746 u8 rqtn[0x18];
8748 u8 reserved_at_60[0x20];
8752 u8 opcode[0x10];
8753 u8 uid[0x10];
8755 u8 reserved_at_20[0x10];
8756 u8 op_mod[0x10];
8758 u8 reserved_at_40[0xc0];
8764 u8 status[0x8];
8765 u8 reserved_at_8[0x18];
8767 u8 syndrome[0x20];
8769 u8 reserved_at_40[0x8];
8770 u8 rqn[0x18];
8772 u8 reserved_at_60[0x20];
8776 u8 opcode[0x10];
8777 u8 uid[0x10];
8779 u8 reserved_at_20[0x10];
8780 u8 op_mod[0x10];
8782 u8 reserved_at_40[0xc0];
8788 u8 status[0x8];
8789 u8 reserved_at_8[0x18];
8791 u8 syndrome[0x20];
8793 u8 reserved_at_40[0x8];
8794 u8 rmpn[0x18];
8796 u8 reserved_at_60[0x20];
8800 u8 opcode[0x10];
8801 u8 uid[0x10];
8803 u8 reserved_at_20[0x10];
8804 u8 op_mod[0x10];
8806 u8 reserved_at_40[0xc0];
8812 u8 status[0x8];
8813 u8 reserved_at_8[0x18];
8815 u8 syndrome[0x20];
8817 u8 reserved_at_40[0x8];
8818 u8 qpn[0x18];
8820 u8 ece[0x20];
8824 u8 opcode[0x10];
8825 u8 uid[0x10];
8827 u8 reserved_at_20[0x10];
8828 u8 op_mod[0x10];
8830 u8 qpc_ext[0x1];
8831 u8 reserved_at_41[0x7];
8832 u8 input_qpn[0x18];
8834 u8 reserved_at_60[0x20];
8835 u8 opt_param_mask[0x20];
8837 u8 ece[0x20];
8841 u8 reserved_at_800[0x60];
8843 u8 wq_umem_valid[0x1];
8844 u8 reserved_at_861[0x1f];
8846 u8 pas[][0x40];
8850 u8 status[0x8];
8851 u8 reserved_at_8[0x18];
8853 u8 syndrome[0x20];
8855 u8 reserved_at_40[0x40];
8857 u8 reserved_at_80[0x8];
8858 u8 psv0_index[0x18];
8860 u8 reserved_at_a0[0x8];
8861 u8 psv1_index[0x18];
8863 u8 reserved_at_c0[0x8];
8864 u8 psv2_index[0x18];
8866 u8 reserved_at_e0[0x8];
8867 u8 psv3_index[0x18];
8871 u8 opcode[0x10];
8872 u8 reserved_at_10[0x10];
8874 u8 reserved_at_20[0x10];
8875 u8 op_mod[0x10];
8877 u8 num_psv[0x4];
8878 u8 reserved_at_44[0x4];
8879 u8 pd[0x18];
8881 u8 reserved_at_60[0x20];
8885 u8 status[0x8];
8886 u8 reserved_at_8[0x18];
8888 u8 syndrome[0x20];
8890 u8 reserved_at_40[0x8];
8891 u8 mkey_index[0x18];
8893 u8 reserved_at_60[0x20];
8897 u8 opcode[0x10];
8898 u8 uid[0x10];
8900 u8 reserved_at_20[0x10];
8901 u8 op_mod[0x10];
8903 u8 reserved_at_40[0x20];
8905 u8 pg_access[0x1];
8906 u8 mkey_umem_valid[0x1];
8907 u8 reserved_at_62[0x1e];
8911 u8 reserved_at_280[0x80];
8913 u8 translations_octword_actual_size[0x20];
8915 u8 reserved_at_320[0x560];
8917 u8 klm_pas_mtt[][0x20];
8921 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
8922 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
8923 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
8924 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
8925 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
8926 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
8927 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
8931 u8 status[0x8];
8932 u8 icm_address_63_40[0x18];
8934 u8 syndrome[0x20];
8936 u8 icm_address_39_32[0x8];
8937 u8 table_id[0x18];
8939 u8 icm_address_31_0[0x20];
8943 u8 opcode[0x10];
8944 u8 uid[0x10];
8946 u8 reserved_at_20[0x10];
8947 u8 op_mod[0x10];
8949 u8 other_vport[0x1];
8950 u8 reserved_at_41[0xf];
8951 u8 vport_number[0x10];
8953 u8 reserved_at_60[0x20];
8955 u8 table_type[0x8];
8956 u8 reserved_at_88[0x18];
8958 u8 reserved_at_a0[0x20];
8964 u8 status[0x8];
8965 u8 reserved_at_8[0x18];
8967 u8 syndrome[0x20];
8969 u8 reserved_at_40[0x8];
8970 u8 group_id[0x18];
8972 u8 reserved_at_60[0x20];
8976 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0,
8977 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1,
8981 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8982 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8983 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8984 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8988 u8 opcode[0x10];
8989 u8 reserved_at_10[0x10];
8991 u8 reserved_at_20[0x10];
8992 u8 op_mod[0x10];
8994 u8 other_vport[0x1];
8995 u8 reserved_at_41[0xf];
8996 u8 vport_number[0x10];
8998 u8 reserved_at_60[0x20];
9000 u8 table_type[0x8];
9001 u8 reserved_at_88[0x4];
9002 u8 group_type[0x4];
9003 u8 reserved_at_90[0x10];
9005 u8 reserved_at_a0[0x8];
9006 u8 table_id[0x18];
9008 u8 source_eswitch_owner_vhca_id_valid[0x1];
9010 u8 reserved_at_c1[0x1f];
9012 u8 start_flow_index[0x20];
9014 u8 reserved_at_100[0x20];
9016 u8 end_flow_index[0x20];
9018 u8 reserved_at_140[0x10];
9019 u8 match_definer_id[0x10];
9021 u8 reserved_at_160[0x80];
9023 u8 reserved_at_1e0[0x18];
9024 u8 match_criteria_enable[0x8];
9028 u8 reserved_at_1200[0xe00];
9032 u8 status[0x8];
9033 u8 reserved_at_8[0x18];
9035 u8 syndrome[0x20];
9037 u8 reserved_at_40[0x18];
9038 u8 eq_number[0x8];
9040 u8 reserved_at_60[0x20];
9044 u8 opcode[0x10];
9045 u8 uid[0x10];
9047 u8 reserved_at_20[0x10];
9048 u8 op_mod[0x10];
9050 u8 reserved_at_40[0x40];
9054 u8 reserved_at_280[0x40];
9056 u8 event_bitmask[4][0x40];
9058 u8 reserved_at_3c0[0x4c0];
9060 u8 pas[][0x40];
9064 u8 status[0x8];
9065 u8 reserved_at_8[0x18];
9067 u8 syndrome[0x20];
9069 u8 reserved_at_40[0x8];
9070 u8 dctn[0x18];
9072 u8 ece[0x20];
9076 u8 opcode[0x10];
9077 u8 uid[0x10];
9079 u8 reserved_at_20[0x10];
9080 u8 op_mod[0x10];
9082 u8 reserved_at_40[0x40];
9086 u8 reserved_at_280[0x180];
9090 u8 status[0x8];
9091 u8 reserved_at_8[0x18];
9093 u8 syndrome[0x20];
9095 u8 reserved_at_40[0x8];
9096 u8 cqn[0x18];
9098 u8 reserved_at_60[0x20];
9102 u8 opcode[0x10];
9103 u8 uid[0x10];
9105 u8 reserved_at_20[0x10];
9106 u8 op_mod[0x10];
9108 u8 reserved_at_40[0x40];
9112 u8 reserved_at_280[0x60];
9114 u8 cq_umem_valid[0x1];
9115 u8 reserved_at_2e1[0x59f];
9117 u8 pas[][0x40];
9121 u8 status[0x8];
9122 u8 reserved_at_8[0x18];
9124 u8 syndrome[0x20];
9126 u8 reserved_at_40[0x4];
9127 u8 min_delay[0xc];
9128 u8 int_vector[0x10];
9130 u8 reserved_at_60[0x20];
9134 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
9135 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
9139 u8 opcode[0x10];
9140 u8 reserved_at_10[0x10];
9142 u8 reserved_at_20[0x10];
9143 u8 op_mod[0x10];
9145 u8 reserved_at_40[0x4];
9146 u8 min_delay[0xc];
9147 u8 int_vector[0x10];
9149 u8 reserved_at_60[0x20];
9153 u8 status[0x8];
9154 u8 reserved_at_8[0x18];
9156 u8 syndrome[0x20];
9158 u8 reserved_at_40[0x40];
9162 u8 opcode[0x10];
9163 u8 uid[0x10];
9165 u8 reserved_at_20[0x10];
9166 u8 op_mod[0x10];
9168 u8 reserved_at_40[0x8];
9169 u8 qpn[0x18];
9171 u8 reserved_at_60[0x20];
9173 u8 multicast_gid[16][0x8];
9177 u8 status[0x8];
9178 u8 reserved_at_8[0x18];
9180 u8 syndrome[0x20];
9182 u8 reserved_at_40[0x40];
9186 u8 opcode[0x10];
9187 u8 reserved_at_10[0x10];
9189 u8 reserved_at_20[0x10];
9190 u8 op_mod[0x10];
9192 u8 reserved_at_40[0x8];
9193 u8 xrqn[0x18];
9195 u8 reserved_at_60[0x10];
9196 u8 lwm[0x10];
9200 u8 status[0x8];
9201 u8 reserved_at_8[0x18];
9203 u8 syndrome[0x20];
9205 u8 reserved_at_40[0x40];
9209 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
9213 u8 opcode[0x10];
9214 u8 uid[0x10];
9216 u8 reserved_at_20[0x10];
9217 u8 op_mod[0x10];
9219 u8 reserved_at_40[0x8];
9220 u8 xrc_srqn[0x18];
9222 u8 reserved_at_60[0x10];
9223 u8 lwm[0x10];
9227 u8 status[0x8];
9228 u8 reserved_at_8[0x18];
9230 u8 syndrome[0x20];
9232 u8 reserved_at_40[0x40];
9236 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9237 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9241 u8 opcode[0x10];
9242 u8 uid[0x10];
9244 u8 reserved_at_20[0x10];
9245 u8 op_mod[0x10];
9247 u8 reserved_at_40[0x8];
9248 u8 srq_number[0x18];
9250 u8 reserved_at_60[0x10];
9251 u8 lwm[0x10];
9255 u8 status[0x8];
9256 u8 reserved_at_8[0x18];
9258 u8 syndrome[0x20];
9260 u8 reserved_at_40[0x40];
9264 u8 opcode[0x10];
9265 u8 reserved_at_10[0x10];
9267 u8 reserved_at_20[0x10];
9268 u8 op_mod[0x10];
9270 u8 reserved_at_40[0x8];
9271 u8 dct_number[0x18];
9273 u8 reserved_at_60[0x20];
9277 u8 status[0x8];
9278 u8 reserved_at_8[0x18];
9280 u8 syndrome[0x20];
9282 u8 reserved_at_40[0x8];
9283 u8 xrcd[0x18];
9285 u8 reserved_at_60[0x20];
9289 u8 opcode[0x10];
9290 u8 uid[0x10];
9292 u8 reserved_at_20[0x10];
9293 u8 op_mod[0x10];
9295 u8 reserved_at_40[0x40];
9299 u8 status[0x8];
9300 u8 reserved_at_8[0x18];
9302 u8 syndrome[0x20];
9304 u8 reserved_at_40[0x8];
9305 u8 uar[0x18];
9307 u8 reserved_at_60[0x20];
9311 u8 opcode[0x10];
9312 u8 uid[0x10];
9314 u8 reserved_at_20[0x10];
9315 u8 op_mod[0x10];
9317 u8 reserved_at_40[0x40];
9321 u8 status[0x8];
9322 u8 reserved_at_8[0x18];
9324 u8 syndrome[0x20];
9326 u8 reserved_at_40[0x8];
9327 u8 transport_domain[0x18];
9329 u8 reserved_at_60[0x20];
9333 u8 opcode[0x10];
9334 u8 uid[0x10];
9336 u8 reserved_at_20[0x10];
9337 u8 op_mod[0x10];
9339 u8 reserved_at_40[0x40];
9343 u8 status[0x8];
9344 u8 reserved_at_8[0x18];
9346 u8 syndrome[0x20];
9348 u8 reserved_at_40[0x18];
9349 u8 counter_set_id[0x8];
9351 u8 reserved_at_60[0x20];
9355 u8 opcode[0x10];
9356 u8 uid[0x10];
9358 u8 reserved_at_20[0x10];
9359 u8 op_mod[0x10];
9361 u8 reserved_at_40[0x40];
9365 u8 status[0x8];
9366 u8 reserved_at_8[0x18];
9368 u8 syndrome[0x20];
9370 u8 reserved_at_40[0x8];
9371 u8 pd[0x18];
9373 u8 reserved_at_60[0x20];
9377 u8 opcode[0x10];
9378 u8 uid[0x10];
9380 u8 reserved_at_20[0x10];
9381 u8 op_mod[0x10];
9383 u8 reserved_at_40[0x40];
9387 u8 status[0x8];
9388 u8 reserved_at_8[0x18];
9390 u8 syndrome[0x20];
9392 u8 flow_counter_id[0x20];
9394 u8 reserved_at_60[0x20];
9398 u8 opcode[0x10];
9399 u8 reserved_at_10[0x10];
9401 u8 reserved_at_20[0x10];
9402 u8 op_mod[0x10];
9404 u8 reserved_at_40[0x33];
9405 u8 flow_counter_bulk_log_size[0x5];
9406 u8 flow_counter_bulk[0x8];
9410 u8 status[0x8];
9411 u8 reserved_at_8[0x18];
9413 u8 syndrome[0x20];
9415 u8 reserved_at_40[0x40];
9419 u8 opcode[0x10];
9420 u8 reserved_at_10[0x10];
9422 u8 reserved_at_20[0x10];
9423 u8 op_mod[0x10];
9425 u8 reserved_at_40[0x20];
9427 u8 reserved_at_60[0x10];
9428 u8 vxlan_udp_port[0x10];
9432 u8 status[0x8];
9433 u8 reserved_at_8[0x18];
9435 u8 syndrome[0x20];
9437 u8 reserved_at_40[0x40];
9441 u8 rate_limit[0x20];
9443 u8 burst_upper_bound[0x20];
9445 u8 reserved_at_40[0x10];
9446 u8 typical_packet_size[0x10];
9448 u8 reserved_at_60[0x120];
9452 u8 opcode[0x10];
9453 u8 uid[0x10];
9455 u8 reserved_at_20[0x10];
9456 u8 op_mod[0x10];
9458 u8 reserved_at_40[0x10];
9459 u8 rate_limit_index[0x10];
9461 u8 reserved_at_60[0x20];
9467 u8 status[0x8];
9468 u8 reserved_at_8[0x18];
9470 u8 syndrome[0x20];
9472 u8 reserved_at_40[0x40];
9474 u8 register_data[][0x20];
9478 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
9479 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
9483 u8 opcode[0x10];
9484 u8 reserved_at_10[0x10];
9486 u8 reserved_at_20[0x10];
9487 u8 op_mod[0x10];
9489 u8 reserved_at_40[0x10];
9490 u8 register_id[0x10];
9492 u8 argument[0x20];
9494 u8 register_data[][0x20];
9498 u8 status[0x4];
9499 u8 version[0x4];
9500 u8 local_port[0x8];
9501 u8 pnat[0x2];
9502 u8 reserved_at_12[0x2];
9503 u8 lane[0x4];
9504 u8 reserved_at_18[0x8];
9506 u8 reserved_at_20[0x20];
9508 u8 reserved_at_40[0x7];
9509 u8 polarity[0x1];
9510 u8 ob_tap0[0x8];
9511 u8 ob_tap1[0x8];
9512 u8 ob_tap2[0x8];
9514 u8 reserved_at_60[0xc];
9515 u8 ob_preemp_mode[0x4];
9516 u8 ob_reg[0x8];
9517 u8 ob_bias[0x8];
9519 u8 reserved_at_80[0x20];
9523 u8 status[0x4];
9524 u8 version[0x4];
9525 u8 local_port[0x8];
9526 u8 pnat[0x2];
9527 u8 reserved_at_12[0x2];
9528 u8 lane[0x4];
9529 u8 reserved_at_18[0x8];
9531 u8 time_to_link_up[0x10];
9532 u8 reserved_at_30[0xc];
9533 u8 grade_lane_speed[0x4];
9535 u8 grade_version[0x8];
9536 u8 grade[0x18];
9538 u8 reserved_at_60[0x4];
9539 u8 height_grade_type[0x4];
9540 u8 height_grade[0x18];
9542 u8 height_dz[0x10];
9543 u8 height_dv[0x10];
9545 u8 reserved_at_a0[0x10];
9546 u8 height_sigma[0x10];
9548 u8 reserved_at_c0[0x20];
9550 u8 reserved_at_e0[0x4];
9551 u8 phase_grade_type[0x4];
9552 u8 phase_grade[0x18];
9554 u8 reserved_at_100[0x8];
9555 u8 phase_eo_pos[0x8];
9556 u8 reserved_at_110[0x8];
9557 u8 phase_eo_neg[0x8];
9559 u8 ffe_set_tested[0x10];
9560 u8 test_errors_per_lane[0x10];
9564 u8 reserved_at_0[0x8];
9565 u8 local_port[0x8];
9566 u8 reserved_at_10[0x10];
9568 u8 reserved_at_20[0x1c];
9569 u8 vl_hw_cap[0x4];
9571 u8 reserved_at_40[0x1c];
9572 u8 vl_admin[0x4];
9574 u8 reserved_at_60[0x1c];
9575 u8 vl_operational[0x4];
9579 u8 swid[0x8];
9580 u8 local_port[0x8];
9581 u8 reserved_at_10[0x4];
9582 u8 admin_status[0x4];
9583 u8 reserved_at_18[0x4];
9584 u8 oper_status[0x4];
9586 u8 reserved_at_20[0x60];
9590 u8 reserved_at_0[0x1];
9591 u8 an_disable_admin[0x1];
9592 u8 an_disable_cap[0x1];
9593 u8 reserved_at_3[0x5];
9594 u8 local_port[0x8];
9595 u8 reserved_at_10[0xd];
9596 u8 proto_mask[0x3];
9598 u8 an_status[0x4];
9599 u8 reserved_at_24[0xc];
9600 u8 data_rate_oper[0x10];
9602 u8 ext_eth_proto_capability[0x20];
9604 u8 eth_proto_capability[0x20];
9606 u8 ib_link_width_capability[0x10];
9607 u8 ib_proto_capability[0x10];
9609 u8 ext_eth_proto_admin[0x20];
9611 u8 eth_proto_admin[0x20];
9613 u8 ib_link_width_admin[0x10];
9614 u8 ib_proto_admin[0x10];
9616 u8 ext_eth_proto_oper[0x20];
9618 u8 eth_proto_oper[0x20];
9620 u8 ib_link_width_oper[0x10];
9621 u8 ib_proto_oper[0x10];
9623 u8 reserved_at_160[0x1c];
9624 u8 connector_type[0x4];
9626 u8 eth_proto_lp_advertise[0x20];
9628 u8 reserved_at_1a0[0x60];
9632 u8 reserved_at_0[0x8];
9633 u8 local_port[0x8];
9634 u8 reserved_at_10[0x20];
9636 u8 beacon_duration[0x10];
9637 u8 reserved_at_40[0x10];
9639 u8 beacon_remain[0x10];
9643 u8 reserved_at_0[0x20];
9645 u8 algorithm_options[0x10];
9646 u8 reserved_at_30[0x4];
9647 u8 repetitions_mode[0x4];
9648 u8 num_of_repetitions[0x8];
9650 u8 grade_version[0x8];
9651 u8 height_grade_type[0x4];
9652 u8 phase_grade_type[0x4];
9653 u8 height_grade_weight[0x8];
9654 u8 phase_grade_weight[0x8];
9656 u8 gisim_measure_bits[0x10];
9657 u8 adaptive_tap_measure_bits[0x10];
9659 u8 ber_bath_high_error_threshold[0x10];
9660 u8 ber_bath_mid_error_threshold[0x10];
9662 u8 ber_bath_low_error_threshold[0x10];
9663 u8 one_ratio_high_threshold[0x10];
9665 u8 one_ratio_high_mid_threshold[0x10];
9666 u8 one_ratio_low_mid_threshold[0x10];
9668 u8 one_ratio_low_threshold[0x10];
9669 u8 ndeo_error_threshold[0x10];
9671 u8 mixer_offset_step_size[0x10];
9672 u8 reserved_at_110[0x8];
9673 u8 mix90_phase_for_voltage_bath[0x8];
9675 u8 mixer_offset_start[0x10];
9676 u8 mixer_offset_end[0x10];
9678 u8 reserved_at_140[0x15];
9679 u8 ber_test_time[0xb];
9683 u8 swid[0x8];
9684 u8 local_port[0x8];
9685 u8 sub_port[0x8];
9686 u8 reserved_at_18[0x8];
9688 u8 reserved_at_20[0x20];
9692 u8 reserved_at_0[0x8];
9693 u8 local_port[0x8];
9694 u8 reserved_at_10[0x5];
9695 u8 prio[0x3];
9696 u8 reserved_at_18[0x6];
9697 u8 mode[0x2];
9699 u8 reserved_at_20[0x20];
9701 u8 reserved_at_40[0x10];
9702 u8 min_threshold[0x10];
9704 u8 reserved_at_60[0x10];
9705 u8 max_threshold[0x10];
9707 u8 reserved_at_80[0x10];
9708 u8 mark_probability_denominator[0x10];
9710 u8 reserved_at_a0[0x60];
9714 u8 reserved_at_0[0x8];
9715 u8 local_port[0x8];
9716 u8 reserved_at_10[0x10];
9718 u8 reserved_at_20[0x60];
9720 u8 reserved_at_80[0x1c];
9721 u8 wrps_admin[0x4];
9723 u8 reserved_at_a0[0x1c];
9724 u8 wrps_status[0x4];
9726 u8 reserved_at_c0[0x8];
9727 u8 up_threshold[0x8];
9728 u8 reserved_at_d0[0x8];
9729 u8 down_threshold[0x8];
9731 u8 reserved_at_e0[0x20];
9733 u8 reserved_at_100[0x1c];
9734 u8 srps_admin[0x4];
9736 u8 reserved_at_120[0x1c];
9737 u8 srps_status[0x4];
9739 u8 reserved_at_140[0x40];
9743 u8 reserved_at_0[0x8];
9744 u8 local_port[0x8];
9745 u8 reserved_at_10[0x10];
9747 u8 reserved_at_20[0x8];
9748 u8 lb_cap[0x8];
9749 u8 reserved_at_30[0x8];
9750 u8 lb_en[0x8];
9754 u8 reserved_at_0[0x8];
9755 u8 local_port[0x8];
9756 u8 reserved_at_10[0x10];
9758 u8 reserved_at_20[0x20];
9760 u8 port_profile_mode[0x8];
9761 u8 static_port_profile[0x8];
9762 u8 active_port_profile[0x8];
9763 u8 reserved_at_58[0x8];
9765 u8 retransmission_active[0x8];
9766 u8 fec_mode_active[0x18];
9768 u8 rs_fec_correction_bypass_cap[0x4];
9769 u8 reserved_at_84[0x8];
9770 u8 fec_override_cap_56g[0x4];
9771 u8 fec_override_cap_100g[0x4];
9772 u8 fec_override_cap_50g[0x4];
9773 u8 fec_override_cap_25g[0x4];
9774 u8 fec_override_cap_10g_40g[0x4];
9776 u8 rs_fec_correction_bypass_admin[0x4];
9777 u8 reserved_at_a4[0x8];
9778 u8 fec_override_admin_56g[0x4];
9779 u8 fec_override_admin_100g[0x4];
9780 u8 fec_override_admin_50g[0x4];
9781 u8 fec_override_admin_25g[0x4];
9782 u8 fec_override_admin_10g_40g[0x4];
9784 u8 fec_override_cap_400g_8x[0x10];
9785 u8 fec_override_cap_200g_4x[0x10];
9787 u8 fec_override_cap_100g_2x[0x10];
9788 u8 fec_override_cap_50g_1x[0x10];
9790 u8 fec_override_admin_400g_8x[0x10];
9791 u8 fec_override_admin_200g_4x[0x10];
9793 u8 fec_override_admin_100g_2x[0x10];
9794 u8 fec_override_admin_50g_1x[0x10];
9796 u8 reserved_at_140[0x140];
9800 u8 swid[0x8];
9801 u8 local_port[0x8];
9802 u8 pnat[0x2];
9803 u8 reserved_at_12[0x8];
9804 u8 grp[0x6];
9806 u8 clr[0x1];
9807 u8 reserved_at_21[0x1c];
9808 u8 prio_tc[0x3];
9814 u8 reserved_at_0[0x2];
9815 u8 depth[0x6];
9816 u8 pcie_index[0x8];
9817 u8 node[0x8];
9818 u8 reserved_at_18[0x8];
9820 u8 capability_mask[0x20];
9822 u8 reserved_at_40[0x8];
9823 u8 link_width_enabled[0x8];
9824 u8 link_speed_enabled[0x10];
9826 u8 lane0_physical_position[0x8];
9827 u8 link_width_active[0x8];
9828 u8 link_speed_active[0x10];
9830 u8 num_of_pfs[0x10];
9831 u8 num_of_vfs[0x10];
9833 u8 bdf0[0x10];
9834 u8 reserved_at_b0[0x10];
9836 u8 max_read_request_size[0x4];
9837 u8 max_payload_size[0x4];
9838 u8 reserved_at_c8[0x5];
9839 u8 pwr_status[0x3];
9840 u8 port_type[0x4];
9841 u8 reserved_at_d4[0xb];
9842 u8 lane_reversal[0x1];
9844 u8 reserved_at_e0[0x14];
9845 u8 pci_power[0xc];
9847 u8 reserved_at_100[0x20];
9849 u8 device_status[0x10];
9850 u8 port_state[0x8];
9851 u8 reserved_at_138[0x8];
9853 u8 reserved_at_140[0x10];
9854 u8 receiver_detect_result[0x10];
9856 u8 reserved_at_160[0x20];
9860 u8 reserved_at_0[0x8];
9861 u8 pcie_index[0x8];
9862 u8 reserved_at_10[0xa];
9863 u8 grp[0x6];
9865 u8 clr[0x1];
9866 u8 reserved_at_21[0x1f];
9872 u8 reserved_at_0[0x3];
9873 u8 single_mac[0x1];
9874 u8 reserved_at_4[0x4];
9875 u8 local_port[0x8];
9876 u8 mac_47_32[0x10];
9878 u8 mac_31_0[0x20];
9880 u8 reserved_at_40[0x40];
9884 u8 reserved_at_0[0x8];
9885 u8 local_port[0x8];
9886 u8 reserved_at_10[0x10];
9888 u8 max_mtu[0x10];
9889 u8 reserved_at_30[0x10];
9891 u8 admin_mtu[0x10];
9892 u8 reserved_at_50[0x10];
9894 u8 oper_mtu[0x10];
9895 u8 reserved_at_70[0x10];
9899 u8 reserved_at_0[0x8];
9900 u8 module[0x8];
9901 u8 reserved_at_10[0x10];
9903 u8 reserved_at_20[0x18];
9904 u8 attenuation_5g[0x8];
9906 u8 reserved_at_40[0x18];
9907 u8 attenuation_7g[0x8];
9909 u8 reserved_at_60[0x18];
9910 u8 attenuation_12g[0x8];
9914 u8 reserved_at_0[0x8];
9915 u8 module[0x8];
9916 u8 reserved_at_10[0xc];
9917 u8 module_status[0x4];
9919 u8 reserved_at_20[0x60];
9923 u8 module_state_updated[32][0x8];
9927 u8 reserved_at_0[0x4];
9928 u8 mlpn_status[0x4];
9929 u8 local_port[0x8];
9930 u8 reserved_at_10[0x10];
9932 u8 e[0x1];
9933 u8 reserved_at_21[0x1f];
9937 u8 rxtx[0x1];
9938 u8 reserved_at_1[0x7];
9939 u8 local_port[0x8];
9940 u8 reserved_at_10[0x8];
9941 u8 width[0x8];
9943 u8 lane0_module_mapping[0x20];
9945 u8 lane1_module_mapping[0x20];
9947 u8 lane2_module_mapping[0x20];
9949 u8 lane3_module_mapping[0x20];
9951 u8 reserved_at_a0[0x160];
9955 u8 reserved_at_0[0x8];
9956 u8 module[0x8];
9957 u8 reserved_at_10[0x4];
9958 u8 admin_status[0x4];
9959 u8 reserved_at_18[0x4];
9960 u8 oper_status[0x4];
9962 u8 ase[0x1];
9963 u8 ee[0x1];
9964 u8 reserved_at_22[0x1c];
9965 u8 e[0x2];
9967 u8 reserved_at_40[0x40];
9971 u8 reserved_at_0[0x4];
9972 u8 profile_id[0xc];
9973 u8 reserved_at_10[0x4];
9974 u8 proto_mask[0x4];
9975 u8 reserved_at_18[0x8];
9977 u8 reserved_at_20[0x10];
9978 u8 lane_speed[0x10];
9980 u8 reserved_at_40[0x17];
9981 u8 lpbf[0x1];
9982 u8 fec_mode_policy[0x8];
9984 u8 retransmission_capability[0x8];
9985 u8 fec_mode_capability[0x18];
9987 u8 retransmission_support_admin[0x8];
9988 u8 fec_mode_support_admin[0x18];
9990 u8 retransmission_request_admin[0x8];
9991 u8 fec_mode_request_admin[0x18];
9993 u8 reserved_at_c0[0x80];
9997 u8 reserved_at_0[0x8];
9998 u8 local_port[0x8];
9999 u8 reserved_at_10[0x8];
10000 u8 ib_port[0x8];
10002 u8 reserved_at_20[0x60];
10006 u8 reserved_at_0[0x8];
10007 u8 local_port[0x8];
10008 u8 reserved_at_10[0xd];
10009 u8 lbf_mode[0x3];
10011 u8 reserved_at_20[0x20];
10015 u8 reserved_at_0[0x8];
10016 u8 local_port[0x8];
10017 u8 reserved_at_10[0x10];
10019 u8 dic[0x1];
10020 u8 reserved_at_21[0x19];
10021 u8 ipg[0x4];
10022 u8 reserved_at_3e[0x2];
10026 u8 reserved_at_0[0x8];
10027 u8 local_port[0x8];
10028 u8 reserved_at_10[0x10];
10030 u8 reserved_at_20[0xe0];
10032 u8 port_filter[8][0x20];
10034 u8 port_filter_update_en[8][0x20];
10038 u8 reserved_at_0[0x8];
10039 u8 local_port[0x8];
10040 u8 reserved_at_10[0xb];
10041 u8 ppan_mask_n[0x1];
10042 u8 minor_stall_mask[0x1];
10043 u8 critical_stall_mask[0x1];
10044 u8 reserved_at_1e[0x2];
10046 u8 ppan[0x4];
10047 u8 reserved_at_24[0x4];
10048 u8 prio_mask_tx[0x8];
10049 u8 reserved_at_30[0x8];
10050 u8 prio_mask_rx[0x8];
10052 u8 pptx[0x1];
10053 u8 aptx[0x1];
10054 u8 pptx_mask_n[0x1];
10055 u8 reserved_at_43[0x5];
10056 u8 pfctx[0x8];
10057 u8 reserved_at_50[0x10];
10059 u8 pprx[0x1];
10060 u8 aprx[0x1];
10061 u8 pprx_mask_n[0x1];
10062 u8 reserved_at_63[0x5];
10063 u8 pfcrx[0x8];
10064 u8 reserved_at_70[0x10];
10066 u8 device_stall_minor_watermark[0x10];
10067 u8 device_stall_critical_watermark[0x10];
10069 u8 reserved_at_a0[0x60];
10073 u8 op[0x4];
10074 u8 reserved_at_4[0x4];
10075 u8 local_port[0x8];
10076 u8 reserved_at_10[0x10];
10078 u8 op_admin[0x8];
10079 u8 op_capability[0x8];
10080 u8 op_request[0x8];
10081 u8 op_active[0x8];
10083 u8 admin[0x40];
10085 u8 capability[0x40];
10087 u8 request[0x40];
10089 u8 active[0x40];
10091 u8 reserved_at_140[0x80];
10095 u8 reserved_at_0[0x8];
10096 u8 local_port[0x8];
10097 u8 reserved_at_10[0x10];
10099 u8 reserved_at_20[0xc];
10100 u8 error_count[0x4];
10101 u8 reserved_at_30[0x10];
10103 u8 reserved_at_40[0xc];
10104 u8 lane[0x4];
10105 u8 reserved_at_50[0x8];
10106 u8 error_type[0x8];
10110 u8 reserved_at_0[0x30];
10111 u8 field_select[0x10];
10113 u8 tx_overflow_sense[0x1];
10114 u8 mark_cqe[0x1];
10115 u8 mark_cnp[0x1];
10116 u8 reserved_at_43[0x1b];
10117 u8 tx_lossy_overflow_oper[0x2];
10119 u8 reserved_at_60[0x100];
10123 u8 sdm[0x1];
10124 u8 reserved_at_1[0x1b];
10125 u8 host_buses[0x4];
10127 u8 reserved_at_20[0x20];
10129 u8 local_port[0x8];
10130 u8 reserved_at_28[0x18];
10132 u8 reserved_at_60[0x20];
10136 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0,
10137 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1,
10141 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
10142 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
10143 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
10147 u8 reserved_at_0[0x5];
10148 u8 freq_adj_units[0x3];
10149 u8 reserved_at_8[0x3];
10150 u8 log_max_freq_adjustment[0x5];
10152 u8 reserved_at_10[0xc];
10153 u8 operation[0x4];
10155 u8 freq_adjustment[0x20];
10157 u8 reserved_at_40[0x40];
10159 u8 utc_sec[0x20];
10161 u8 reserved_at_a0[0x2];
10162 u8 utc_nsec[0x1e];
10164 u8 time_adjustment[0x20];
10168 u8 reserved_at_0[0x68];
10169 u8 fec_50G_per_lane_in_pplm[0x1];
10170 u8 reserved_at_69[0x4];
10171 u8 rx_icrc_encapsulated_counter[0x1];
10172 u8 reserved_at_6e[0x4];
10173 u8 ptys_extended_ethernet[0x1];
10174 u8 reserved_at_73[0x3];
10175 u8 pfcc_mask[0x1];
10176 u8 reserved_at_77[0x3];
10177 u8 per_lane_error_counters[0x1];
10178 u8 rx_buffer_fullness_counters[0x1];
10179 u8 ptys_connector_type[0x1];
10180 u8 reserved_at_7d[0x1];
10181 u8 ppcnt_discard_group[0x1];
10182 u8 ppcnt_statistical_group[0x1];
10186 u8 port_access_reg_cap_mask_127_to_96[0x20];
10187 u8 port_access_reg_cap_mask_95_to_64[0x20];
10189 u8 port_access_reg_cap_mask_63_to_36[0x1c];
10190 u8 pplm[0x1];
10191 u8 port_access_reg_cap_mask_34_to_32[0x3];
10193 u8 port_access_reg_cap_mask_31_to_13[0x13];
10194 u8 pbmc[0x1];
10195 u8 pptb[0x1];
10196 u8 port_access_reg_cap_mask_10_to_09[0x2];
10197 u8 ppcnt[0x1];
10198 u8 port_access_reg_cap_mask_07_to_00[0x8];
10202 u8 reserved_at_0[0x8];
10203 u8 feature_group[0x8];
10204 u8 reserved_at_10[0x8];
10205 u8 access_reg_group[0x8];
10207 u8 reserved_at_20[0x20];
10211 u8 reserved_at_0[0x80];
10214 u8 reserved_at_c0[0x80];
10218 u8 reserved_at_0[0x80];
10221 u8 reserved_at_1c0[0xc0];
10225 u8 reserved_at_0[0x50];
10226 u8 mtutc_freq_adj_units[0x1];
10227 u8 mtutc_time_adjustment_extended_range[0x1];
10228 u8 reserved_at_52[0xb];
10229 u8 mcia_32dwords[0x1];
10230 u8 out_pulse_duration_ns[0x1];
10231 u8 npps_period[0x1];
10232 u8 reserved_at_60[0xa];
10233 u8 reset_state[0x1];
10234 u8 ptpcyc2realtime_modify[0x1];
10235 u8 reserved_at_6c[0x2];
10236 u8 pci_status_and_power[0x1];
10237 u8 reserved_at_6f[0x5];
10238 u8 mark_tx_action_cnp[0x1];
10239 u8 mark_tx_action_cqe[0x1];
10240 u8 dynamic_tx_overflow[0x1];
10241 u8 reserved_at_77[0x4];
10242 u8 pcie_outbound_stalled[0x1];
10243 u8 tx_overflow_buffer_pkt[0x1];
10244 u8 mtpps_enh_out_per_adj[0x1];
10245 u8 mtpps_fs[0x1];
10246 u8 pcie_performance_group[0x1];
10250 u8 reserved_at_0[0x1c];
10251 u8 mcda[0x1];
10252 u8 mcc[0x1];
10253 u8 mcqi[0x1];
10254 u8 mcqs[0x1];
10256 u8 regs_95_to_87[0x9];
10257 u8 mpegc[0x1];
10258 u8 mtutc[0x1];
10259 u8 regs_84_to_68[0x11];
10260 u8 tracer_registers[0x4];
10262 u8 regs_63_to_46[0x12];
10263 u8 mrtc[0x1];
10264 u8 regs_44_to_41[0x4];
10265 u8 mfrl[0x1];
10266 u8 regs_39_to_32[0x8];
10268 u8 regs_31_to_10[0x16];
10269 u8 mtmp[0x1];
10270 u8 regs_8_to_0[0x9];
10274 u8 regs_127_to_96[0x20];
10276 u8 regs_95_to_64[0x20];
10278 u8 regs_63_to_32[0x20];
10280 u8 regs_31_to_0[0x20];
10284 u8 regs_127_to_99[0x1d];
10285 u8 mirc[0x1];
10286 u8 regs_97_to_96[0x2];
10288 u8 regs_95_to_87[0x09];
10289 u8 synce_registers[0x2];
10290 u8 regs_84_to_64[0x15];
10292 u8 regs_63_to_32[0x20];
10294 u8 regs_31_to_0[0x20];
10298 u8 reserved_at_0[0x8];
10299 u8 feature_group[0x8];
10300 u8 reserved_at_10[0x8];
10301 u8 access_reg_group[0x8];
10303 u8 reserved_at_20[0x20];
10309 u8 reserved_at_0[0x80];
10312 u8 reserved_at_c0[0x80];
10316 u8 reserved_at_0[0x80];
10319 u8 reserved_at_1c0[0x80];
10323 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
10324 u8 qpdpm[0x1];
10325 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
10326 u8 qdpm[0x1];
10327 u8 qpts[0x1];
10328 u8 qcap[0x1];
10329 u8 qcam_access_reg_cap_mask_0[0x1];
10333 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
10334 u8 qpts_trust_both[0x1];
10338 u8 reserved_at_0[0x8];
10339 u8 feature_group[0x8];
10340 u8 reserved_at_10[0x8];
10341 u8 access_reg_group[0x8];
10342 u8 reserved_at_20[0x20];
10346 u8 reserved_at_0[0x80];
10349 u8 reserved_at_c0[0x80];
10353 u8 reserved_at_0[0x80];
10356 u8 reserved_at_1c0[0x80];
10360 u8 reserved_at_0[0x18];
10361 u8 core_dump_type[0x8];
10363 u8 reserved_at_20[0x30];
10364 u8 vhca_id[0x10];
10366 u8 reserved_at_60[0x8];
10367 u8 qpn[0x18];
10368 u8 reserved_at_80[0x180];
10372 u8 reserved_at_0[0x8];
10373 u8 local_port[0x8];
10374 u8 reserved_at_10[0x10];
10376 u8 port_capability_mask[4][0x20];
10380 u8 swid[0x8];
10381 u8 local_port[0x8];
10382 u8 reserved_at_10[0x4];
10383 u8 admin_status[0x4];
10384 u8 reserved_at_18[0x4];
10385 u8 oper_status[0x4];
10387 u8 ase[0x1];
10388 u8 ee[0x1];
10389 u8 reserved_at_22[0x1c];
10390 u8 e[0x2];
10392 u8 reserved_at_40[0x40];
10396 u8 reserved_at_0[0x8];
10397 u8 opamp_group[0x8];
10398 u8 reserved_at_10[0xc];
10399 u8 opamp_group_type[0x4];
10401 u8 start_index[0x10];
10402 u8 reserved_at_30[0x4];
10403 u8 num_of_indices[0xc];
10405 u8 index_data[18][0x10];
10409 u8 reserved_at_0[0x8];
10410 u8 local_port[0x8];
10411 u8 reserved_at_10[0x10];
10413 u8 entropy_force_cap[0x1];
10414 u8 entropy_calc_cap[0x1];
10415 u8 entropy_gre_calc_cap[0x1];
10416 u8 reserved_at_23[0xf];
10417 u8 rx_ts_over_crc_cap[0x1];
10418 u8 reserved_at_33[0xb];
10419 u8 fcs_cap[0x1];
10420 u8 reserved_at_3f[0x1];
10422 u8 entropy_force[0x1];
10423 u8 entropy_calc[0x1];
10424 u8 entropy_gre_calc[0x1];
10425 u8 reserved_at_43[0xf];
10426 u8 rx_ts_over_crc[0x1];
10427 u8 reserved_at_53[0xb];
10428 u8 fcs_chk[0x1];
10429 u8 reserved_at_5f[0x1];
10433 u8 reserved_at_0[0x4];
10434 u8 rx_lane[0x4];
10435 u8 reserved_at_8[0x4];
10436 u8 tx_lane[0x4];
10437 u8 reserved_at_10[0x8];
10438 u8 module[0x8];
10442 u8 reserved_at_0[0x6];
10443 u8 lossy[0x1];
10444 u8 epsb[0x1];
10445 u8 reserved_at_8[0x8];
10446 u8 size[0x10];
10448 u8 xoff_threshold[0x10];
10449 u8 xon_threshold[0x10];
10453 u8 node_description[64][0x8];
10457 u8 reserved_at_0[0x18];
10458 u8 power_settings_level[0x8];
10460 u8 reserved_at_20[0x60];
10464 u8 he[0x1];
10465 u8 reserved_at_1[0x1f];
10467 u8 reserved_at_20[0x60];
10471 u8 reserved_at_0[0x20];
10473 u8 mkey[0x20];
10475 u8 addressh_63_32[0x20];
10477 u8 addressl_31_0[0x20];
10481 u8 dc_key[0x40];
10483 u8 ext[0x1];
10484 u8 reserved_at_41[0x7];
10485 u8 destination_qp_dct[0x18];
10487 u8 static_rate[0x4];
10488 u8 sl_eth_prio[0x4];
10489 u8 fl[0x1];
10490 u8 mlid[0x7];
10491 u8 rlid_udp_sport[0x10];
10493 u8 reserved_at_80[0x20];
10495 u8 rmac_47_16[0x20];
10497 u8 rmac_15_0[0x10];
10498 u8 tclass[0x8];
10499 u8 hop_limit[0x8];
10501 u8 reserved_at_e0[0x1];
10502 u8 grh[0x1];
10503 u8 reserved_at_e2[0x2];
10504 u8 src_addr_index[0x8];
10505 u8 flow_label[0x14];
10507 u8 rgid_rip[16][0x8];
10511 u8 reserved_at_0[0x10];
10512 u8 function_id[0x10];
10514 u8 num_pages[0x20];
10516 u8 reserved_at_40[0xa0];
10520 u8 reserved_at_0[0x8];
10521 u8 event_type[0x8];
10522 u8 reserved_at_10[0x8];
10523 u8 event_sub_type[0x8];
10525 u8 reserved_at_20[0xe0];
10529 u8 reserved_at_1e0[0x10];
10530 u8 signature[0x8];
10531 u8 reserved_at_1f8[0x7];
10532 u8 owner[0x1];
10536 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
10540 u8 type[0x8];
10541 u8 reserved_at_8[0x18];
10543 u8 input_length[0x20];
10545 u8 input_mailbox_pointer_63_32[0x20];
10547 u8 input_mailbox_pointer_31_9[0x17];
10548 u8 reserved_at_77[0x9];
10550 u8 command_input_inline_data[16][0x8];
10552 u8 command_output_inline_data[16][0x8];
10554 u8 output_mailbox_pointer_63_32[0x20];
10556 u8 output_mailbox_pointer_31_9[0x17];
10557 u8 reserved_at_1b7[0x9];
10559 u8 output_length[0x20];
10561 u8 token[0x8];
10562 u8 signature[0x8];
10563 u8 reserved_at_1f0[0x8];
10564 u8 status[0x7];
10565 u8 ownership[0x1];
10569 u8 status[0x8];
10570 u8 reserved_at_8[0x18];
10572 u8 syndrome[0x20];
10574 u8 command_output[0x20];
10578 u8 opcode[0x10];
10579 u8 reserved_at_10[0x10];
10581 u8 reserved_at_20[0x10];
10582 u8 op_mod[0x10];
10584 u8 command[][0x20];
10588 u8 mailbox_data[512][0x8];
10590 u8 reserved_at_1000[0x180];
10592 u8 next_pointer_63_32[0x20];
10594 u8 next_pointer_31_10[0x16];
10595 u8 reserved_at_11b6[0xa];
10597 u8 block_number[0x20];
10599 u8 reserved_at_11e0[0x8];
10600 u8 token[0x8];
10601 u8 ctrl_signature[0x8];
10602 u8 signature[0x8];
10606 u8 ptag_63_32[0x20];
10608 u8 ptag_31_8[0x18];
10609 u8 reserved_at_38[0x6];
10610 u8 wr_en[0x1];
10611 u8 rd_en[0x1];
10615 u8 status[0x8];
10616 u8 reserved_at_8[0x18];
10618 u8 syndrome[0x20];
10620 u8 reserved_at_40[0x10];
10621 u8 rol_mode[0x8];
10622 u8 wol_mode[0x8];
10624 u8 reserved_at_60[0x20];
10628 u8 opcode[0x10];
10629 u8 reserved_at_10[0x10];
10631 u8 reserved_at_20[0x10];
10632 u8 op_mod[0x10];
10634 u8 reserved_at_40[0x40];
10638 u8 status[0x8];
10639 u8 reserved_at_8[0x18];
10641 u8 syndrome[0x20];
10643 u8 reserved_at_40[0x40];
10647 u8 opcode[0x10];
10648 u8 reserved_at_10[0x10];
10650 u8 reserved_at_20[0x10];
10651 u8 op_mod[0x10];
10653 u8 rol_mode_valid[0x1];
10654 u8 wol_mode_valid[0x1];
10655 u8 reserved_at_42[0xe];
10656 u8 rol_mode[0x8];
10657 u8 wol_mode[0x8];
10659 u8 reserved_at_60[0x20];
10663 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
10664 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
10665 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
10669 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
10670 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
10671 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
10675 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
10676 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
10677 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
10678 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
10679 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
10680 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
10681 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
10682 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
10683 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
10684 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
10685 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
10686 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12,
10690 u8 fw_rev_minor[0x10];
10691 u8 fw_rev_major[0x10];
10693 u8 cmd_interface_rev[0x10];
10694 u8 fw_rev_subminor[0x10];
10696 u8 reserved_at_40[0x40];
10698 u8 cmdq_phy_addr_63_32[0x20];
10700 u8 cmdq_phy_addr_31_12[0x14];
10701 u8 reserved_at_b4[0x2];
10702 u8 nic_interface[0x2];
10703 u8 log_cmdq_size[0x4];
10704 u8 log_cmdq_stride[0x4];
10706 u8 command_doorbell_vector[0x20];
10708 u8 reserved_at_e0[0xf00];
10710 u8 initializing[0x1];
10711 u8 reserved_at_fe1[0x4];
10712 u8 nic_interface_supported[0x3];
10713 u8 embedded_cpu[0x1];
10714 u8 reserved_at_fe9[0x17];
10718 u8 no_dram_nic_offset[0x20];
10720 u8 reserved_at_1220[0x6e40];
10722 u8 reserved_at_8060[0x1f];
10723 u8 clear_int[0x1];
10725 u8 health_syndrome[0x8];
10726 u8 health_counter[0x18];
10728 u8 reserved_at_80a0[0x17fc0];
10732 u8 reserved_at_0[0xc];
10733 u8 cap_number_of_pps_pins[0x4];
10734 u8 reserved_at_10[0x4];
10735 u8 cap_max_num_of_pps_in_pins[0x4];
10736 u8 reserved_at_18[0x4];
10737 u8 cap_max_num_of_pps_out_pins[0x4];
10739 u8 reserved_at_20[0x13];
10740 u8 cap_log_min_npps_period[0x5];
10741 u8 reserved_at_38[0x3];
10742 u8 cap_log_min_out_pulse_duration_ns[0x5];
10744 u8 reserved_at_40[0x4];
10745 u8 cap_pin_3_mode[0x4];
10746 u8 reserved_at_48[0x4];
10747 u8 cap_pin_2_mode[0x4];
10748 u8 reserved_at_50[0x4];
10749 u8 cap_pin_1_mode[0x4];
10750 u8 reserved_at_58[0x4];
10751 u8 cap_pin_0_mode[0x4];
10753 u8 reserved_at_60[0x4];
10754 u8 cap_pin_7_mode[0x4];
10755 u8 reserved_at_68[0x4];
10756 u8 cap_pin_6_mode[0x4];
10757 u8 reserved_at_70[0x4];
10758 u8 cap_pin_5_mode[0x4];
10759 u8 reserved_at_78[0x4];
10760 u8 cap_pin_4_mode[0x4];
10762 u8 field_select[0x20];
10763 u8 reserved_at_a0[0x20];
10765 u8 npps_period[0x40];
10767 u8 enable[0x1];
10768 u8 reserved_at_101[0xb];
10769 u8 pattern[0x4];
10770 u8 reserved_at_110[0x4];
10771 u8 pin_mode[0x4];
10772 u8 pin[0x8];
10774 u8 reserved_at_120[0x2];
10775 u8 out_pulse_duration_ns[0x1e];
10777 u8 time_stamp[0x40];
10779 u8 out_pulse_duration[0x10];
10780 u8 out_periodic_adjustment[0x10];
10781 u8 enhanced_out_periodic_adjustment[0x20];
10783 u8 reserved_at_1c0[0x20];
10787 u8 reserved_at_0[0x18];
10788 u8 pin[0x8];
10789 u8 event_arm[0x1];
10790 u8 reserved_at_21[0x1b];
10791 u8 event_generation_mode[0x4];
10792 u8 reserved_at_40[0x40];
10796 u8 last_index_flag[0x1];
10797 u8 reserved_at_1[0x7];
10798 u8 fw_device[0x8];
10799 u8 component_index[0x10];
10801 u8 reserved_at_20[0x10];
10802 u8 identifier[0x10];
10804 u8 reserved_at_40[0x17];
10805 u8 component_status[0x5];
10806 u8 component_update_state[0x4];
10808 u8 last_update_state_changer_type[0x4];
10809 u8 last_update_state_changer_host_id[0x4];
10810 u8 reserved_at_68[0x18];
10814 u8 supported_info_bitmask[0x20];
10816 u8 component_size[0x20];
10818 u8 max_component_size[0x20];
10820 u8 log_mcda_word_size[0x4];
10821 u8 reserved_at_64[0xc];
10822 u8 mcda_max_write_size[0x10];
10824 u8 rd_en[0x1];
10825 u8 reserved_at_81[0x1];
10826 u8 match_chip_id[0x1];
10827 u8 match_psid[0x1];
10828 u8 check_user_timestamp[0x1];
10829 u8 match_base_guid_mac[0x1];
10830 u8 reserved_at_86[0x1a];
10834 u8 reserved_at_0[0x2];
10835 u8 build_time_valid[0x1];
10836 u8 user_defined_time_valid[0x1];
10837 u8 reserved_at_4[0x14];
10838 u8 version_string_length[0x8];
10840 u8 version[0x20];
10842 u8 build_time[0x40];
10844 u8 user_defined_time[0x40];
10846 u8 build_tool_version[0x20];
10848 u8 reserved_at_e0[0x20];
10850 u8 version_string[92][0x8];
10854 u8 pending_server_ac_power_cycle[0x1];
10855 u8 pending_server_dc_power_cycle[0x1];
10856 u8 pending_server_reboot[0x1];
10857 u8 pending_fw_reset[0x1];
10858 u8 auto_activate[0x1];
10859 u8 all_hosts_sync[0x1];
10860 u8 device_hw_reset[0x1];
10861 u8 reserved_at_7[0x19];
10871 u8 read_pending_component[0x1];
10872 u8 reserved_at_1[0xf];
10873 u8 component_index[0x10];
10875 u8 reserved_at_20[0x20];
10877 u8 reserved_at_40[0x1b];
10878 u8 info_type[0x5];
10880 u8 info_size[0x20];
10882 u8 offset[0x20];
10884 u8 reserved_at_a0[0x10];
10885 u8 data_size[0x10];
10891 u8 reserved_at_0[0x4];
10892 u8 time_elapsed_since_last_cmd[0xc];
10893 u8 reserved_at_10[0x8];
10894 u8 instruction[0x8];
10896 u8 reserved_at_20[0x10];
10897 u8 component_index[0x10];
10899 u8 reserved_at_40[0x8];
10900 u8 update_handle[0x18];
10902 u8 handle_owner_type[0x4];
10903 u8 handle_owner_host_id[0x4];
10904 u8 reserved_at_68[0x1];
10905 u8 control_progress[0x7];
10906 u8 error_code[0x8];
10907 u8 reserved_at_78[0x4];
10908 u8 control_state[0x4];
10910 u8 component_size[0x20];
10912 u8 reserved_at_a0[0x60];
10916 u8 reserved_at_0[0x8];
10917 u8 update_handle[0x18];
10919 u8 offset[0x20];
10921 u8 reserved_at_40[0x10];
10922 u8 size[0x10];
10924 u8 reserved_at_60[0x20];
10926 u8 data[][0x20];
10930 MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10939 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10944 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10950 u8 reserved_at_0[0x20];
10952 u8 reserved_at_20[0x2];
10953 u8 pci_sync_for_fw_update_start[0x1];
10954 u8 pci_sync_for_fw_update_resp[0x2];
10955 u8 rst_type_sel[0x3];
10956 u8 reserved_at_28[0x4];
10957 u8 reset_state[0x4];
10958 u8 reset_type[0x8];
10959 u8 reset_level[0x8];
10963 u8 reserved_at_0[0x18];
10964 u8 status_code[0x8];
10966 u8 reserved_at_20[0x20];
10970 u8 reserved_at_0[0x10];
10971 u8 monitor_opcode[0x10];
10976 u8 reserved_at_0[0x20];
10981 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10985 u8 reserved_at_0[0x10];
10986 u8 group_opcode[0x10];
10990 u8 reserved_at_40[0x20];
10992 u8 status_message[59][0x20];
10997 u8 reserved_at_0[0x7c0];
11001 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
11005 u8 reserved_at_0[0x8];
11006 u8 local_port[0x8];
11007 u8 pnat[0x2];
11008 u8 reserved_at_12[0xe];
11010 u8 reserved_at_20[0x18];
11011 u8 page_select[0x8];
11017 u8 time_synced[0x1];
11018 u8 reserved_at_1[0x1f];
11020 u8 reserved_at_20[0x20];
11022 u8 time_h[0x20];
11024 u8 time_l[0x20];
11028 u8 reserved_at_0[0x19];
11029 u8 sensor_count[0x7];
11031 u8 reserved_at_20[0x20];
11033 u8 sensor_map[0x40];
11037 u8 reserved_at_0[0x14];
11038 u8 sensor_index[0xc];
11040 u8 reserved_at_20[0x10];
11041 u8 temperature[0x10];
11043 u8 mte[0x1];
11044 u8 mtr[0x1];
11045 u8 reserved_at_42[0xe];
11046 u8 max_temperature[0x10];
11048 u8 tee[0x2];
11049 u8 reserved_at_62[0xe];
11050 u8 temp_threshold_hi[0x10];
11052 u8 reserved_at_80[0x10];
11053 u8 temp_threshold_lo[0x10];
11055 u8 reserved_at_a0[0x20];
11057 u8 sensor_name_hi[0x20];
11058 u8 sensor_name_lo[0x20];
11125 u8 reserved_at_0[0x60e0];
11130 u8 reserved_at_0[0x200];
11135 u8 reserved_at_0[0x20060];
11139 u8 status[0x8];
11140 u8 reserved_at_8[0x18];
11142 u8 syndrome[0x20];
11144 u8 reserved_at_40[0x40];
11148 u8 opcode[0x10];
11149 u8 reserved_at_10[0x10];
11151 u8 reserved_at_20[0x10];
11152 u8 op_mod[0x10];
11154 u8 other_vport[0x1];
11155 u8 reserved_at_41[0xf];
11156 u8 vport_number[0x10];
11158 u8 reserved_at_60[0x20];
11160 u8 table_type[0x8];
11161 u8 reserved_at_88[0x7];
11162 u8 table_of_other_vport[0x1];
11163 u8 table_vport_number[0x10];
11165 u8 reserved_at_a0[0x8];
11166 u8 table_id[0x18];
11168 u8 reserved_at_c0[0x8];
11169 u8 underlay_qpn[0x18];
11170 u8 table_eswitch_owner_vhca_id_valid[0x1];
11171 u8 reserved_at_e1[0xf];
11172 u8 table_eswitch_owner_vhca_id[0x10];
11173 u8 reserved_at_100[0x100];
11177 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
11182 u8 status[0x8];
11183 u8 reserved_at_8[0x18];
11185 u8 syndrome[0x20];
11187 u8 reserved_at_40[0x40];
11191 u8 opcode[0x10];
11192 u8 reserved_at_10[0x10];
11194 u8 reserved_at_20[0x10];
11195 u8 op_mod[0x10];
11197 u8 other_vport[0x1];
11198 u8 reserved_at_41[0xf];
11199 u8 vport_number[0x10];
11201 u8 reserved_at_60[0x10];
11202 u8 modify_field_select[0x10];
11204 u8 table_type[0x8];
11205 u8 reserved_at_88[0x18];
11207 u8 reserved_at_a0[0x8];
11208 u8 table_id[0x18];
11214 u8 g[0x1];
11215 u8 b[0x1];
11216 u8 r[0x1];
11217 u8 reserved_at_3[0x9];
11218 u8 group[0x4];
11219 u8 reserved_at_10[0x9];
11220 u8 bw_allocation[0x7];
11222 u8 reserved_at_20[0xc];
11223 u8 max_bw_units[0x4];
11224 u8 reserved_at_30[0x8];
11225 u8 max_bw_value[0x8];
11229 u8 reserved_at_0[0x2];
11230 u8 r[0x1];
11231 u8 reserved_at_3[0x1d];
11233 u8 reserved_at_20[0xc];
11234 u8 max_bw_units[0x4];
11235 u8 reserved_at_30[0x8];
11236 u8 max_bw_value[0x8];
11240 u8 reserved_at_0[0x8];
11241 u8 port_number[0x8];
11242 u8 reserved_at_10[0x30];
11244 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
11249 u8 e[0x1];
11250 u8 reserved_at_01[0x0b];
11251 u8 prio[0x04];
11255 u8 reserved_at_0[0x8];
11256 u8 local_port[0x8];
11257 u8 reserved_at_10[0x10];
11262 u8 reserved_at_0[0x8];
11263 u8 local_port[0x8];
11264 u8 reserved_at_10[0x2d];
11265 u8 trust_state[0x3];
11269 u8 reserved_at_0[0x2];
11270 u8 mm[0x2];
11271 u8 reserved_at_4[0x4];
11272 u8 local_port[0x8];
11273 u8 reserved_at_10[0x6];
11274 u8 cm[0x1];
11275 u8 um[0x1];
11276 u8 pm[0x8];
11278 u8 prio_x_buff[0x20];
11280 u8 pm_msb[0x8];
11281 u8 reserved_at_48[0x10];
11282 u8 ctrl_buff[0x4];
11283 u8 untagged_buff[0x4];
11287 u8 reserved_at_0[0x8];
11288 u8 feature_group[0x8];
11289 u8 reserved_at_10[0x8];
11290 u8 access_reg_group[0x8];
11292 u8 reserved_at_20[0x20];
11294 u8 sb_access_reg_cap_mask[4][0x20];
11296 u8 reserved_at_c0[0x80];
11298 u8 sb_feature_cap_mask[4][0x20];
11300 u8 reserved_at_1c0[0x40];
11302 u8 cap_total_buffer_size[0x20];
11304 u8 cap_cell_size[0x10];
11305 u8 cap_max_pg_buffers[0x8];
11306 u8 cap_num_pool_supported[0x8];
11308 u8 reserved_at_240[0x8];
11309 u8 cap_sbsr_stat_size[0x8];
11310 u8 cap_max_tclass_data[0x8];
11311 u8 cap_max_cpu_ingress_tclass_sb[0x8];
11315 u8 reserved_at_0[0x8];
11316 u8 local_port[0x8];
11317 u8 reserved_at_10[0x10];
11319 u8 xoff_timer_value[0x10];
11320 u8 xoff_refresh[0x10];
11322 u8 reserved_at_40[0x9];
11323 u8 fullness_threshold[0x7];
11324 u8 port_buffer_size[0x10];
11328 u8 reserved_at_2e0[0x80];
11332 u8 desc[0x1];
11333 u8 snap[0x1];
11334 u8 reserved_at_2[0x4];
11335 u8 dir[0x2];
11336 u8 reserved_at_8[0x14];
11337 u8 pool[0x4];
11339 u8 infi_size[0x1];
11340 u8 reserved_at_21[0x7];
11341 u8 size[0x18];
11343 u8 reserved_at_40[0x1c];
11344 u8 mode[0x4];
11346 u8 reserved_at_60[0x8];
11347 u8 buff_occupancy[0x18];
11349 u8 clr[0x1];
11350 u8 reserved_at_81[0x7];
11351 u8 max_buff_occupancy[0x18];
11353 u8 reserved_at_a0[0x8];
11354 u8 ext_buff_occupancy[0x18];
11358 u8 desc[0x1];
11359 u8 snap[0x1];
11360 u8 reserved_at_2[0x6];
11361 u8 local_port[0x8];
11362 u8 pnat[0x2];
11363 u8 pg_buff[0x6];
11364 u8 reserved_at_18[0x6];
11365 u8 dir[0x2];
11367 u8 reserved_at_20[0x1f];
11368 u8 exc[0x1];
11370 u8 reserved_at_40[0x40];
11372 u8 reserved_at_80[0x8];
11373 u8 buff_occupancy[0x18];
11375 u8 clr[0x1];
11376 u8 reserved_at_a1[0x7];
11377 u8 max_buff_occupancy[0x18];
11379 u8 reserved_at_c0[0x8];
11380 u8 min_buff[0x18];
11382 u8 infi_max[0x1];
11383 u8 reserved_at_e1[0x7];
11384 u8 max_buff[0x18];
11386 u8 reserved_at_100[0x20];
11388 u8 reserved_at_120[0x1c];
11389 u8 pool[0x4];
11393 u8 reserved_at_0[0x8];
11394 u8 port_number[0x8];
11395 u8 reserved_at_10[0xd];
11396 u8 prio[0x3];
11398 u8 reserved_at_20[0x1d];
11399 u8 tclass[0x3];
11403 u8 l[0x1];
11404 u8 reserved_at_1[0x7];
11405 u8 module[0x8];
11406 u8 reserved_at_10[0x8];
11407 u8 status[0x8];
11409 u8 i2c_device_address[0x8];
11410 u8 page_number[0x8];
11411 u8 device_address[0x10];
11413 u8 reserved_at_40[0x10];
11414 u8 size[0x10];
11416 u8 reserved_at_60[0x20];
11418 u8 dword_0[0x20];
11419 u8 dword_1[0x20];
11420 u8 dword_2[0x20];
11421 u8 dword_3[0x20];
11422 u8 dword_4[0x20];
11423 u8 dword_5[0x20];
11424 u8 dword_6[0x20];
11425 u8 dword_7[0x20];
11426 u8 dword_8[0x20];
11427 u8 dword_9[0x20];
11428 u8 dword_10[0x20];
11429 u8 dword_11[0x20];
11433 u8 dcbx_cee_cap[0x1];
11434 u8 dcbx_ieee_cap[0x1];
11435 u8 dcbx_standby_cap[0x1];
11436 u8 reserved_at_3[0x5];
11437 u8 port_number[0x8];
11438 u8 reserved_at_10[0xa];
11440 u8 reserved_at_20[0x15];
11441 u8 version_oper[0x3];
11443 u8 version_admin[0x3];
11444 u8 willing_admin[0x1];
11445 u8 reserved_at_41[0x3];
11446 u8 pfc_cap_oper[0x4];
11447 u8 reserved_at_48[0x4];
11448 u8 pfc_cap_admin[0x4];
11449 u8 reserved_at_50[0x4];
11450 u8 num_of_tc_oper[0x4];
11451 u8 reserved_at_58[0x4];
11452 u8 num_of_tc_admin[0x4];
11453 u8 remote_willing[0x1];
11456 u8 reserved_at_68[0x14];
11457 u8 remote_num_of_tc[0x4];
11458 u8 reserved_at_80[0x18];
11459 u8 error[0x8];
11460 u8 reserved_at_a0[0x160];
11464 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11470 u8 fdb_selection_mode[0x1];
11471 u8 reserved_at_1[0x14];
11472 u8 port_select_mode[0x3];
11473 u8 reserved_at_18[0x5];
11474 u8 lag_state[0x3];
11476 u8 reserved_at_20[0xc];
11477 u8 active_port[0x4];
11478 u8 reserved_at_30[0x4];
11479 u8 tx_remap_affinity_2[0x4];
11480 u8 reserved_at_38[0x4];
11481 u8 tx_remap_affinity_1[0x4];
11485 u8 status[0x8];
11486 u8 reserved_at_8[0x18];
11488 u8 syndrome[0x20];
11490 u8 reserved_at_40[0x40];
11494 u8 opcode[0x10];
11495 u8 reserved_at_10[0x10];
11497 u8 reserved_at_20[0x10];
11498 u8 op_mod[0x10];
11504 u8 status[0x8];
11505 u8 reserved_at_8[0x18];
11507 u8 syndrome[0x20];
11509 u8 reserved_at_40[0x40];
11513 u8 opcode[0x10];
11514 u8 reserved_at_10[0x10];
11516 u8 reserved_at_20[0x10];
11517 u8 op_mod[0x10];
11519 u8 reserved_at_40[0x20];
11520 u8 field_select[0x20];
11526 u8 status[0x8];
11527 u8 reserved_at_8[0x18];
11529 u8 syndrome[0x20];
11535 u8 opcode[0x10];
11536 u8 reserved_at_10[0x10];
11538 u8 reserved_at_20[0x10];
11539 u8 op_mod[0x10];
11541 u8 reserved_at_40[0x40];
11545 u8 status[0x8];
11546 u8 reserved_at_8[0x18];
11548 u8 syndrome[0x20];
11550 u8 reserved_at_40[0x40];
11554 u8 opcode[0x10];
11555 u8 reserved_at_10[0x10];
11557 u8 reserved_at_20[0x10];
11558 u8 op_mod[0x10];
11560 u8 reserved_at_40[0x40];
11564 u8 status[0x8];
11565 u8 reserved_at_8[0x18];
11567 u8 syndrome[0x20];
11569 u8 reserved_at_40[0x40];
11573 u8 opcode[0x10];
11574 u8 reserved_at_10[0x10];
11576 u8 reserved_at_20[0x10];
11577 u8 op_mod[0x10];
11579 u8 reserved_at_40[0x40];
11583 u8 status[0x8];
11584 u8 reserved_at_8[0x18];
11586 u8 syndrome[0x20];
11588 u8 reserved_at_40[0x40];
11592 u8 opcode[0x10];
11593 u8 reserved_at_10[0x10];
11595 u8 reserved_at_20[0x10];
11596 u8 op_mod[0x10];
11598 u8 reserved_at_40[0x40];
11607 u8 opcode[0x10];
11608 u8 uid[0x10];
11610 u8 reserved_at_20[0x10];
11611 u8 op_mod[0x10];
11613 u8 reserved_at_40[0x20];
11615 u8 reserved_at_60[0x18];
11616 u8 memic_operation_type[0x8];
11618 u8 memic_start_addr[0x40];
11620 u8 reserved_at_c0[0x140];
11624 u8 status[0x8];
11625 u8 reserved_at_8[0x18];
11627 u8 syndrome[0x20];
11629 u8 reserved_at_40[0x40];
11631 u8 memic_operation_addr[0x40];
11633 u8 reserved_at_c0[0x140];
11637 u8 opcode[0x10];
11638 u8 reserved_at_10[0x10];
11640 u8 reserved_at_20[0x10];
11641 u8 op_mod[0x10];
11643 u8 reserved_at_30[0x20];
11645 u8 reserved_at_40[0x18];
11646 u8 log_memic_addr_alignment[0x8];
11648 u8 range_start_addr[0x40];
11650 u8 range_size[0x20];
11652 u8 memic_size[0x20];
11656 u8 status[0x8];
11657 u8 reserved_at_8[0x18];
11659 u8 syndrome[0x20];
11661 u8 memic_start_addr[0x40];
11665 u8 opcode[0x10];
11666 u8 reserved_at_10[0x10];
11668 u8 reserved_at_20[0x10];
11669 u8 op_mod[0x10];
11671 u8 reserved_at_40[0x40];
11673 u8 memic_start_addr[0x40];
11675 u8 memic_size[0x20];
11677 u8 reserved_at_e0[0x20];
11681 u8 status[0x8];
11682 u8 reserved_at_8[0x18];
11684 u8 syndrome[0x20];
11686 u8 reserved_at_40[0x40];
11690 u8 reserved_at_0[0x80];
11692 u8 ats[0x1];
11693 u8 reserved_at_81[0x1a];
11694 u8 log_page_size[0x5];
11696 u8 page_offset[0x20];
11698 u8 num_of_mtt[0x40];
11704 u8 cap[0x20];
11706 u8 reserved_at_20[0x160];
11710 u8 modify_field_select[0x40];
11712 u8 reserved_at_40[0x18];
11713 u8 log_sw_icm_size[0x8];
11715 u8 reserved_at_60[0x20];
11717 u8 sw_icm_start_addr[0x40];
11719 u8 reserved_at_c0[0x140];
11723 u8 modify_field_select[0x40];
11725 u8 reserved_at_40[0x18];
11726 u8 geneve_option_fte_index[0x8];
11728 u8 option_class[0x10];
11729 u8 option_type[0x8];
11730 u8 reserved_at_78[0x3];
11731 u8 option_data_length[0x5];
11733 u8 reserved_at_80[0x180];
11737 u8 opcode[0x10];
11738 u8 uid[0x10];
11740 u8 reserved_at_20[0x10];
11741 u8 op_mod[0x10];
11743 u8 reserved_at_40[0x40];
11749 u8 status[0x8];
11750 u8 reserved_at_8[0x18];
11752 u8 syndrome[0x20];
11754 u8 reserved_at_40[0x8];
11755 u8 umem_id[0x18];
11757 u8 reserved_at_60[0x20];
11761 u8 opcode[0x10];
11762 u8 uid[0x10];
11764 u8 reserved_at_20[0x10];
11765 u8 op_mod[0x10];
11767 u8 reserved_at_40[0x8];
11768 u8 umem_id[0x18];
11770 u8 reserved_at_60[0x20];
11774 u8 status[0x8];
11775 u8 reserved_at_8[0x18];
11777 u8 syndrome[0x20];
11779 u8 reserved_at_40[0x40];
11783 u8 opcode[0x10];
11784 u8 reserved_at_10[0x10];
11786 u8 reserved_at_20[0x10];
11787 u8 op_mod[0x10];
11789 u8 reserved_at_40[0x40];
11795 u8 status[0x8];
11796 u8 reserved_at_8[0x18];
11798 u8 syndrome[0x20];
11800 u8 reserved_at_40[0x10];
11801 u8 uid[0x10];
11803 u8 reserved_at_60[0x20];
11807 u8 opcode[0x10];
11808 u8 reserved_at_10[0x10];
11810 u8 reserved_at_20[0x10];
11811 u8 op_mod[0x10];
11813 u8 reserved_at_40[0x10];
11814 u8 uid[0x10];
11816 u8 reserved_at_60[0x20];
11820 u8 status[0x8];
11821 u8 reserved_at_8[0x18];
11823 u8 syndrome[0x20];
11825 u8 reserved_at_40[0x40];
11839 u8 string_db_base_address[0x20];
11841 u8 reserved_at_20[0x8];
11842 u8 string_db_size[0x18];
11846 u8 trace_owner[0x1];
11847 u8 trace_to_memory[0x1];
11848 u8 reserved_at_2[0x4];
11849 u8 trc_ver[0x2];
11850 u8 reserved_at_8[0x14];
11851 u8 num_string_db[0x4];
11853 u8 first_string_trace[0x8];
11854 u8 num_string_trace[0x8];
11855 u8 reserved_at_30[0x28];
11857 u8 log_max_trace_buffer_size[0x8];
11859 u8 reserved_at_60[0x20];
11863 u8 reserved_at_280[0x180];
11867 u8 reserved_at_0[0x1c];
11868 u8 trace_mode[0x4];
11869 u8 reserved_at_20[0x18];
11870 u8 log_trace_buffer_size[0x8];
11871 u8 trace_mkey[0x20];
11872 u8 reserved_at_60[0x3a0];
11876 u8 string_db_index[0x4];
11877 u8 reserved_at_4[0x4];
11878 u8 read_size[0x18];
11879 u8 start_offset[0x20];
11884 u8 trace_status[0x2];
11885 u8 reserved_at_2[0x2];
11886 u8 arm_event[0x1];
11887 u8 reserved_at_5[0xb];
11888 u8 modify_field_select[0x10];
11889 u8 reserved_at_20[0x2b];
11890 u8 current_timestamp52_32[0x15];
11891 u8 current_timestamp31_0[0x20];
11892 u8 reserved_at_80[0x180];
11896 u8 host_number[0x8];
11897 u8 reserved_at_8[0x7];
11898 u8 host_pf_disabled[0x1];
11899 u8 host_num_of_vfs[0x10];
11901 u8 host_total_vfs[0x10];
11902 u8 host_pci_bus[0x10];
11904 u8 reserved_at_40[0x10];
11905 u8 host_pci_device[0x10];
11907 u8 reserved_at_60[0x10];
11908 u8 host_pci_function[0x10];
11910 u8 reserved_at_80[0x180];
11914 u8 opcode[0x10];
11915 u8 reserved_at_10[0x10];
11917 u8 reserved_at_20[0x10];
11918 u8 op_mod[0x10];
11920 u8 reserved_at_40[0x40];
11924 u8 status[0x8];
11925 u8 reserved_at_8[0x18];
11927 u8 syndrome[0x20];
11929 u8 reserved_at_40[0x40];
11933 u8 reserved_at_280[0x180];
11934 u8 host_sf_enable[][0x40];
11938 u8 reserved_at_0[0x10];
11939 u8 log_num_sf[0x8];
11940 u8 log_sf_bar_size[0x8];
11944 u8 status[0x8];
11945 u8 reserved_at_8[0x18];
11947 u8 syndrome[0x20];
11949 u8 reserved_at_40[0x18];
11950 u8 num_sf_partitions[0x8];
11952 u8 reserved_at_60[0x20];
11958 u8 opcode[0x10];
11959 u8 reserved_at_10[0x10];
11961 u8 reserved_at_20[0x10];
11962 u8 op_mod[0x10];
11964 u8 reserved_at_40[0x40];
11968 u8 status[0x8];
11969 u8 reserved_at_8[0x18];
11971 u8 syndrome[0x20];
11973 u8 reserved_at_40[0x40];
11977 u8 opcode[0x10];
11978 u8 reserved_at_10[0x10];
11980 u8 reserved_at_20[0x10];
11981 u8 op_mod[0x10];
11983 u8 reserved_at_40[0x10];
11984 u8 function_id[0x10];
11986 u8 reserved_at_60[0x20];
11990 u8 status[0x8];
11991 u8 reserved_at_8[0x18];
11993 u8 syndrome[0x20];
11995 u8 reserved_at_40[0x40];
11999 u8 opcode[0x10];
12000 u8 reserved_at_10[0x10];
12002 u8 reserved_at_20[0x10];
12003 u8 op_mod[0x10];
12005 u8 reserved_at_40[0x10];
12006 u8 function_id[0x10];
12008 u8 reserved_at_60[0x20];
12012 u8 reserved_at_0[0x10];
12013 u8 obj_type[0x10];
12015 u8 obj_id[0x20];
12019 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
12020 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
12021 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
12022 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
12026 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12027 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12028 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12029 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12030 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12031 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12032 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12040 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12041 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12042 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12043 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12047 MLX5_IPSEC_ASO_MODE = 0x0,
12048 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12049 MLX5_IPSEC_ASO_INC_SN = 0x2,
12053 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0,
12054 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1,
12055 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12056 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12060 u8 valid[0x1];
12061 u8 reserved_at_201[0x1];
12062 u8 mode[0x2];
12063 u8 window_sz[0x2];
12064 u8 soft_lft_arm[0x1];
12065 u8 hard_lft_arm[0x1];
12066 u8 remove_flow_enable[0x1];
12067 u8 esn_event_arm[0x1];
12068 u8 reserved_at_20a[0x16];
12070 u8 remove_flow_pkt_cnt[0x20];
12072 u8 remove_flow_soft_lft[0x20];
12074 u8 reserved_at_260[0x80];
12076 u8 mode_parameter[0x20];
12078 u8 replay_protection_window[0x100];
12082 u8 modify_field_select[0x40];
12083 u8 full_offload[0x1];
12084 u8 reserved_at_41[0x1];
12085 u8 esn_en[0x1];
12086 u8 esn_overlap[0x1];
12087 u8 reserved_at_44[0x2];
12088 u8 icv_length[0x2];
12089 u8 reserved_at_48[0x4];
12090 u8 aso_return_reg[0x4];
12091 u8 reserved_at_50[0x10];
12093 u8 esn_msb[0x20];
12095 u8 reserved_at_80[0x8];
12096 u8 dekn[0x18];
12098 u8 salt[0x20];
12100 u8 implicit_iv[0x40];
12102 u8 reserved_at_100[0x8];
12103 u8 ipsec_aso_access_pd[0x18];
12104 u8 reserved_at_120[0xe0];
12115 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12130 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12134 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0,
12135 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1,
12136 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12137 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12140 #define MLX5_MACSEC_ASO_INC_SN 0x2
12141 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12144 u8 valid[0x1];
12145 u8 reserved_at_1[0x1];
12146 u8 mode[0x2];
12147 u8 window_size[0x2];
12148 u8 soft_lifetime_arm[0x1];
12149 u8 hard_lifetime_arm[0x1];
12150 u8 remove_flow_enable[0x1];
12151 u8 epn_event_arm[0x1];
12152 u8 reserved_at_a[0x16];
12154 u8 remove_flow_packet_count[0x20];
12156 u8 remove_flow_soft_lifetime[0x20];
12158 u8 reserved_at_60[0x80];
12160 u8 mode_parameter[0x20];
12162 u8 replay_protection_window[8][0x20];
12166 u8 modify_field_select[0x40];
12168 u8 confidentiality_en[0x1];
12169 u8 reserved_at_41[0x1];
12170 u8 epn_en[0x1];
12171 u8 epn_overlap[0x1];
12172 u8 reserved_at_44[0x2];
12173 u8 confidentiality_offset[0x2];
12174 u8 reserved_at_48[0x4];
12175 u8 aso_return_reg[0x4];
12176 u8 reserved_at_50[0x10];
12178 u8 epn_msb[0x20];
12180 u8 reserved_at_80[0x8];
12181 u8 dekn[0x18];
12183 u8 reserved_at_a0[0x20];
12185 u8 sci[0x40];
12187 u8 reserved_at_100[0x8];
12188 u8 macsec_aso_access_pd[0x18];
12190 u8 reserved_at_120[0x60];
12192 u8 salt[3][0x20];
12194 u8 reserved_at_1e0[0x20];
12210 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12220 u8 gcm_iv[0x60];
12222 u8 reserved_at_60[0x20];
12224 u8 const0[0x1];
12225 u8 key_size[0x1];
12226 u8 reserved_at_82[0x2];
12227 u8 key2_invalid[0x1];
12228 u8 reserved_at_85[0x3];
12229 u8 pd[0x18];
12231 u8 key_purpose[0x5];
12232 u8 reserved_at_a5[0x13];
12233 u8 kek_id[0x8];
12235 u8 reserved_at_c0[0x40];
12237 u8 key1[0x8][0x20];
12239 u8 key2[0x8][0x20];
12241 u8 reserved_at_300[0x40];
12243 u8 const1[0x1];
12244 u8 reserved_at_341[0x1f];
12246 u8 reserved_at_360[0x20];
12248 u8 auth_tag[0x80];
12252 u8 modify_field_select[0x40];
12254 u8 state[0x8];
12255 u8 sw_wrapped[0x1];
12256 u8 reserved_at_49[0xb];
12257 u8 key_size[0x4];
12258 u8 reserved_at_58[0x4];
12259 u8 key_purpose[0x4];
12261 u8 reserved_at_60[0x8];
12262 u8 pd[0x18];
12264 u8 reserved_at_80[0x100];
12266 u8 opaque[0x40];
12268 u8 reserved_at_1c0[0x40];
12270 u8 key[8][0x80];
12272 u8 sw_wrapped_dek[8][0x80];
12274 u8 reserved_at_a00[0x600];
12288 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0,
12289 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1,
12290 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2,
12291 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3,
12295 u8 valid[0x1];
12296 u8 bucket_overflow[0x1];
12297 u8 start_color[0x2];
12298 u8 both_buckets_on_green[0x1];
12299 u8 reserved_at_5[0x1];
12300 u8 meter_mode[0x2];
12301 u8 reserved_at_8[0x18];
12303 u8 reserved_at_20[0x20];
12305 u8 reserved_at_40[0x3];
12306 u8 cbs_exponent[0x5];
12307 u8 cbs_mantissa[0x8];
12308 u8 reserved_at_50[0x3];
12309 u8 cir_exponent[0x5];
12310 u8 cir_mantissa[0x8];
12312 u8 reserved_at_60[0x20];
12314 u8 reserved_at_80[0x3];
12315 u8 ebs_exponent[0x5];
12316 u8 ebs_mantissa[0x8];
12317 u8 reserved_at_90[0x3];
12318 u8 eir_exponent[0x5];
12319 u8 eir_mantissa[0x8];
12321 u8 reserved_at_a0[0x60];
12325 u8 modify_field_select[0x40];
12327 u8 reserved_at_40[0x40];
12329 u8 reserved_at_80[0x8];
12330 u8 meter_aso_access_pd[0x18];
12332 u8 reserved_at_a0[0x160];
12343 u8 modify_field_select[0x40];
12345 u8 state[0x8];
12346 u8 auto_gen[0x1];
12347 u8 reserved_at_49[0xb];
12348 u8 key_size[0x4];
12349 u8 reserved_at_58[0x8];
12351 u8 reserved_at_60[0x8];
12352 u8 pd[0x18];
12354 u8 reserved_at_80[0x180];
12355 u8 key[8][0x80];
12357 u8 reserved_at_600[0x200];
12371 u8 modify_field_select[0x40];
12373 u8 table_type[0x8];
12374 u8 level[0x8];
12375 u8 reserved_at_50[0xf];
12376 u8 ignore_flow_level[0x1];
12378 u8 sample_ratio[0x20];
12380 u8 reserved_at_80[0x8];
12381 u8 sample_table_id[0x18];
12383 u8 reserved_at_a0[0x8];
12384 u8 default_table_id[0x18];
12386 u8 sw_steering_icm_address_rx[0x40];
12387 u8 sw_steering_icm_address_tx[0x40];
12389 u8 reserved_at_140[0xa0];
12403 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12404 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12408 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12409 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12410 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12414 u8 const_2[0x2];
12415 u8 tls_version[0x4];
12416 u8 const_1[0x2];
12417 u8 reserved_at_8[0x14];
12418 u8 encryption_standard[0x4];
12420 u8 reserved_at_20[0x20];
12422 u8 initial_record_number[0x40];
12424 u8 resync_tcp_sn[0x20];
12426 u8 gcm_iv[0x20];
12428 u8 implicit_iv[0x40];
12430 u8 reserved_at_100[0x8];
12431 u8 dek_index[0x18];
12433 u8 reserved_at_120[0xe0];
12437 u8 next_record_tcp_sn[0x20];
12439 u8 hw_resync_tcp_sn[0x20];
12441 u8 record_tracker_state[0x2];
12442 u8 auth_state[0x2];
12443 u8 reserved_at_44[0x4];
12444 u8 hw_offset_record_number[0x18];
12448 MLX5_MTT_PERM_READ = 1 << 0,
12454 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0,
12455 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1,
12459 u8 opcode[0x10];
12460 u8 uid[0x10];
12462 u8 reserved_at_20[0x10];
12463 u8 op_mod[0x10];
12465 u8 reserved_at_40[0x10];
12466 u8 vhca_id[0x10];
12468 u8 reserved_at_60[0x20];
12472 u8 status[0x8];
12473 u8 reserved_at_8[0x18];
12475 u8 syndrome[0x20];
12477 u8 reserved_at_40[0x40];
12481 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0,
12482 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1,
12486 u8 opcode[0x10];
12487 u8 uid[0x10];
12489 u8 reserved_at_20[0x10];
12490 u8 op_mod[0x10];
12492 u8 reserved_at_40[0x10];
12493 u8 vhca_id[0x10];
12495 u8 reserved_at_60[0x20];
12499 u8 status[0x8];
12500 u8 reserved_at_8[0x18];
12502 u8 syndrome[0x20];
12504 u8 reserved_at_40[0x40];
12508 u8 opcode[0x10];
12509 u8 uid[0x10];
12511 u8 reserved_at_20[0x10];
12512 u8 op_mod[0x10];
12514 u8 incremental[0x1];
12515 u8 chunk[0x1];
12516 u8 reserved_at_42[0xe];
12517 u8 vhca_id[0x10];
12519 u8 reserved_at_60[0x20];
12523 u8 status[0x8];
12524 u8 reserved_at_8[0x18];
12526 u8 syndrome[0x20];
12528 u8 reserved_at_40[0x40];
12530 u8 required_umem_size[0x20];
12532 u8 reserved_at_a0[0x20];
12534 u8 remaining_total_size[0x40];
12536 u8 reserved_at_100[0x100];
12540 u8 opcode[0x10];
12541 u8 uid[0x10];
12543 u8 reserved_at_20[0x10];
12544 u8 op_mod[0x10];
12546 u8 incremental[0x1];
12547 u8 set_track[0x1];
12548 u8 reserved_at_42[0xe];
12549 u8 vhca_id[0x10];
12551 u8 reserved_at_60[0x20];
12553 u8 va[0x40];
12555 u8 mkey[0x20];
12557 u8 size[0x20];
12561 u8 status[0x8];
12562 u8 reserved_at_8[0x18];
12564 u8 syndrome[0x20];
12566 u8 actual_image_size[0x20];
12568 u8 next_required_umem_size[0x20];
12572 u8 opcode[0x10];
12573 u8 uid[0x10];
12575 u8 reserved_at_20[0x10];
12576 u8 op_mod[0x10];
12578 u8 reserved_at_40[0x10];
12579 u8 vhca_id[0x10];
12581 u8 reserved_at_60[0x20];
12583 u8 va[0x40];
12585 u8 mkey[0x20];
12587 u8 size[0x20];
12591 u8 status[0x8];
12592 u8 reserved_at_8[0x18];
12594 u8 syndrome[0x20];
12596 u8 reserved_at_40[0x40];
12600 u8 reserved_at_0[0x3];
12601 u8 pg_track_log_max_num[0x5];
12602 u8 pg_track_max_num_range[0x8];
12603 u8 pg_track_log_min_addr_space[0x8];
12604 u8 pg_track_log_max_addr_space[0x8];
12606 u8 reserved_at_20[0x3];
12607 u8 pg_track_log_min_msg_size[0x5];
12608 u8 reserved_at_28[0x3];
12609 u8 pg_track_log_max_msg_size[0x5];
12610 u8 reserved_at_30[0x3];
12611 u8 pg_track_log_min_page_size[0x5];
12612 u8 reserved_at_38[0x3];
12613 u8 pg_track_log_max_page_size[0x5];
12615 u8 reserved_at_40[0x7c0];
12619 u8 dirty_address_high[0x20];
12621 u8 dirty_address_low[0x20];
12631 u8 start_address[0x40];
12633 u8 length[0x40];
12637 u8 modify_field_select[0x40];
12639 u8 reserved_at_40[0x10];
12640 u8 vhca_id[0x10];
12642 u8 reserved_at_60[0x20];
12644 u8 state[0x4];
12645 u8 track_type[0x4];
12646 u8 log_addr_space_size[0x8];
12647 u8 reserved_at_90[0x3];
12648 u8 log_page_size[0x5];
12649 u8 reserved_at_98[0x3];
12650 u8 log_msg_size[0x5];
12652 u8 reserved_at_a0[0x8];
12653 u8 reporting_qpn[0x18];
12655 u8 reserved_at_c0[0x18];
12656 u8 num_ranges[0x8];
12658 u8 reserved_at_e0[0x20];
12660 u8 range_start_address[0x40];
12662 u8 length[0x40];
12664 struct mlx5_ifc_page_track_range_bits track_range[0];
12678 u8 reserved_at_0[0x20];
12680 u8 reserved_at_20[0x12];
12681 u8 network_option[0x2];
12682 u8 local_ssm_code[0x4];
12683 u8 local_enhanced_ssm_code[0x8];
12685 u8 local_clock_identity[0x40];
12687 u8 reserved_at_80[0x180];
12691 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0),
12697 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0,
12698 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1,
12702 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0,
12703 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1,
12704 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2,
12705 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3,
12706 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4,
12707 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5,
12711 u8 reserved_at_0[0x8];
12712 u8 local_port[0x8];
12713 u8 pnat[0x2];
12714 u8 lp_msb[0x2];
12715 u8 reserved_at_14[0xc];
12717 u8 field_select[0x20];
12719 u8 admin_status[0x4];
12720 u8 oper_status[0x4];
12721 u8 ho_acq[0x1];
12722 u8 reserved_at_49[0xc];
12723 u8 admin_freq_measure[0x1];
12724 u8 oper_freq_measure[0x1];
12725 u8 failure_reason[0x9];
12727 u8 frequency_diff[0x20];
12729 u8 reserved_at_80[0x180];