Lines Matching defs:mlx5_ifc_mtpps_reg_bits
10731 struct mlx5_ifc_mtpps_reg_bits { struct
10732 u8 reserved_at_0[0xc];
10733 u8 cap_number_of_pps_pins[0x4];
10734 u8 reserved_at_10[0x4];
10735 u8 cap_max_num_of_pps_in_pins[0x4];
10736 u8 reserved_at_18[0x4];
10737 u8 cap_max_num_of_pps_out_pins[0x4];
10739 u8 reserved_at_20[0x13];
10740 u8 cap_log_min_npps_period[0x5];
10741 u8 reserved_at_38[0x3];
10742 u8 cap_log_min_out_pulse_duration_ns[0x5];
10744 u8 reserved_at_40[0x4];
10745 u8 cap_pin_3_mode[0x4];
10746 u8 reserved_at_48[0x4];
10747 u8 cap_pin_2_mode[0x4];
10748 u8 reserved_at_50[0x4];
10749 u8 cap_pin_1_mode[0x4];
10750 u8 reserved_at_58[0x4];
10751 u8 cap_pin_0_mode[0x4];
10753 u8 reserved_at_60[0x4];
10754 u8 cap_pin_7_mode[0x4];
10755 u8 reserved_at_68[0x4];
10756 u8 cap_pin_6_mode[0x4];
10757 u8 reserved_at_70[0x4];
10758 u8 cap_pin_5_mode[0x4];
10759 u8 reserved_at_78[0x4];
10760 u8 cap_pin_4_mode[0x4];
10762 u8 field_select[0x20];
10763 u8 reserved_at_a0[0x20];
10765 u8 npps_period[0x40];
10767 u8 enable[0x1];
10768 u8 reserved_at_101[0xb];
10769 u8 pattern[0x4];
10770 u8 reserved_at_110[0x4];
10771 u8 pin_mode[0x4];
10772 u8 pin[0x8];
10774 u8 reserved_at_120[0x2];
10775 u8 out_pulse_duration_ns[0x1e];
10777 u8 time_stamp[0x40];
10779 u8 out_pulse_duration[0x10];
10780 u8 out_periodic_adjustment[0x10];
10781 u8 enhanced_out_periodic_adjustment[0x20];
10783 u8 reserved_at_1c0[0x20];