1261 #define MLX5_CAP_GEN(mdev, cap) \  argument
1264 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1267 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1270 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1273 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1276 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1279 #define MLX5_CAP_ETH(mdev, cap) \  argument
1283 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1287 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1290 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1293 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1296 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1299 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1302 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1305 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1308 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1311 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1314 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1317 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1320 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1323 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1327 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1330 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1333 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1336 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1339 #define MLX5_CAP_ESW(mdev, cap) \  argument
1343 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1347 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1351 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1355 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1359 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1362 #define MLX5_CAP_ODP(mdev, cap)\  argument
1365 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1368 #define MLX5_CAP_QOS(mdev, cap)\  argument
1371 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1397 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1400 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1403 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1406 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1409 #define MLX5_CAP_TLS(mdev, cap) \  argument
1412 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1415 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1419 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1423 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1426 #define MLX5_CAP_CRYPTO(mdev, cap)\  argument
1429 #define MLX5_CAP_MACSEC(mdev, cap)\  argument