include/linux/fsl_ifc.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
20  * The actual number of banks implemented depends on the IFC version
21  *    - IFC version 1.0 implements 4 banks.
22  *    - IFC version 1.1 onward implements 8 banks.
35  * CSPR - Chip Select Property Register
55 /* NAND */
69 					(__ilog2(n) - IFC_AMASK_SHIFT))
110 #define CSOR_NAND_PB(n)		((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
123  * Chip Select Option Register - NOR Flash Mode
150  * Chip Select Option Register - GPCM Mode
152 /* GPCM Mode - Normal */
154 /* GPCM Mode - GenericASIC */
163 #define CSOR_GPCM_GPTO(n)	((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
175 #define CSOR_GPCM_GAPERRD(n)	(((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
199 /* reset all IFC hardware */
224  * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
240 #define IFC_CCR_CLK_DIV(n)		((n-1) << IFC_CCR_CLK_DIV_SHIFT)
241 /* IFC Clock Delay */
245 /* Invert IFC clock before sending out */
247 /* Fedback IFC Clock */
260  * NAND Configuration Register (NCFGR)
266 /* Addressing Mode-ROW0+n/COL0 */
268 /* Addressing Mode-ROW0+n/COL0+n */
279  * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
281 /* General purpose FCM flash command bytes CMD0-CMD7 */
308  * NAND Flash Byte Count Register (NAND_BC)
314  * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
316 /* NAND Machine specific opcodes OP0-OP14*/
350  * in FIR registers- 6bits
390  * NAND Chip Select Register (NAND_CSEL)
400  * NAND Operation Sequence Start (NANDSEQ_STRT)
402 /* NAND Flash Operation Start */
416  * NAND Event and Error Status Register (NAND_EVTER_STAT)
434  * NAND Flash Page Read Completion Event Status Register
438 /* Small Page 0-15 Done */
439 #define PGRDCMPL_EVT_STAT_SECTION_SP(n)	(1 << (31 - (n)))
440 /* Large Page(2K) 0-3 Done */
441 #define PGRDCMPL_EVT_STAT_LP_2K(n)	(0xF << (28 - (n)*4))
442 /* Large Page(4K) 0-1 Done */
443 #define PGRDCMPL_EVT_STAT_LP_4K(n)	(0xFF << (24 - (n)*8))
446  * NAND Event and Error Enable Register (NAND_EVTER_EN)
460  * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
474  * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
477 /* Error on CS0-3 for NAND */
486  * NAND Flash Status Register (NAND_FSR)
494  * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
496 /* Number of ECC errors on sector n (n = 0-15) */
531  * NAND Control Register (NANDCR)
535 #define IFC_NAND_NCR_FTOCNT(n)	((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
587  * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
602  * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
614 #define IFC_NORCR_NUM_PHASE(n)	((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
618 #define IFC_NORCR_STOCNT(n)	((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
648  * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
663  * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
678  * IFC Controller NAND Machine registers
742  * IFC controller NOR Machine registers
760  * IFC controller GPCM Machine registers
776  * IFC Controller Registers
832 /* overview of the fsl ifc controller */
842 	void				*nand;  member
857 	if (fsl_ifc_ctrl_dev->little_endian)  in ifc_in32()
869 	if (fsl_ifc_ctrl_dev->little_endian)  in ifc_in16()
884 	if (fsl_ifc_ctrl_dev->little_endian)  in ifc_out32()
892 	if (fsl_ifc_ctrl_dev->little_endian)  in ifc_out16()