1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
18  * typedef dma_cookie_t - an opaque DMA cookie
20  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
31  * enum dma_status - DMA transaction status
46  * enum dma_transaction_type - DMA transaction types/indexes
49  * automatically set as dma devices are registered.
68 /* last transaction type for creation of the capabilities mask */
73  * enum dma_transfer_direction - dma transfer mode and direction indicator
89  * ----------------------------
91  * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
96  *  it is to be repeated and other per-transfer attributes.
103  *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
111  * struct data_chunk - Element of scatter-gather list that makes a frame.
133  * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
164  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
166  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
168  * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
171  * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
172  * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
173  * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
176  * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
180  * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
184  *  repeated when it ends until a transaction is issued on the same channel
208  * enum sum_check_bits - bit position of pq_check_flags
216  * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
217  * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
218  * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
227  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
233  * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
234  * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
239  * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
245  * - DMA_DEV_TO_MEM:
253  * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
264  * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
269  *   4. use dmaengine_desc_set_metadata_len()  to tell the DMA engine the amount
272  * - DMA_DEV_TO_MEM:
289  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
300  * struct dma_router - DMA router structure
301  * @dev: pointer to the DMA router device
310  * struct dma_chan - devices supply DMA channels, clients use them
311  * @device: ptr to the dma device who supplies this channel, always !%NULL
312  * @slave: ptr to the device using this channel
314  * @completed_cookie: last completed cookie for this channel
315  * @chan_id: channel ID for sysfs
319  *	dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx"
321  * @local: per-cpu pointer to a struct dma_chan_percpu
322  * @client_count: how many clients are using this channel
323  * @table_count: number of appearances in the mem-to-mem allocation table
324  * @router: pointer to the DMA router structure
325  * @route_data: channel specific data for the router
326  * @private: private data for certain client-channel associations
347 	/* DMA router */
355  * struct dma_chan_dev - relate sysfs device node to backing channel device
356  * @chan: driver channel device
359  * @chan_dma_dev: The channel is using custom/different dma-mapping
370  * enum dma_slave_buswidth - defines bus width of the DMA slave
387  * struct dma_slave_config - dma slave channel runtime config
389  * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
393  * @src_addr: this is the physical address where DMA slave data
396  * @dst_addr: this is the physical address where DMA slave data
400  * register where DMA data shall be read. If the source
414  * an area instead of a single register to receive the data. Typically the DMA
425  * This struct is passed in as configuration data to a DMA engine
426  * in order to set up a certain channel for DMA transport at runtime.
427  * The DMA device/engine has to provide support for an additional
432  * follows: if it is likely that more than one DMA slave controllers in
453  * enum dma_residue_granularity - Granularity of the reported transfer residue
455  *  DMA channel is only able to tell whether a descriptor has been completed or
456  *  not, which means residue reporting is not supported by this channel. The
463  *  the hardware supports scatter-gather and the segment descriptor has a field
479  * struct dma_slave_caps - expose capabilities of a slave channel only
480  * @src_addr_widths: bit mask of src addr widths the channel supports.
481  *	Width is specified in bytes, e.g. for a channel supporting
482  *	a width of 4 the mask should have BIT(4) set.
483  * @dst_addr_widths: bit mask of dst addr widths the channel supports
484  * @directions: bit mask of slave directions the channel supports.
486  *	each type, the dma controller should set BIT(<TYPE>) and same
488  * @min_burst: min burst capability per-transfer
489  * @max_burst: max burst capability per-transfer
491  *	DMA tansaction with no software intervention for reinitialization.
517 	return dev_name(&chan->dev->device);  in dma_chan_name()
521  * typedef dma_filter_fn - callback filter for dma_request_channel
522  * @chan: channel to be reviewed
526  * suitable channel is passed to this routine for further dispositioning before
527  * being returned.  Where 'suitable' indicates a non-busy channel that
528  * satisfies the given capability mask.  It returns 'true' to indicate that the
529  * channel is suitable.
537 	DMA_TRANS_READ_FAILED,		/* Source DMA read failed */
538 	DMA_TRANS_WRITE_FAILED,		/* Destination DMA write failed */
578  * struct dma_async_tx_descriptor - async transaction descriptor
579  * ---dma generic offload fields---
580  * @cookie: tracking cookie for this transaction, set to -EBUSY if
585  * @chan: target channel for this operation
593  * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the
594  *	DMA driver if metadata mode is supported with the descriptor
595  * ---async_tx api specific fields---
624 	kref_get(&unmap->kref);  in dma_set_unmap()
625 	tx->unmap = unmap;  in dma_set_unmap()
648 	if (!tx->unmap)  in dma_descriptor_unmap()
651 	dmaengine_unmap_put(tx->unmap);  in dma_descriptor_unmap()
652 	tx->unmap = NULL;  in dma_descriptor_unmap()
684 	spin_lock_bh(&txd->lock);  in txd_lock()
688 	spin_unlock_bh(&txd->lock);  in txd_unlock()
692 	txd->next = next;  in txd_chain()
693 	next->parent = txd;  in txd_chain()
697 	txd->parent = NULL;  in txd_clear_parent()
701 	txd->next = NULL;  in txd_clear_next()
705 	return txd->parent;  in txd_parent()
709 	return txd->next;  in txd_next()
714  * struct dma_tx_state - filled in to report the status of
716  * @last: last completed DMA cookie
717  * @used: last issued DMA cookie (i.e. the one in progress)
721  * @in_flight_bytes: amount of data in bytes cached by the DMA.
731  * enum dmaengine_alignment - defines alignment of the DMA async tx
747  * struct dma_slave_map - associates slave device and it's slave channel with
750  * @slave: slave channel name
760  * struct dma_filter - information for slave device/channel to filter_fn/param
763  * @mapcnt: number of slave device/channel in the map
764  * @map: array of channel to filter mapping data
773  * struct dma_device - info on the entity supplying DMA services
774  * @ref: reference is taken and put every time a channel is allocated or freed
775  * @chancnt: how many DMA channels are supported
776  * @privatecnt: how many DMA channels are requested by dma_request_channel
781  * @desc_metadata_modes: supported metadata modes by the DMA device
783  * @max_pq: maximum number of PQ sources and PQ-continue capability
789  * @dev: struct device reference for dma mapping api
791  * @chan_ida: unique channel ID
792  * @src_addr_widths: bit mask of src addr widths the device supports
794  *	a width of 4 the mask should have BIT(4) set.
795  * @dst_addr_widths: bit mask of dst addr widths the device supports
796  * @directions: bit mask of slave directions the device supports.
798  *	each type, the dma controller should set BIT(<TYPE>) and same
800  * @min_burst: min burst capability per-transfer
801  * @max_burst: max burst capability per-transfer
803  *	DMA tansaction with no software intervention for reinitialization.
810  * @device_router_config: optional callback for DMA router configuration
811  * @device_free_chan_resources: release DMA channel's resources
820  * @device_prep_slave_sg: prepares a slave dma operation
821  * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
825  * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
826  * @device_caps: May be used to override the generic DMA slave capabilities
827  *	with per-channel specific ones
828  * @device_config: Pushes a new configuration to a channel, return 0 or an error
830  * @device_pause: Pauses any transfer happening on a channel. Returns
832  * @device_resume: Resumes any transfer on a channel previously
834  * @device_terminate_all: Aborts all transfers on a channel. Returns 0
948 	if (chan->device->device_config)  in dmaengine_slave_config()
949 		return chan->device->device_config(chan, config);  in dmaengine_slave_config()
951 	return -ENOSYS;  in dmaengine_slave_config()
969 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)  in dmaengine_prep_slave_single()
972 	return chan->device->device_prep_slave_sg(chan, &sg, 1,  in dmaengine_prep_slave_single()
980 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)  in dmaengine_prep_slave_sg()
983 	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,  in dmaengine_prep_slave_sg()
994 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)  in dmaengine_prep_rio_sg()
997 	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,  in dmaengine_prep_rio_sg()
1007 	if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)  in dmaengine_prep_dma_cyclic()
1010 	return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,  in dmaengine_prep_dma_cyclic()
1018 	if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)  in dmaengine_prep_interleaved_dma()
1021 	    !test_bit(DMA_REPEAT, chan->device->cap_mask.bits))  in dmaengine_prep_interleaved_dma()
1024 	return chan->device->device_prep_interleaved_dma(chan, xt, flags);  in dmaengine_prep_interleaved_dma()
1028  * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor.
1029  * @chan: The channel to be used for this descriptor
1033  * @flags: DMA engine flags
1039 	if (!chan || !chan->device || !chan->device->device_prep_dma_memset)  in dmaengine_prep_dma_memset()
1042 	return chan->device->device_prep_dma_memset(chan, dest, value,  in dmaengine_prep_dma_memset()
1050 	if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)  in dmaengine_prep_dma_memcpy()
1053 	return chan->device->device_prep_dma_memcpy(chan, dest, src,  in dmaengine_prep_dma_memcpy()
1063 	return !!(chan->device->desc_metadata_modes & mode);  in dmaengine_is_metadata_mode_supported()
1077 	return -EINVAL;  in dmaengine_desc_attach_metadata()
1088 	return -EINVAL;  in dmaengine_desc_set_metadata_len()
1093  * dmaengine_terminate_all() - Terminate all active DMA transfers
1094  * @chan: The channel for which to terminate the transfers
1101 	if (chan->device->device_terminate_all)  in dmaengine_terminate_all()
1102 		return chan->device->device_terminate_all(chan);  in dmaengine_terminate_all()
1104 	return -ENOSYS;  in dmaengine_terminate_all()
1108  * dmaengine_terminate_async() - Terminate all active DMA transfers
1109  * @chan: The channel for which to terminate the transfers
1112  * that have previously been submitted to the channel. It is not guaranteed
1123  * complete callback of a descriptor submitted on the same channel.
1130 	if (chan->device->device_terminate_all)  in dmaengine_terminate_async()
1131 		return chan->device->device_terminate_all(chan);  in dmaengine_terminate_async()
1133 	return -EINVAL;  in dmaengine_terminate_async()
1137  * dmaengine_synchronize() - Synchronize DMA channel termination
1138  * @chan: The channel to synchronize
1140  * Synchronizes to the DMA channel termination to the current context. When this
1150  * This function must only be called from non-atomic context and must not be
1152  * channel.
1158 	if (chan->device->device_synchronize)  in dmaengine_synchronize()
1159 		chan->device->device_synchronize(chan);  in dmaengine_synchronize()
1163  * dmaengine_terminate_sync() - Terminate all active DMA transfers
1164  * @chan: The channel for which to terminate the transfers
1167  * that have previously been submitted to the channel. It is similar to
1168  * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
1172  * This function must only be called from non-atomic context and must not be
1174  * channel.
1191 	if (chan->device->device_pause)  in dmaengine_pause()
1192 		return chan->device->device_pause(chan);  in dmaengine_pause()
1194 	return -ENOSYS;  in dmaengine_pause()
1199 	if (chan->device->device_resume)  in dmaengine_resume()
1200 		return chan->device->device_resume(chan);  in dmaengine_resume()
1202 	return -ENOSYS;  in dmaengine_resume()
1208 	return chan->device->device_tx_status(chan, cookie, state);  in dmaengine_tx_status()
1213 	return desc->tx_submit(desc);  in dmaengine_submit()
1219 	return !(((1 << align) - 1) & (off1 | off2 | len));  in dmaengine_check_align()
1225 	return dmaengine_check_align(dev->copy_align, off1, off2, len);  in is_dma_copy_aligned()
1231 	return dmaengine_check_align(dev->xor_align, off1, off2, len);  in is_dma_xor_aligned()
1237 	return dmaengine_check_align(dev->pq_align, off1, off2, len);  in is_dma_pq_aligned()
1243 	return dmaengine_check_align(dev->fill_align, off1, off2, len);  in is_dma_fill_aligned()
1247 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)  in dma_set_maxpq()  argument
1249 	dma->max_pq = maxpq;  in dma_set_maxpq()
1251 		dma->max_pq |= DMA_HAS_PQ_CONTINUE;  in dma_set_maxpq()
1261 	enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;  in dmaf_p_disabled_continue()  local
1263 	return (flags & mask) == mask;  in dmaf_p_disabled_continue()
1266 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)  in dma_dev_has_pq_continue()  argument
1268 	return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;  in dma_dev_has_pq_continue()
1271 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)  in dma_dev_to_maxpq()  argument
1273 	return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;  in dma_dev_to_maxpq()
1276 /* dma_maxpq - reduce maxpq in the face of continued operations
1277  * @dma - dma device with PQ capability
1278  * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1289 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)  in dma_maxpq()  argument
1291 	if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))  in dma_maxpq()
1292 		return dma_dev_to_maxpq(dma);  in dma_maxpq()
1294 		return dma_dev_to_maxpq(dma) - 1;  in dma_maxpq()
1296 		return dma_dev_to_maxpq(dma) - 3;  in dma_maxpq()
1316 	return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,  in dmaengine_get_dst_icg()
1317 				 chunk->icg, chunk->dst_icg);  in dmaengine_get_dst_icg()
1323 	return dmaengine_get_icg(xt->src_inc, xt->src_sgl,  in dmaengine_get_src_icg()
1324 				 chunk->icg, chunk->src_icg);  in dmaengine_get_src_icg()
1327 /* --- public DMA engine API --- */
1367 	tx->flags |= DMA_CTRL_ACK;  in async_tx_ack()
1372 	tx->flags &= ~DMA_CTRL_ACK;  in async_tx_clear_ack()
1377 	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;  in async_tx_test_ack()
1380 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))  argument
1384 	set_bit(tx_type, dstp->bits);  in __dma_cap_set()
1387 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))  argument
1391 	clear_bit(tx_type, dstp->bits);  in __dma_cap_clear()
1394 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))  argument
1397 	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);  in __dma_cap_zero()
1400 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))  argument
1404 	return test_bit(tx_type, srcp->bits);  in __dma_has_cap()
1407 #define for_each_dma_cap_mask(cap, mask) \  argument
1408 	for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1411  * dma_async_issue_pending - flush pending transactions to HW
1412  * @chan: target DMA channel
1419 	chan->device->device_issue_pending(chan);  in dma_async_issue_pending()
1423  * dma_async_is_tx_complete - poll for transaction completion
1424  * @chan: DMA channel
1431  * the status of multiple cookies without re-checking hardware state.
1439 	status = chan->device->device_tx_status(chan, cookie, &state);  in dma_async_is_tx_complete()
1448  * dma_async_is_complete - test a cookie against chan state
1475 	st->last = last;  in dma_set_tx_state()
1476 	st->used = used;  in dma_set_tx_state()
1477 	st->residue = residue;  in dma_set_tx_state()
1485 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1490 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1510 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,  in __dma_request_channel()  argument
1520 	return ERR_PTR(-ENODEV);  in dma_request_chan()
1523 						const dma_cap_mask_t *mask)  in dma_request_chan_by_mask()  argument
1525 	return ERR_PTR(-ENODEV);  in dma_request_chan_by_mask()
1533 	return -ENXIO;  in dma_get_slave_caps()
1542 	ret = dma_get_slave_caps(tx->chan, &caps);  in dmaengine_desc_set_reuse()
1547 		return -EPERM;  in dmaengine_desc_set_reuse()
1549 	tx->flags |= DMA_CTRL_REUSE;  in dmaengine_desc_set_reuse()
1555 	tx->flags &= ~DMA_CTRL_REUSE;  in dmaengine_desc_clear_reuse()
1560 	return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;  in dmaengine_desc_test_reuse()
1567 		return -EPERM;  in dmaengine_desc_free()
1569 	return desc->desc_free(desc);  in dmaengine_desc_free()
1572 /* --- DMA device --- */
1582 #define dma_request_channel(mask, x, y) \  argument
1583 	__dma_request_channel(&(mask), x, y, NULL)
1595 *dma_request_slave_channel_compat(const dma_cap_mask_t mask,  in dma_request_slave_channel_compat()  argument
1608 	return __dma_request_channel(&mask, fn, fn_param, NULL);  in dma_request_slave_channel_compat()
1630 	if (chan->dev->chan_dma_dev)  in dmaengine_get_dma_device()
1631 		return &chan->dev->device;  in dmaengine_get_dma_device()
1633 	return chan->device->dev;  in dmaengine_get_dma_device()