1 /* SPDX-License-Identifier: GPL-2.0 */
3  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14  * top-level framework.  custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42  * struct clk_rate_request - Structure encoding the clk constraints that
67 void clk_hw_init_rate_request(const struct clk_hw *hw,
77  * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88  * struct clk_ops -  Callback operations for hardware clocks; these are to
136  *		0. Returns the calculated rate. Optional, but recommended - if
152  *		Returns 0 on success, -EERROR otherwise.
168  *		Returns 0 on success, -EERROR otherwise.
179  *		Returns 0 on success, -EERROR otherwise.
184  *		Returns the calculated accuracy.  Optional - if	this op is not
189  *		Returned values are 0-359 degrees on success, negative
194  *		0-359. Return 0 on success, otherwise -EERROR.
203  *              and >= numerator) Return 0 on success, otherwise -EERROR.
205  * @init:	Perform platform-specific initialization magic.
207  *		This callback exist for HW which needs to perform some
212  *		Returns 0 on success, -EERROR otherwise.
216  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
220  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
230  * (eg. when a device is opened), and clk_enable when the clock is actually
235 	int		(*prepare)(struct clk_hw *hw);
236 	void		(*unprepare)(struct clk_hw *hw);
237 	int		(*is_prepared)(struct clk_hw *hw);
238 	void		(*unprepare_unused)(struct clk_hw *hw);
239 	int		(*enable)(struct clk_hw *hw);
240 	void		(*disable)(struct clk_hw *hw);
241 	int		(*is_enabled)(struct clk_hw *hw);
242 	void		(*disable_unused)(struct clk_hw *hw);
243 	int		(*save_context)(struct clk_hw *hw);
244 	void		(*restore_context)(struct clk_hw *hw);
245 	unsigned long	(*recalc_rate)(struct clk_hw *hw,
247 	long		(*round_rate)(struct clk_hw *hw, unsigned long rate,
249 	int		(*determine_rate)(struct clk_hw *hw,
251 	int		(*set_parent)(struct clk_hw *hw, u8 index);
252 	u8		(*get_parent)(struct clk_hw *hw);
253 	int		(*set_rate)(struct clk_hw *hw, unsigned long rate,
255 	int		(*set_rate_and_parent)(struct clk_hw *hw,
258 	unsigned long	(*recalc_accuracy)(struct clk_hw *hw,
260 	int		(*get_phase)(struct clk_hw *hw);
261 	int		(*set_phase)(struct clk_hw *hw, int degrees);
262 	int		(*get_duty_cycle)(struct clk_hw *hw,
264 	int		(*set_duty_cycle)(struct clk_hw *hw,
266 	int		(*init)(struct clk_hw *hw);
267 	void		(*terminate)(struct clk_hw *hw);
268 	void		(*debug_init)(struct clk_hw *hw, struct dentry *dentry);
272  * struct clk_parent_data - clk parent information
273  * @hw: parent clk_hw pointer (used for clk providers with internal clks)
279 	const struct clk_hw	*hw;  member
286  * struct clk_init_data - holds init data that's common to all clocks and is
297  * @flags: framework-level hints and quirks
311  * struct clk_hw - handle for traversing from a struct clk to its corresponding
312  * hardware-specific structure.  struct clk_hw should be declared within struct
319  * @clk: pointer to the per-user struct clk instance that can be used to call
342  * struct clk_fixed_rate - fixed-rate clock
343  * @hw:		handle between common and hardware-specific interfaces
349  * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
353 	struct		clk_hw hw;  member
362 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
368 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
372  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
374  * @dev: device that is registering this clock
377  * @flags: framework-specific flags
378  * @fixed_rate: non-adjustable clock rate
385  * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
387  * @dev: device that is registering this clock
390  * @flags: framework-specific flags
391  * @fixed_rate: non-adjustable clock rate
397  * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
399  * @dev: device that is registering this clock
402  * @flags: framework-specific flags
403  * @fixed_rate: non-adjustable clock rate
410  * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
412  * @dev: device that is registering this clock
415  * @flags: framework-specific flags
416  * @fixed_rate: non-adjustable clock rate
424  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
426  * @dev: device that is registering this clock
429  * @flags: framework-specific flags
430  * @fixed_rate: non-adjustable clock rate
431  * @fixed_accuracy: non-adjustable clock accuracy
440  * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
442  * @dev: device that is registering this clock
445  * @flags: framework-specific flags
446  * @fixed_rate: non-adjustable clock rate
447  * @fixed_accuracy: non-adjustable clock accuracy
455  * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
457  * @dev: device that is registering this clock
460  * @flags: framework-specific flags
461  * @fixed_rate: non-adjustable clock rate
462  * @fixed_accuracy: non-adjustable clock accuracy
470  * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
472  * @dev: device that is registering this clock
475  * @flags: framework-specific flags
476  * @fixed_rate: non-adjustable clock rate
485 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
490  * struct clk_gate - gating clock
492  * @hw:		handle between common and hardware-specific interfaces
495  * @flags:	hardware-specific flags
501  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
504  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
505  *	of this register, and mask of gate bits are in higher 16-bit of this
506  *	register.  While setting the gate bits, higher 16-bit should also be
508  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
513 	struct clk_hw hw;  member
520 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
527 struct clk_hw *__clk_hw_register_gate(struct device *dev,
534 struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
541 struct clk *clk_register_gate(struct device *dev, const char *name,
546  * clk_hw_register_gate - register a gate clock with the clock framework
547  * @dev: device that is registering this clock
550  * @flags: framework-specific flags for this clock
551  * @reg: register address to control gating of this clock
553  * @clk_gate_flags: gate-specific flags for this clock
562  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
564  * @dev: device that is registering this clock
567  * @flags: framework-specific flags for this clock
568  * @reg: register address to control gating of this clock
570  * @clk_gate_flags: gate-specific flags for this clock
579  * clk_hw_register_gate_parent_data - register a gate clock with the clock
581  * @dev: device that is registering this clock
584  * @flags: framework-specific flags for this clock
585  * @reg: register address to control gating of this clock
587  * @clk_gate_flags: gate-specific flags for this clock
596  * devm_clk_hw_register_gate - register a gate clock with the clock framework
597  * @dev: device that is registering this clock
600  * @flags: framework-specific flags for this clock
601  * @reg: register address to control gating of this clock
603  * @clk_gate_flags: gate-specific flags for this clock
612  * devm_clk_hw_register_gate_parent_data - register a gate clock with the
614  * @dev: device that is registering this clock
617  * @flags: framework-specific flags for this clock
618  * @reg: register address to control gating of this clock
620  * @clk_gate_flags: gate-specific flags for this clock
631 void clk_hw_unregister_gate(struct clk_hw *hw);
632 int clk_gate_is_enabled(struct clk_hw *hw);
640  * struct clk_divider - adjustable divider clock
642  * @hw:		handle between common and hardware-specific interfaces
653  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
657  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
659  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
664  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
665  *	of this register, and mask of divider bits are in higher 16-bit of this
666  *	register.  While setting the divider bits, higher 16-bit should also be
668  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
670  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
672  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
675  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
680 	struct clk_hw	hw;  member
689 #define clk_div_mask(width)	((1 << (width)) - 1)
690 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
704 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
707 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
711 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
715 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
718 int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
725 struct clk_hw *__clk_hw_register_divider(struct device *dev,
731 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
737 struct clk *clk_register_divider_table(struct device *dev, const char *name,
743  * clk_register_divider - register a divider clock with the clock framework
744  * @dev: device registering this clock
747  * @flags: framework-specific flags
748  * @reg: register address to adjust divider
751  * @clk_divider_flags: divider-specific flags for this clock
760  * clk_hw_register_divider - register a divider clock with the clock framework
761  * @dev: device registering this clock
764  * @flags: framework-specific flags
765  * @reg: register address to adjust divider
768  * @clk_divider_flags: divider-specific flags for this clock
777  * clk_hw_register_divider_parent_hw - register a divider clock with the clock
779  * @dev: device registering this clock
782  * @flags: framework-specific flags
783  * @reg: register address to adjust divider
786  * @clk_divider_flags: divider-specific flags for this clock
796  * clk_hw_register_divider_parent_data - register a divider clock with the clock
798  * @dev: device registering this clock
801  * @flags: framework-specific flags
802  * @reg: register address to adjust divider
805  * @clk_divider_flags: divider-specific flags for this clock
815  * clk_hw_register_divider_table - register a table based divider clock with
817  * @dev: device registering this clock
820  * @flags: framework-specific flags
821  * @reg: register address to adjust divider
824  * @clk_divider_flags: divider-specific flags for this clock
835  * clk_hw_register_divider_table_parent_hw - register a table based divider
837  * @dev: device registering this clock
840  * @flags: framework-specific flags
841  * @reg: register address to adjust divider
844  * @clk_divider_flags: divider-specific flags for this clock
856  * clk_hw_register_divider_table_parent_data - register a table based divider
858  * @dev: device registering this clock
861  * @flags: framework-specific flags
862  * @reg: register address to adjust divider
865  * @clk_divider_flags: divider-specific flags for this clock
878  * devm_clk_hw_register_divider - register a divider clock with the clock framework
879  * @dev: device registering this clock
882  * @flags: framework-specific flags
883  * @reg: register address to adjust divider
886  * @clk_divider_flags: divider-specific flags for this clock
895  * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
896  * @dev: device registering this clock
899  * @flags: framework-specific flags
900  * @reg: register address to adjust divider
903  * @clk_divider_flags: divider-specific flags for this clock
914  * devm_clk_hw_register_divider_table - register a table based divider clock
916  * @dev: device registering this clock
919  * @flags: framework-specific flags
920  * @reg: register address to adjust divider
923  * @clk_divider_flags: divider-specific flags for this clock
936 void clk_hw_unregister_divider(struct clk_hw *hw);
939  * struct clk_mux - multiplexer clock
941  * @hw:		handle between common and hardware-specific interfaces
946  * @flags:	hardware-specific flags
953  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
954  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
955  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
956  *	register, and mask of mux bits are in higher 16-bit of this register.
957  *	While setting the mux bits, higher 16-bit should also be updated to
959  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
961  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
963  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
968 	struct clk_hw	hw;  member
977 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
989 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
996 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
1003 struct clk *clk_register_mux_table(struct device *dev, const char *name,
1011 			       (flags), (reg), (shift), BIT((width)) - 1,     \
1031 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1037 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1043 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1050 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1055 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1062 				   (shift), BIT((width)) - 1,		      \
1070 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1072 int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
1077 void clk_hw_unregister_mux(struct clk_hw *hw);
1082  * struct clk_fixed_factor - fixed multiplier and divider clock
1084  * @hw:		handle between common and hardware-specific interfaces
1094 	struct clk_hw	hw;  member
1099 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
1102 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1106 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
1109 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
1110 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
1113 struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1117 struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1121 struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1125  * struct clk_fractional_divider - adjustable fractional divider clock
1127  * @hw:		handle between common and hardware-specific interfaces
1139  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1143  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1146  * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1151  *	caller's side the power-of-two capable prescaler exists.
1154 	struct clk_hw	hw;  member
1161 	void		(*approximation)(struct clk_hw *hw,
1167 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
1173 struct clk *clk_register_fractional_divider(struct device *dev,
1177 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1181 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1184  * struct clk_multiplier - adjustable multiplier clock
1186  * @hw:		handle between common and hardware-specific interfaces
1196  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1201  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1203  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1208 	struct clk_hw	hw;  member
1216 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1225  * struct clk_composite - aggregate clock of mux, divider and gate clocks
1227  * @hw:		handle between common and hardware-specific interfaces
1228  * @mux_hw:	handle between composite and hardware-specific mux clock
1229  * @rate_hw:	handle between composite and hardware-specific rate clock
1230  * @gate_hw:	handle between composite and hardware-specific gate clock
1236 	struct clk_hw	hw;  member
1248 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1250 struct clk *clk_register_composite(struct device *dev, const char *name,
1256 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1263 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1269 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1276 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1283 void clk_hw_unregister_composite(struct clk_hw *hw);
1285 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1286 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1288 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1289 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1290 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1294 void clk_hw_unregister(struct clk_hw *hw);
1298 const char *clk_hw_get_name(const struct clk_hw *hw);
1308 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1309 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1312 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1313 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1314 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1316 int clk_hw_get_parent_index(struct clk_hw *hw);
1317 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1319 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1320 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1321 #define clk_hw_can_set_rate_parent(hw) \  argument
1322 	(clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1324 bool clk_hw_is_prepared(const struct clk_hw *hw);
1325 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1326 bool clk_hw_is_enabled(const struct clk_hw *hw);
1329 int __clk_mux_determine_rate(struct clk_hw *hw,
1332 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1334 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1337 int clk_hw_determine_rate_no_reparent(struct clk_hw *hw,
1339 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1340 void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,
1342 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1347 	dst->clk = src->clk;  in __clk_hw_set_clk()
1348 	dst->core = src->core;  in __clk_hw_set_clk()
1351 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,  in divider_round_rate()  argument
1356 	return divider_round_rate_parent(hw, clk_hw_get_parent(hw),  in divider_round_rate()
1360 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,  in divider_ro_round_rate()  argument
1366 	return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),  in divider_ro_round_rate()
1374 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1396  * routines, one at of_clk_init(), and one at platform device probe
1490 		.hw.init	= CLK_HW_INIT(_name,			\
1501 		.hw.init	= CLK_HW_INIT_HW(_name,			\
1516 		.hw.init	= CLK_HW_INIT_HWS(_name,		\
1527 		.hw.init	= CLK_HW_INIT_FW_NAME(_name,		\
1542 int devm_of_clk_add_hw_provider(struct device *dev,
1576 static inline int devm_of_clk_add_hw_provider(struct device *dev,  in devm_of_clk_add_hw_provider()
1588 	return ERR_PTR(-ENOENT);  in of_clk_src_simple_get()
1593 	return ERR_PTR(-ENOENT);  in of_clk_hw_simple_get()
1598 	return ERR_PTR(-ENOENT);  in of_clk_src_onecell_get()
1603 	return ERR_PTR(-ENOENT);  in of_clk_hw_onecell_get()
1617 void clk_gate_restore_context(struct clk_hw *hw);