Lines Matching +full:reset +full:- +full:synchronized
1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/reset.h>
67 if (priv->devtype == WDT_RZV2M) { in rzg2l_wdt_reset()
68 /* WDT needs TYPE-B reset control */ in rzg2l_wdt_reset()
69 err = reset_control_assert(priv->rstc); in rzg2l_wdt_reset()
72 ndelay(priv->minimum_assertion_period); in rzg2l_wdt_reset()
73 err = reset_control_deassert(priv->rstc); in rzg2l_wdt_reset()
78 priv->rstc); in rzg2l_wdt_reset()
80 err = reset_control_reset(priv->rstc); in rzg2l_wdt_reset()
89 ndelay(priv->delay); in rzg2l_wdt_wait_delay()
104 writel_relaxed(val, priv->base + reg); in rzg2l_wdt_write()
105 /* Registers other than the WDTINT is always synchronized with WDT_CLK */ in rzg2l_wdt_write()
117 /* 2 consecutive overflow cycle needed to trigger reset */ in rzg2l_wdt_init_timeout()
118 time_out = (wdev->timeout * (MICRO / 2)) / in rzg2l_wdt_init_timeout()
119 rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0); in rzg2l_wdt_init_timeout()
127 pm_runtime_get_sync(wdev->parent); in rzg2l_wdt_start()
146 pm_runtime_put(wdev->parent); in rzg2l_wdt_stop()
153 wdev->timeout = timeout; in rzg2l_wdt_set_timeout()
156 * If the watchdog is active, reset the module for updating the WDTSET in rzg2l_wdt_set_timeout()
158 * to reset the module) so that it is updated with new timeout values. in rzg2l_wdt_set_timeout()
173 clk_prepare_enable(priv->pclk); in rzg2l_wdt_restart()
174 clk_prepare_enable(priv->osc_clk); in rzg2l_wdt_restart()
176 if (priv->devtype == WDT_RZG2L) { in rzg2l_wdt_restart()
177 /* Generate Reset (WDTRSTB) Signal on parity error */ in rzg2l_wdt_restart()
186 wdev->timeout = 0; in rzg2l_wdt_restart()
197 /* Wait 2 consecutive overflow cycles for reset */ in rzg2l_wdt_restart()
198 mdelay(DIV_ROUND_UP(2 * 0xFFFFF * 1000, priv->osc_clk_rate)); in rzg2l_wdt_restart()
232 pm_runtime_disable(wdev->parent); in rzg2l_wdt_reset_assert_pm_disable()
233 reset_control_assert(priv->rstc); in rzg2l_wdt_reset_assert_pm_disable()
238 struct device *dev = &pdev->dev; in rzg2l_wdt_probe()
245 return -ENOMEM; in rzg2l_wdt_probe()
247 priv->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_wdt_probe()
248 if (IS_ERR(priv->base)) in rzg2l_wdt_probe()
249 return PTR_ERR(priv->base); in rzg2l_wdt_probe()
252 priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk"); in rzg2l_wdt_probe()
253 if (IS_ERR(priv->osc_clk)) in rzg2l_wdt_probe()
254 return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk"); in rzg2l_wdt_probe()
256 priv->osc_clk_rate = clk_get_rate(priv->osc_clk); in rzg2l_wdt_probe()
257 if (!priv->osc_clk_rate) in rzg2l_wdt_probe()
258 return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0"); in rzg2l_wdt_probe()
261 priv->pclk = devm_clk_get(&pdev->dev, "pclk"); in rzg2l_wdt_probe()
262 if (IS_ERR(priv->pclk)) in rzg2l_wdt_probe()
263 return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk"); in rzg2l_wdt_probe()
265 pclk_rate = clk_get_rate(priv->pclk); in rzg2l_wdt_probe()
267 return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0"); in rzg2l_wdt_probe()
269 priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9; in rzg2l_wdt_probe()
271 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); in rzg2l_wdt_probe()
272 if (IS_ERR(priv->rstc)) in rzg2l_wdt_probe()
273 return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc), in rzg2l_wdt_probe()
274 "failed to get cpg reset"); in rzg2l_wdt_probe()
276 ret = reset_control_deassert(priv->rstc); in rzg2l_wdt_probe()
280 priv->devtype = (uintptr_t)of_device_get_match_data(dev); in rzg2l_wdt_probe()
282 if (priv->devtype == WDT_RZV2M) { in rzg2l_wdt_probe()
283 priv->minimum_assertion_period = RZV2M_A_NSEC + in rzg2l_wdt_probe()
285 max(F2CYCLE_NSEC(priv->osc_clk_rate), in rzg2l_wdt_probe()
289 pm_runtime_enable(&pdev->dev); in rzg2l_wdt_probe()
291 priv->wdev.info = &rzg2l_wdt_ident; in rzg2l_wdt_probe()
292 priv->wdev.ops = &rzg2l_wdt_ops; in rzg2l_wdt_probe()
293 priv->wdev.parent = dev; in rzg2l_wdt_probe()
294 priv->wdev.min_timeout = 1; in rzg2l_wdt_probe()
295 priv->wdev.max_timeout = rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0xfff) / in rzg2l_wdt_probe()
297 priv->wdev.timeout = WDT_DEFAULT_TIMEOUT; in rzg2l_wdt_probe()
299 watchdog_set_drvdata(&priv->wdev, priv); in rzg2l_wdt_probe()
300 ret = devm_add_action_or_reset(&pdev->dev, in rzg2l_wdt_probe()
302 &priv->wdev); in rzg2l_wdt_probe()
306 watchdog_set_nowayout(&priv->wdev, nowayout); in rzg2l_wdt_probe()
307 watchdog_stop_on_unregister(&priv->wdev); in rzg2l_wdt_probe()
309 ret = watchdog_init_timeout(&priv->wdev, 0, dev); in rzg2l_wdt_probe()
313 return devm_watchdog_register_device(&pdev->dev, &priv->wdev); in rzg2l_wdt_probe()
317 { .compatible = "renesas,rzg2l-wdt", .data = (void *)WDT_RZG2L },
318 { .compatible = "renesas,rzv2m-wdt", .data = (void *)WDT_RZV2M },