Lines Matching +full:- +full:l
1 // SPDX-License-Identifier: GPL-2.0-only
41 return -EBUSY; in dss_pll_register()
61 if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0) in dss_pll_find()
72 r = clk_prepare_enable(pll->clkin); in dss_pll_enable()
76 if (pll->regulator) { in dss_pll_enable()
77 r = regulator_enable(pll->regulator); in dss_pll_enable()
82 r = pll->ops->enable(pll); in dss_pll_enable()
89 if (pll->regulator) in dss_pll_enable()
90 regulator_disable(pll->regulator); in dss_pll_enable()
92 clk_disable_unprepare(pll->clkin); in dss_pll_enable()
98 pll->ops->disable(pll); in dss_pll_disable()
100 if (pll->regulator) in dss_pll_disable()
101 regulator_disable(pll->regulator); in dss_pll_disable()
103 clk_disable_unprepare(pll->clkin); in dss_pll_disable()
105 memset(&pll->cinfo, 0, sizeof(pll->cinfo)); in dss_pll_disable()
112 r = pll->ops->set_config(pll, cinfo); in dss_pll_set_config()
116 pll->cinfo = *cinfo; in dss_pll_set_config()
125 const struct dss_pll_hw *hw = pll->hw; in dss_pll_hsdiv_calc()
134 m_stop = min((unsigned)(clkdco / out_min), hw->mX_max); in dss_pll_hsdiv_calc()
150 const struct dss_pll_hw *hw = pll->hw; in dss_pll_calc()
157 pll_hw_max = hw->clkdco_max; in dss_pll_calc()
159 fint_hw_min = hw->fint_min; in dss_pll_calc()
160 fint_hw_max = hw->fint_max; in dss_pll_calc()
163 n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max); in dss_pll_calc()
174 hw->m_max); in dss_pll_calc()
195 while (t-- > 0) { in wait_for_bit_change()
216 void __iomem *base = pll->base; in dss_pll_wait_reset_done()
219 return -ETIMEDOUT; in dss_pll_wait_reset_done()
228 while (t-- > 0) { in dss_wait_hsdiv_ack()
229 u32 v = readl_relaxed(pll->base + PLL_STATUS); in dss_wait_hsdiv_ack()
235 return -ETIMEDOUT; in dss_wait_hsdiv_ack()
241 const struct dss_pll_hw *hw = pll->hw; in dss_pll_write_config_type_a()
242 void __iomem *base = pll->base; in dss_pll_write_config_type_a()
244 u32 l; in dss_pll_write_config_type_a() local
246 l = 0; in dss_pll_write_config_type_a()
247 if (hw->has_stopmode) in dss_pll_write_config_type_a()
248 l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */ in dss_pll_write_config_type_a()
249 l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb); /* PLL_REGN */ in dss_pll_write_config_type_a()
250 l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb); /* PLL_REGM */ in dss_pll_write_config_type_a()
252 l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0, in dss_pll_write_config_type_a()
253 hw->mX_msb[0], hw->mX_lsb[0]); in dss_pll_write_config_type_a()
255 l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0, in dss_pll_write_config_type_a()
256 hw->mX_msb[1], hw->mX_lsb[1]); in dss_pll_write_config_type_a()
257 writel_relaxed(l, base + PLL_CONFIGURATION1); in dss_pll_write_config_type_a()
259 l = 0; in dss_pll_write_config_type_a()
261 l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0, in dss_pll_write_config_type_a()
262 hw->mX_msb[2], hw->mX_lsb[2]); in dss_pll_write_config_type_a()
264 l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0, in dss_pll_write_config_type_a()
265 hw->mX_msb[3], hw->mX_lsb[3]); in dss_pll_write_config_type_a()
266 writel_relaxed(l, base + PLL_CONFIGURATION3); in dss_pll_write_config_type_a()
268 l = readl_relaxed(base + PLL_CONFIGURATION2); in dss_pll_write_config_type_a()
269 if (hw->has_freqsel) { in dss_pll_write_config_type_a()
270 u32 f = cinfo->fint < 1000000 ? 0x3 : in dss_pll_write_config_type_a()
271 cinfo->fint < 1250000 ? 0x4 : in dss_pll_write_config_type_a()
272 cinfo->fint < 1500000 ? 0x5 : in dss_pll_write_config_type_a()
273 cinfo->fint < 1750000 ? 0x6 : in dss_pll_write_config_type_a()
276 l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */ in dss_pll_write_config_type_a()
277 } else if (hw->has_selfreqdco) { in dss_pll_write_config_type_a()
278 u32 f = cinfo->clkdco < hw->clkdco_low ? 0x2 : 0x4; in dss_pll_write_config_type_a()
280 l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */ in dss_pll_write_config_type_a()
282 l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */ in dss_pll_write_config_type_a()
283 l = FLD_MOD(l, 0, 14, 14); /* PHY_CLKINEN */ in dss_pll_write_config_type_a()
284 l = FLD_MOD(l, 0, 16, 16); /* M4_CLOCK_EN */ in dss_pll_write_config_type_a()
285 l = FLD_MOD(l, 0, 18, 18); /* M5_CLOCK_EN */ in dss_pll_write_config_type_a()
286 l = FLD_MOD(l, 1, 20, 20); /* HSDIVBYPASS */ in dss_pll_write_config_type_a()
287 if (hw->has_refsel) in dss_pll_write_config_type_a()
288 l = FLD_MOD(l, 3, 22, 21); /* REFSEL = sysclk */ in dss_pll_write_config_type_a()
289 l = FLD_MOD(l, 0, 23, 23); /* M6_CLOCK_EN */ in dss_pll_write_config_type_a()
290 l = FLD_MOD(l, 0, 25, 25); /* M7_CLOCK_EN */ in dss_pll_write_config_type_a()
291 writel_relaxed(l, base + PLL_CONFIGURATION2); in dss_pll_write_config_type_a()
297 r = -EIO; in dss_pll_write_config_type_a()
303 r = -EIO; in dss_pll_write_config_type_a()
307 l = readl_relaxed(base + PLL_CONFIGURATION2); in dss_pll_write_config_type_a()
308 l = FLD_MOD(l, 1, 14, 14); /* PHY_CLKINEN */ in dss_pll_write_config_type_a()
309 l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */ in dss_pll_write_config_type_a()
310 l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */ in dss_pll_write_config_type_a()
311 l = FLD_MOD(l, 0, 20, 20); /* HSDIVBYPASS */ in dss_pll_write_config_type_a()
312 l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */ in dss_pll_write_config_type_a()
313 l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */ in dss_pll_write_config_type_a()
314 writel_relaxed(l, base + PLL_CONFIGURATION2); in dss_pll_write_config_type_a()
317 (cinfo->mX[0] ? BIT(7) : 0) | in dss_pll_write_config_type_a()
318 (cinfo->mX[1] ? BIT(8) : 0) | in dss_pll_write_config_type_a()
319 (cinfo->mX[2] ? BIT(10) : 0) | in dss_pll_write_config_type_a()
320 (cinfo->mX[3] ? BIT(11) : 0)); in dss_pll_write_config_type_a()
333 const struct dss_pll_hw *hw = pll->hw; in dss_pll_write_config_type_b()
334 void __iomem *base = pll->base; in dss_pll_write_config_type_b()
335 u32 l; in dss_pll_write_config_type_b() local
337 l = 0; in dss_pll_write_config_type_b()
338 l = FLD_MOD(l, cinfo->m, 20, 9); /* PLL_REGM */ in dss_pll_write_config_type_b()
339 l = FLD_MOD(l, cinfo->n - 1, 8, 1); /* PLL_REGN */ in dss_pll_write_config_type_b()
340 writel_relaxed(l, base + PLL_CONFIGURATION1); in dss_pll_write_config_type_b()
342 l = readl_relaxed(base + PLL_CONFIGURATION2); in dss_pll_write_config_type_b()
343 l = FLD_MOD(l, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ in dss_pll_write_config_type_b()
344 l = FLD_MOD(l, 0x1, 13, 13); /* PLL_REFEN */ in dss_pll_write_config_type_b()
345 l = FLD_MOD(l, 0x0, 14, 14); /* PHY_CLKINEN */ in dss_pll_write_config_type_b()
346 if (hw->has_refsel) in dss_pll_write_config_type_b()
347 l = FLD_MOD(l, 0x3, 22, 21); /* REFSEL = SYSCLK */ in dss_pll_write_config_type_b()
350 if (cinfo->clkdco > hw->clkdco_low) in dss_pll_write_config_type_b()
351 l = FLD_MOD(l, 0x4, 3, 1); in dss_pll_write_config_type_b()
353 l = FLD_MOD(l, 0x2, 3, 1); in dss_pll_write_config_type_b()
354 writel_relaxed(l, base + PLL_CONFIGURATION2); in dss_pll_write_config_type_b()
356 l = readl_relaxed(base + PLL_CONFIGURATION3); in dss_pll_write_config_type_b()
357 l = FLD_MOD(l, cinfo->sd, 17, 10); /* PLL_REGSD */ in dss_pll_write_config_type_b()
358 writel_relaxed(l, base + PLL_CONFIGURATION3); in dss_pll_write_config_type_b()
360 l = readl_relaxed(base + PLL_CONFIGURATION4); in dss_pll_write_config_type_b()
361 l = FLD_MOD(l, cinfo->mX[0], 24, 18); /* PLL_REGM2 */ in dss_pll_write_config_type_b()
362 l = FLD_MOD(l, cinfo->mf, 17, 0); /* PLL_REGM_F */ in dss_pll_write_config_type_b()
363 writel_relaxed(l, base + PLL_CONFIGURATION4); in dss_pll_write_config_type_b()
369 return -EIO; in dss_pll_write_config_type_b()
374 return -ETIMEDOUT; in dss_pll_write_config_type_b()