21 #define SDRAM_CFG_0   0x49A1
22 #define SDRAM_CFG_1   0xA732
23 #define SDRAM_CFG_2   0x31
24 #define SDRAM_ARB_CFG 0xA0
25 #define SDRAM_REFRESH 0x20
28 #define PMX2_SOFTRESET_DAC_RST		0x0001
29 #define PMX2_SOFTRESET_C1_RST		0x0004
30 #define PMX2_SOFTRESET_C2_RST		0x0008
31 #define PMX2_SOFTRESET_3D_RST		0x0010
32 #define PMX2_SOFTRESET_VIDIN_RST	0x0020
33 #define PMX2_SOFTRESET_TLB_RST		0x0040
34 #define PMX2_SOFTRESET_SD_RST		0x0080
35 #define PMX2_SOFTRESET_VGA_RST		0x0100
36 #define PMX2_SOFTRESET_ROM_RST		0x0200	/* reserved bit, do not reset */
37 #define PMX2_SOFTRESET_TA_RST		0x0400
38 #define PMX2_SOFTRESET_REG_RST		0x4000
39 #define PMX2_SOFTRESET_ALL		0x7fff
48 static u16 CorePllControl = 0x70;
50 #define	PCI_CONFIG_SUBSYS_ID	0x2e
56 #define DAC_PLL_CONFIG_REG         0
67 #define    STG4K3_PLL_MIN_OD      0	/* Min output divider (shift) */
79 volatile u32 i,count=0; \
80     for(i=0;i<X;i++) count++; \
86 	static const u8 adwSDRAMArgCfg0[] = { 0xa0, 0x80, 0xa0, 0xa0, 0xa0 };  in InitSDRAMRegisters()
87 	static const u16 adwSDRAMCfg1[] = { 0x8732, 0x8732, 0xa732, 0xa732, 0x8732 };  in InitSDRAMRegisters()
88 	static const u16 adwSDRAMCfg2[] = { 0x87d2, 0x87d2, 0xa7d2, 0x87d2, 0xa7d2 };  in InitSDRAMRegisters()
95 	dwMemTypeIdx = (dwSubSysID & 0x70) >> 4;  in InitSDRAMRegisters()
96 	dwChipSpeedIdx = (dwSubSysID & 0x180) >> 7;  in InitSDRAMRegisters()
99 		return 0;  in InitSDRAMRegisters()
104 		STG_WRITE_REG(SDRAMConf0, 0x49A1);  in InitSDRAMRegisters()
107 		STG_WRITE_REG(SDRAMConf0, 0x4DF1);  in InitSDRAMRegisters()
111 	STG_WRITE_REG(SDRAMConf2, 0x31);  in InitSDRAMRegisters()
121 	u32 R = 0, F = 0, OD = 0, ODIndex = 0;  in ProgramClock()
122 	u32 ulBestR = 0, ulBestF = 0, ulBestOD = 0;  in ProgramClock()
123 	u32 ulBestClk = 0, ulBestScore = 0;  in ProgramClock()
125 	u32 ulTmp = 0, ulVCO;  in ProgramClock()
127 	static const unsigned char ODValues[] = { 1, 2, 0 };  in ProgramClock()
143 	for (ODIndex = 0; ODIndex < 3; ODIndex++) {  in ProgramClock()
207 						if ((ulScore >= ulBestScore) && (OD > 0)) {  in ProgramClock()
244 	u16 core_pll = 0, sub;  in SetCoreClockPLL()
248 	STG_WRITE_REG(IntMask, 0xFFFF);  in SetCoreClockPLL()
252 	CLEAR_BIT(0);  in SetCoreClockPLL()
257 	CLEAR_BIT(0);  in SetCoreClockPLL()
267 	STG_WRITE_REG(TAConfiguration, 0);  in SetCoreClockPLL()
279 	if (ulChipSpeed == 0)  in SetCoreClockPLL()
288 	/* Send bits 0:7 of the Core PLL Mode register */  in SetCoreClockPLL()
289 	tmp = ((CORE_PLL_MODE_REG_0_7 << 8) | (core_pll & 0x00FF));  in SetCoreClockPLL()
302 	    ((CORE_PLL_MODE_REG_8_15 << 8) | ((core_pll & 0xFF00) >> 8));  in SetCoreClockPLL()
312 #if 0  in SetCoreClockPLL()
314 	tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0));  in SetCoreClockPLL()
318 	tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0));  in SetCoreClockPLL()
322 	return 0;  in SetCoreClockPLL()