Lines Matching +full:mixed +full:- +full:burst
1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/io-64-nonatomic-lo-hi.h>
21 /* Code sharing between pci-quirks and xhci hcd */
22 #include "xhci-ext-caps.h"
23 #include "pci-quirks.h"
31 /* Max number of USB devices for any host controller - limit in section 6.1 */
33 /* Section 5.3.3 - MaxPorts */
43 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
45 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
46 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
47 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
48 * @hcc_params: HCCPARAMS - Capability Parameters
49 * @db_off: DBOFF - Doorbell array offset
50 * @run_regs_off: RTSOFF - Runtime register space offset
62 /* Reserved up to (CAPLENGTH - 0x1C) */
66 /* bits 7:0 - how long is the Capabilities register */
71 /* HCSPARAMS1 - hcs_params1 - bitmasks */
77 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
80 /* HCSPARAMS2 - hcs_params2 - bitmasks */
87 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
91 /* HCSPARAMS3 - hcs_params3 - bitmasks */
97 /* HCCPARAMS - hcc_params - bitmasks */
98 /* true: HC can use 64-bit address pointers */
102 /* true: HC uses 64-byte Device Context structures
103 * FIXME 64-byte context structures aren't supported yet.
116 /* true: HC supports Stopped - Short Packet */
120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
127 /* db_off bitmask - bits 0:1 reserved */
130 /* run_regs_off bitmask - bits 0:4 reserved */
133 /* HCCPARAMS2 - hcc_params2 - bitmasks */
146 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
158 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
159 * @command: USBCMD - xHC command register
160 * @status: USBSTS - xHC status register
165 * @cmd_ring: CRP - 64-bit Command Ring Pointer
166 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
167 * @config_reg: CONFIG - Configure Register
168 * @port_status_base: PORTSCn - base address for Port Status and Control
173 * @port_power_base: PORTPMSCn - base address for
175 * @port_link_base: PORTLIn - base address for Port Link Info (current
187 /* rsvd: offset 0x20-2F */
191 /* rsvd: offset 0x3C-3FF */
198 /* registers for ports 2-255 */
202 /* USBCMD - USB command - command bitmasks */
203 /* start/stop HC execution - do not write unless HC is halted*/
205 /* Reset HC - resets internal HC state machine and all registers (except
210 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
212 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
215 /* light reset (port status stays unchanged) - reset completed when this is 0 */
220 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
222 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
223 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
225 * disabled, or powered-off state.
235 /* IMAN - Interrupt Management Register */
239 /* USBSTS - USB status - status bitmasks */
240 /* HC not running - set to 1 when run/stop bit is cleared. */
244 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
249 /* save state status - '1' means xHC is saving state */
251 /* restore state status - '1' means xHC is restoring state */
257 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
262 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
273 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
277 /* stop ring immediately - abort the currently executing command */
282 /* Command Ring pointer - bit mask for the lower 32 bits. */
285 /* CONFIG - Configure Register - config_reg bitmasks */
286 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
292 /* bits 10:31 - reserved and should be preserved */
294 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
300 /* true: port has an over-current condition */
304 /* Port Link State - bits 5:8
326 * 0 - undefined speed - port hasn't be initialized by a reset yet
327 * 1 - full speed
328 * 2 - low speed
329 * 3 - high speed
330 * 4 - super speed
331 * 5-15 reserved
359 /* Port Link State Write Strobe - set this when changing link state */
371 /* true: over-current change */
373 /* true: reset change - 1 to 0 transition of PORT_RESET */
375 /* port link status change - set on some port link state transitions:
377 * ------------------------------------------------------------------------------
378 * - U3 to Resume Wakeup signaling from a device
379 * - Resume to Recovery to U0 USB 3.0 device resume
380 * - Resume to U0 USB 2.0 device resume
381 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
382 * - U3 to U0 Software resume of USB 2.0 device complete
383 * - U2 to U0 L1 resume of USB 2.1 device complete
384 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
385 * - U0 to disabled L1 entry error with USB 2.1 device
386 * - Any state to inactive Error on USB 3.0 port
389 /* port configure error change - port failed to configure its link partner */
395 /* Cold Attach Status - xHC can set this bit to report device attached during
404 /* wake on over-current (enable) */
407 /* true: device is non-removable - for USB 3.0 roothub emulation */
409 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
412 /* We mark duplicate entries with -1 */
413 #define DUPLICATE_ENTRY ((u8)(-1))
415 /* Port Power Management Status and Control - port_power_base bitmasks */
450 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
470 * struct xhci_intr_reg - Interrupt Register Set
471 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
473 * @irq_control: IMOD - Interrupt Moderation Register.
479 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
498 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
509 /* Counter used to count down the time to the next interrupt - HW use only */
520 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
524 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
533 * MFINDEX - current microframe number
548 * Bits 0 - 7: Endpoint target
549 * Bits 8 - 15: RsvdZ
550 * Bits 16 - 31: Stream ID
594 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
595 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
608 /* Route String - 0:19 */
610 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
614 /* Is this LS/FS device connected through a HS hub? - bit 25 */
616 /* Set if the device is a hub - bit 26 */
618 /* Index of the last valid endpoint context in this device context - 27:31 */
621 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
626 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
637 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
639 * this low or full-speed device. '0' if attached to root hub port.
643 * The number of the downstream facing port of the high-speed hub
651 /* USB device address - assigned by the HC */
667 * @ep_info2: information on endpoint type, max packet size, max burst size,
670 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
678 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
679 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
687 /* offset 0x14 - 0x1f reserved for HC internal use */
693 * Endpoint State - bits 0:2
694 * 0 - disabled
695 * 1 - running
696 * 2 - halted due to halt condition - ok to manipulate endpoint ring
697 * 3 - stopped
698 * 4 - TRB error
699 * 5-7 - reserved
707 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
709 /* Mult - Max number of burtst within an interval, in EP companion desc. */
714 /* Interval - period between requests to an endpoint - 125u increments. */
728 * Force Event - generate transfer events for all TRBs for this endpoint
743 /* bit 7 is Host Initiate Disable - for disabling stream selection */
775 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
777 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
780 * It's useful to pre-allocate these for commands that cannot fail due to
781 * out-of-memory errors, like freeing streams.
804 /* 64-bit stream ring address, cycle state, and stream type */
806 /* offset 0x14 - 0x1f reserved for HC internal use */
810 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
846 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
850 /* ep_interval is zero-based */
852 /* mult and num_packets are one-based */
899 /* Percentage of bus bandwidth reserved for non-periodic transfers */
928 /* ---- Related to URB cancellation ---- */
1042 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1045 /* 64-bit device addresses; we only write 32-bit addresses */
1050 /* TODO: write function to set the 64-bit device DMA address */
1058 /* 64-bit buffer address, or immediate data */
1072 /* Completion Code - only applicable for some types of TRBs */
1170 return "Stopped - Length Invalid"; in xhci_trb_comp_code_string()
1172 return "Stopped - Short Packet"; in xhci_trb_comp_code_string()
1193 /* 64-bit segment pointer*/
1212 /* Address device - disable SetAddress */
1215 /* Configure Endpoint - Deconfigure */
1218 /* Stop Ring - Transfer State Preserve */
1250 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1251 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1267 /* Port ID - bits 31:24 */
1273 /* transfer_len bitmasks - bits 0:16 */
1280 /* Interrupter Target - which MSI-X vector to target the completion event at */
1283 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1287 /* Cycle bit - indicates TRB ownership by HC or HCD */
1353 /* Transfer Ring No-op (not for the command ring) */
1382 /* Force Header Command - generate a transaction or link management packet */
1384 /* No-op Command - not for transfer rings */
1386 /* TRB IDs 24-31 reserved */
1400 /* Device Notification Event - device sent function wake notification */
1402 /* MFINDEX Wrap Event - microframe counter wrapped */
1404 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1406 /* Nec vendor-specific command completion event. */
1429 return "No-Op"; in xhci_trb_type_string()
1459 return "No-Op Command"; in xhci_trb_type_string()
1486 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1497 * since the command ring is 64-byte aligned.
1502 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1509 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1510 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1525 /* Max packet sized bounce buffer for td-fragmant alignment */
1624 /* 64-bit event ring segment address */
1634 /* xhci->event_ring keeps track of segment dma addresses */
1678 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1745 /* Cached register copies of read-only HC data */
1769 /* MSI-X/MSI vectors */
1811 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1814 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1817 * they see this status (any time they drop and re-acquire xhci->lock).
1915 /* platform-specific data -- must come last */
1946 primary_hcd = hcd->primary_hcd; in hcd_to_xhci()
1948 return (struct xhci_hcd *) (primary_hcd->hcd_priv); in hcd_to_xhci()
1953 return xhci->main_hcd; in xhci_to_hcd()
1958 if (xhci->shared_hcd) in xhci_get_usb3_hcd()
1959 return xhci->shared_hcd; in xhci_get_usb3_hcd()
1961 if (!xhci->usb2_rhub.num_ports) in xhci_get_usb3_hcd()
1962 return xhci->main_hcd; in xhci_get_usb3_hcd()
1976 return xhci->allow_single_roothub && in xhci_has_one_roothub()
1977 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); in xhci_has_one_roothub()
1981 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1983 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1985 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1987 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1989 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1994 * Some xHCI implementations may support 64-bit address pointers. Registers
1995 * with 64-bit address pointers should be written to with dword accesses by
1997 * xHCI implementations that do not support 64-bit address pointers will ignore
2013 return xhci->quirks & XHCI_LINK_TRB_QUIRK; in xhci_link_trb_quirk()
2219 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, in xhci_urb_to_transfer_ring()
2220 xhci_get_endpoint_index(&urb->ep->desc), in xhci_urb_to_transfer_ring()
2221 urb->stream_id); in xhci_urb_to_transfer_ring()
2231 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && in xhci_urb_suitable_for_idt()
2232 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && in xhci_urb_suitable_for_idt()
2233 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && in xhci_urb_suitable_for_idt()
2234 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && in xhci_urb_suitable_for_idt()
2235 !urb->num_sgs) in xhci_urb_suitable_for_idt()
2471 "type '%s' -> raw %08x %08x %08x %08x", in xhci_decode_trb()
2526 s = "full-speed"; in xhci_decode_slot_context()
2529 s = "low-speed"; in xhci_decode_slot_context()
2532 s = "high-speed"; in xhci_decode_slot_context()
2535 s = "super-speed"; in xhci_decode_slot_context()
2538 s = "super-speed plus"; in xhci_decode_slot_context()
2543 mtt ? " multi-TT" : "", in xhci_decode_slot_context()
2600 portsc & PORT_POWER ? "Powered" : "Powered-off", in xhci_decode_portsc()
2601 portsc & PORT_CONNECT ? "Connected" : "Not-connected", in xhci_decode_portsc()
2609 ret += sprintf(str + ret, "In-Reset "); in xhci_decode_portsc()
2752 u8 burst; in xhci_decode_ep_context() local
2771 burst = CTX_TO_MAX_BURST(info2); in xhci_decode_ep_context()
2785 burst, maxp, deq); in xhci_decode_ep_context()