25 	0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
26 	0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
27 	0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
28 	0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
29 	0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
30 	0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
31 	0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
32 	0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
57 	bos->bNumDeviceCaps = 1;  in xhci_create_usb3x_bos_desc()
80 			ssac = port_cap->psi_count + num_sym_ssa - 1;  in xhci_create_usb3x_bos_desc()
81 			ssic = port_cap->psi_uid_count - 1;  in xhci_create_usb3x_bos_desc()
88 			ssic = (ssac + 1) / 2 - 1;  in xhci_create_usb3x_bos_desc()
139 		for (i = 0; i < ssac + 1; i++)  in xhci_create_usb3x_bos_desc()
169 		/* Shift to Gbps and set SSP Link Protocol if 10Gpbs */  in xhci_create_usb3x_bos_desc()
186 		 * is 20Gbps, but the BOS descriptor lane speed mantissa is  in xhci_create_usb3x_bos_desc()
187 		 * 10Gbps. Check and modify the mantissa value to match the  in xhci_create_usb3x_bos_desc()
193 			 * values. But the lane speed for gen1x2 is 5Gbps while  in xhci_create_usb3x_bos_desc()
194 			 * gen2x1 is 10Gbps. If the previous PSI dword SSID is  in xhci_create_usb3x_bos_desc()
200 				u32 prev = port_cap->psi[i - 1];  in xhci_create_usb3x_bos_desc()
249 			    FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) |  in xhci_create_usb3x_bos_desc()
250 			    FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1));  in xhci_create_usb3x_bos_desc()
264 	/* Bits 1:0 - support per-port power switching, or power always on */  in xhci_common_hub_descriptor()
283 	__u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];  in xhci_usb2_hub_descriptor()
292 	temp = 1 + (ports / 8);  in xhci_usb2_hub_descriptor()
307 			 * is reserved, and bit 1 is for port 1, etc.  in xhci_usb2_hub_descriptor()
309 			port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);  in xhci_usb2_hub_descriptor()
327 	for (i = 0; i < (ports + 1 + 7) / 8; i++)  in xhci_usb2_hub_descriptor()
356 	/* bit 0 is reserved, bit 1 is for port 1, etc. */  in xhci_usb3_hub_descriptor()
360 			port_removable |= 1 << (i + 1);  in xhci_usb3_hub_descriptor()
398 #define	XHCI_PORT_RO	((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
400  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
404 #define XHCI_PORT_RWS	((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
406  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
409 #define	XHCI_PORT_RW1S	((1<<4))
411  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
412  * bits 1, 17, 18, 19, 20, 21, 22, 23
417 #define XHCI_PORT_RW1CS	((1<<1) | (0x7f<<17))
419  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
422 #define	XHCI_PORT_RW	((1<<16))
427 #define	XHCI_PORT_RZ	((1<<2) | (1<<24) | (0xf<<28))
437  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
487  * suspend will set to 1, if suspend bit need to set in command.
567 	for (i = 0; i < LAST_EP_INDEX + 1; i++) {  in xhci_ring_device()
571 			for (s = 1; s < ep->stream_info->num_streams; s++)  in xhci_ring_device()
603 	/* Write 1 to disable the port */  in xhci_disable_port()
608 		 hcd->self.busnum, port->hcd_portnum + 1, portsc);  in xhci_disable_port()
654 	/* Change bits are all write 1 to clear */  in xhci_clear_port_change_bit()
659 		 wIndex + 1, port_change_bit, port_status);  in xhci_clear_port_change_bit()
687 		 hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp);  in xhci_set_port_power()
734 	for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {  in xhci_enter_test_mode()
761 	/* Port is selected by wIndex. port_id = wIndex + 1 */  in xhci_enter_test_mode()
763 					test_mode, wIndex + 1);  in xhci_enter_test_mode()
800 		 port->rhub->hcd->self.busnum, port->hcd_portnum + 1,  in xhci_set_link_state()
908 	u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);  in xhci_del_comp_mod_timer()
915 		xhci->port_status_u0 |= 1 << wIndex;  in xhci_del_comp_mod_timer()
971 			 hcd->self.busnum, wIndex + 1);  in xhci_handle_usb2_port_link_resume()
990 							    wIndex + 1);  in xhci_handle_usb2_port_link_resume()
1000 				  hcd->self.busnum, wIndex + 1, port_status);  in xhci_handle_usb2_port_link_resume()
1010 		bus_state->port_c_suspend |= 1 << wIndex;  in xhci_handle_usb2_port_link_resume()
1011 		bus_state->suspended_ports &= ~(1 << wIndex);  in xhci_handle_usb2_port_link_resume()
1022 	/* only support rx and tx lane counts of 1 in usb3.1 spec */  in xhci_get_ext_port_status()
1073 		if (bus_state->port_remote_wakeup & (1 << portnum)) {  in xhci_get_usb3_port_status()
1074 			bus_state->port_remote_wakeup &= ~(1 << portnum);  in xhci_get_usb3_port_status()
1077 		bus_state->suspended_ports &= ~(1 << portnum);  in xhci_get_usb3_port_status()
1106 			if (bus_state->suspended_ports & (1 << portnum)) {  in xhci_get_usb2_port_status()
1107 				bus_state->suspended_ports &= ~(1 << portnum);  in xhci_get_usb2_port_status()
1108 				bus_state->port_c_suspend |= 1 << portnum;  in xhci_get_usb2_port_status()
1134 		bus_state->suspended_ports &= ~(1 << portnum);  in xhci_get_usb2_port_status()
1191 	if (bus_state->port_c_suspend & (1 << wIndex))  in xhci_get_port_status()
1258 		port = ports[portnum1 - 1];  in xhci_hub_control()
1303 		port = ports[portnum1 - 1];  in xhci_hub_control()
1325 			 * enabled (PED = ‘1’,PLS < ‘3’) state.  in xhci_hub_control()
1343 			xhci_stop_device(xhci, slot_id, 1);  in xhci_hub_control()
1353 			bus_state->suspended_ports |= 1 << wIndex;  in xhci_hub_control()
1473 					xhci_stop_device(xhci, slot_id, 1);  in xhci_hub_control()
1486 				bus_state->suspended_ports |= 1 << wIndex;  in xhci_hub_control()
1553 		port = ports[portnum1 - 1];  in xhci_hub_control()
1585 			bus_state->port_c_suspend |= 1 << wIndex;  in xhci_hub_control()
1596 			bus_state->port_c_suspend &= ~(1 << wIndex);  in xhci_hub_control()
1634  * and 1-indexed from the USB core pointer of view.
1675 			status = 1;  in xhci_hub_status_data()
1693 			(bus_state->port_c_suspend & 1 << i) ||  in xhci_hub_status_data()
1696 			buf[(i + 1) / 8] |= 1 << (i + 1) % 8;  in xhci_hub_status_data()
1697 			status = 1;  in xhci_hub_status_data()
1702 			status = 1;  in xhci_hub_status_data()
1767 				 hcd->self.busnum, port_index + 1);  in xhci_bus_suspend()
1786 				 hcd->self.busnum, port_index + 1);  in xhci_bus_suspend()
1827 							    port_index + 1);  in xhci_bus_suspend()
1830 				xhci_stop_device(xhci, slot_id, 1);  in xhci_bus_suspend()
1921 				 hcd->self.busnum, port_index + 1);  in xhci_bus_resume()
1969 				  hcd->self.busnum, port_index + 1);  in xhci_bus_resume()
1973 		slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);  in xhci_bus_resume()