Lines Matching +full:rk3066 +full:- +full:usb
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2004-2016 Synopsys, Inc.
9 #include <linux/usb/of.h>
20 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_bcm_params()
22 p->host_rx_fifo_size = 774; in dwc2_set_bcm_params()
23 p->max_transfer_size = 65535; in dwc2_set_bcm_params()
24 p->max_packet_count = 511; in dwc2_set_bcm_params()
25 p->ahbcfg = 0x10; in dwc2_set_bcm_params()
30 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_his_params()
32 p->otg_caps.hnp_support = false; in dwc2_set_his_params()
33 p->otg_caps.srp_support = false; in dwc2_set_his_params()
34 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_his_params()
35 p->host_rx_fifo_size = 512; in dwc2_set_his_params()
36 p->host_nperio_tx_fifo_size = 512; in dwc2_set_his_params()
37 p->host_perio_tx_fifo_size = 512; in dwc2_set_his_params()
38 p->max_transfer_size = 65535; in dwc2_set_his_params()
39 p->max_packet_count = 511; in dwc2_set_his_params()
40 p->host_channels = 16; in dwc2_set_his_params()
41 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_his_params()
42 p->phy_utmi_width = 8; in dwc2_set_his_params()
43 p->i2c_enable = false; in dwc2_set_his_params()
44 p->reload_ctl = false; in dwc2_set_his_params()
45 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_his_params()
47 p->change_speed_quirk = true; in dwc2_set_his_params()
48 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_his_params()
53 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_jz4775_params()
55 p->otg_caps.hnp_support = false; in dwc2_set_jz4775_params()
56 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_jz4775_params()
57 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_jz4775_params()
58 p->phy_utmi_width = 16; in dwc2_set_jz4775_params()
59 p->activate_ingenic_overcurrent_detection = in dwc2_set_jz4775_params()
60 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_jz4775_params()
65 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_loongson_params()
67 p->phy_utmi_width = 8; in dwc2_set_loongson_params()
68 p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL; in dwc2_set_loongson_params()
73 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_x1600_params()
75 p->otg_caps.hnp_support = false; in dwc2_set_x1600_params()
76 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_x1600_params()
77 p->host_channels = 16; in dwc2_set_x1600_params()
78 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_x1600_params()
79 p->phy_utmi_width = 16; in dwc2_set_x1600_params()
80 p->activate_ingenic_overcurrent_detection = in dwc2_set_x1600_params()
81 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_x1600_params()
86 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_x2000_params()
88 p->otg_caps.hnp_support = false; in dwc2_set_x2000_params()
89 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_x2000_params()
90 p->host_rx_fifo_size = 1024; in dwc2_set_x2000_params()
91 p->host_nperio_tx_fifo_size = 1024; in dwc2_set_x2000_params()
92 p->host_perio_tx_fifo_size = 1024; in dwc2_set_x2000_params()
93 p->host_channels = 16; in dwc2_set_x2000_params()
94 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_x2000_params()
95 p->phy_utmi_width = 16; in dwc2_set_x2000_params()
96 p->activate_ingenic_overcurrent_detection = in dwc2_set_x2000_params()
97 !device_property_read_bool(hsotg->dev, "disable-over-current"); in dwc2_set_x2000_params()
102 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_s3c6400_params()
104 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_s3c6400_params()
105 p->no_clock_gating = true; in dwc2_set_s3c6400_params()
106 p->phy_utmi_width = 8; in dwc2_set_s3c6400_params()
111 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_socfpga_agilex_params()
113 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_socfpga_agilex_params()
114 p->no_clock_gating = true; in dwc2_set_socfpga_agilex_params()
119 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_rk_params()
121 p->otg_caps.hnp_support = false; in dwc2_set_rk_params()
122 p->otg_caps.srp_support = false; in dwc2_set_rk_params()
123 p->host_rx_fifo_size = 525; in dwc2_set_rk_params()
124 p->host_nperio_tx_fifo_size = 128; in dwc2_set_rk_params()
125 p->host_perio_tx_fifo_size = 256; in dwc2_set_rk_params()
126 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_rk_params()
128 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_rk_params()
129 p->lpm = false; in dwc2_set_rk_params()
130 p->lpm_clock_gating = false; in dwc2_set_rk_params()
131 p->besl = false; in dwc2_set_rk_params()
132 p->hird_threshold_en = false; in dwc2_set_rk_params()
133 p->no_clock_gating = true; in dwc2_set_rk_params()
138 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_ltq_params()
140 p->otg_caps.hnp_support = false; in dwc2_set_ltq_params()
141 p->otg_caps.srp_support = false; in dwc2_set_ltq_params()
142 p->host_rx_fifo_size = 288; in dwc2_set_ltq_params()
143 p->host_nperio_tx_fifo_size = 128; in dwc2_set_ltq_params()
144 p->host_perio_tx_fifo_size = 96; in dwc2_set_ltq_params()
145 p->max_transfer_size = 65535; in dwc2_set_ltq_params()
146 p->max_packet_count = 511; in dwc2_set_ltq_params()
147 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_ltq_params()
153 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_params()
155 p->otg_caps.hnp_support = false; in dwc2_set_amlogic_params()
156 p->otg_caps.srp_support = false; in dwc2_set_amlogic_params()
157 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_amlogic_params()
158 p->host_rx_fifo_size = 512; in dwc2_set_amlogic_params()
159 p->host_nperio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
160 p->host_perio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
161 p->host_channels = 16; in dwc2_set_amlogic_params()
162 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_amlogic_params()
163 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << in dwc2_set_amlogic_params()
165 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_amlogic_params()
170 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_g12a_params()
172 p->lpm = false; in dwc2_set_amlogic_g12a_params()
173 p->lpm_clock_gating = false; in dwc2_set_amlogic_g12a_params()
174 p->besl = false; in dwc2_set_amlogic_g12a_params()
175 p->hird_threshold_en = false; in dwc2_set_amlogic_g12a_params()
180 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_a1_params()
182 p->otg_caps.hnp_support = false; in dwc2_set_amlogic_a1_params()
183 p->otg_caps.srp_support = false; in dwc2_set_amlogic_a1_params()
184 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_amlogic_a1_params()
185 p->host_rx_fifo_size = 192; in dwc2_set_amlogic_a1_params()
186 p->host_nperio_tx_fifo_size = 128; in dwc2_set_amlogic_a1_params()
187 p->host_perio_tx_fifo_size = 128; in dwc2_set_amlogic_a1_params()
188 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_amlogic_a1_params()
189 p->phy_utmi_width = 8; in dwc2_set_amlogic_a1_params()
190 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_amlogic_a1_params()
191 p->lpm = false; in dwc2_set_amlogic_a1_params()
192 p->lpm_clock_gating = false; in dwc2_set_amlogic_a1_params()
193 p->besl = false; in dwc2_set_amlogic_a1_params()
194 p->hird_threshold_en = false; in dwc2_set_amlogic_a1_params()
199 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amcc_params()
201 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_amcc_params()
206 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f4x9_fsotg_params()
208 p->otg_caps.hnp_support = false; in dwc2_set_stm32f4x9_fsotg_params()
209 p->otg_caps.srp_support = false; in dwc2_set_stm32f4x9_fsotg_params()
210 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32f4x9_fsotg_params()
211 p->host_rx_fifo_size = 128; in dwc2_set_stm32f4x9_fsotg_params()
212 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
213 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
214 p->max_packet_count = 256; in dwc2_set_stm32f4x9_fsotg_params()
215 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32f4x9_fsotg_params()
216 p->i2c_enable = false; in dwc2_set_stm32f4x9_fsotg_params()
217 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32f4x9_fsotg_params()
222 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f7_hsotg_params()
224 p->host_rx_fifo_size = 622; in dwc2_set_stm32f7_hsotg_params()
225 p->host_nperio_tx_fifo_size = 128; in dwc2_set_stm32f7_hsotg_params()
226 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32f7_hsotg_params()
231 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_fsotg_params()
233 p->otg_caps.hnp_support = false; in dwc2_set_stm32mp15_fsotg_params()
234 p->otg_caps.srp_support = false; in dwc2_set_stm32mp15_fsotg_params()
235 p->otg_caps.otg_rev = 0x200; in dwc2_set_stm32mp15_fsotg_params()
236 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32mp15_fsotg_params()
237 p->host_rx_fifo_size = 128; in dwc2_set_stm32mp15_fsotg_params()
238 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
239 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
240 p->max_packet_count = 256; in dwc2_set_stm32mp15_fsotg_params()
241 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32mp15_fsotg_params()
242 p->i2c_enable = false; in dwc2_set_stm32mp15_fsotg_params()
243 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32mp15_fsotg_params()
244 p->activate_stm_id_vb_detection = true; in dwc2_set_stm32mp15_fsotg_params()
245 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_stm32mp15_fsotg_params()
246 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_fsotg_params()
247 p->host_support_fs_ls_low_power = true; in dwc2_set_stm32mp15_fsotg_params()
248 p->host_ls_low_power_phy_clk = true; in dwc2_set_stm32mp15_fsotg_params()
253 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_hsotg_params()
255 p->otg_caps.hnp_support = false; in dwc2_set_stm32mp15_hsotg_params()
256 p->otg_caps.srp_support = false; in dwc2_set_stm32mp15_hsotg_params()
257 p->otg_caps.otg_rev = 0x200; in dwc2_set_stm32mp15_hsotg_params()
258 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); in dwc2_set_stm32mp15_hsotg_params()
259 p->host_rx_fifo_size = 440; in dwc2_set_stm32mp15_hsotg_params()
260 p->host_nperio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
261 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
262 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_stm32mp15_hsotg_params()
263 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_hsotg_params()
264 p->lpm = false; in dwc2_set_stm32mp15_hsotg_params()
265 p->lpm_clock_gating = false; in dwc2_set_stm32mp15_hsotg_params()
266 p->besl = false; in dwc2_set_stm32mp15_hsotg_params()
267 p->hird_threshold_en = false; in dwc2_set_stm32mp15_hsotg_params()
271 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
272 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
273 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },
274 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },
275 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },
276 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },
277 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },
278 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
279 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
280 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
281 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
282 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
284 { .compatible = "samsung,s3c6400-hsotg",
286 { .compatible = "amlogic,meson8-usb",
288 { .compatible = "amlogic,meson8b-usb",
290 { .compatible = "amlogic,meson-gxbb-usb",
292 { .compatible = "amlogic,meson-g12a-usb",
294 { .compatible = "amlogic,meson-a1-usb",
296 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
297 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
298 { .compatible = "st,stm32f4x9-fsotg",
300 { .compatible = "st,stm32f4x9-hsotg" },
301 { .compatible = "st,stm32f7-hsotg",
303 { .compatible = "st,stm32mp15-fsotg",
305 { .compatible = "st,stm32mp15-hsotg",
307 { .compatible = "intel,socfpga-agilex-hsotg",
338 switch (hsotg->hw_params.op_mode) { in dwc2_set_param_otg_cap()
340 hsotg->params.otg_caps.hnp_support = true; in dwc2_set_param_otg_cap()
341 hsotg->params.otg_caps.srp_support = true; in dwc2_set_param_otg_cap()
346 hsotg->params.otg_caps.hnp_support = false; in dwc2_set_param_otg_cap()
347 hsotg->params.otg_caps.srp_support = true; in dwc2_set_param_otg_cap()
350 hsotg->params.otg_caps.hnp_support = false; in dwc2_set_param_otg_cap()
351 hsotg->params.otg_caps.srp_support = false; in dwc2_set_param_otg_cap()
359 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_set_param_phy_type()
371 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_param_phy_type()
373 hsotg->params.phy_type = val; in dwc2_set_param_phy_type()
380 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? in dwc2_set_param_speed()
389 hsotg->params.speed = val; in dwc2_set_param_speed()
396 val = (hsotg->hw_params.utmi_phy_data_width == in dwc2_set_param_phy_utmi_width()
399 if (hsotg->phy) { in dwc2_set_param_phy_utmi_width()
402 * width is 8-bit and set the phyif appropriately. in dwc2_set_param_phy_utmi_width()
404 if (phy_get_bus_width(hsotg->phy) == 8) in dwc2_set_param_phy_utmi_width()
408 hsotg->params.phy_utmi_width = val; in dwc2_set_param_phy_utmi_width()
413 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_tx_fifo_sizes()
420 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); in dwc2_set_param_tx_fifo_sizes()
423 p->g_tx_fifo_size[i] = depth_average; in dwc2_set_param_tx_fifo_sizes()
430 if (hsotg->hw_params.hibernation) in dwc2_set_param_power_down()
432 else if (hsotg->hw_params.power_optimized) in dwc2_set_param_power_down()
437 hsotg->params.power_down = val; in dwc2_set_param_power_down()
442 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_lpm()
444 p->lpm = hsotg->hw_params.lpm_mode; in dwc2_set_param_lpm()
445 if (p->lpm) { in dwc2_set_param_lpm()
446 p->lpm_clock_gating = true; in dwc2_set_param_lpm()
447 p->besl = true; in dwc2_set_param_lpm()
448 p->hird_threshold_en = true; in dwc2_set_param_lpm()
449 p->hird_threshold = 4; in dwc2_set_param_lpm()
451 p->lpm_clock_gating = false; in dwc2_set_param_lpm()
452 p->besl = false; in dwc2_set_param_lpm()
453 p->hird_threshold_en = false; in dwc2_set_param_lpm()
458 * dwc2_set_default_params() - Set all core parameters to their
459 * auto-detected default values.
466 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_set_default_params()
467 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_default_params()
468 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); in dwc2_set_default_params()
476 p->phy_ulpi_ddr = false; in dwc2_set_default_params()
477 p->phy_ulpi_ext_vbus = false; in dwc2_set_default_params()
479 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; in dwc2_set_default_params()
480 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; in dwc2_set_default_params()
481 p->i2c_enable = hw->i2c_enable; in dwc2_set_default_params()
482 p->acg_enable = hw->acg_enable; in dwc2_set_default_params()
483 p->ulpi_fs_ls = false; in dwc2_set_default_params()
484 p->ts_dline = false; in dwc2_set_default_params()
485 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); in dwc2_set_default_params()
486 p->uframe_sched = true; in dwc2_set_default_params()
487 p->external_id_pin_ctl = false; in dwc2_set_default_params()
488 p->ipg_isoc_en = false; in dwc2_set_default_params()
489 p->service_interval = false; in dwc2_set_default_params()
490 p->max_packet_count = hw->max_packet_count; in dwc2_set_default_params()
491 p->max_transfer_size = hw->max_transfer_size; in dwc2_set_default_params()
492 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_default_params()
493 p->ref_clk_per = 33333; in dwc2_set_default_params()
494 p->sof_cnt_wkup_alert = 100; in dwc2_set_default_params()
496 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || in dwc2_set_default_params()
497 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_set_default_params()
498 p->host_dma = dma_capable; in dwc2_set_default_params()
499 p->dma_desc_enable = false; in dwc2_set_default_params()
500 p->dma_desc_fs_enable = false; in dwc2_set_default_params()
501 p->host_support_fs_ls_low_power = false; in dwc2_set_default_params()
502 p->host_ls_low_power_phy_clk = false; in dwc2_set_default_params()
503 p->host_channels = hw->host_channels; in dwc2_set_default_params()
504 p->host_rx_fifo_size = hw->rx_fifo_size; in dwc2_set_default_params()
505 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; in dwc2_set_default_params()
506 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; in dwc2_set_default_params()
509 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_set_default_params()
510 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_set_default_params()
511 p->g_dma = dma_capable; in dwc2_set_default_params()
512 p->g_dma_desc = hw->dma_desc_enable; in dwc2_set_default_params()
517 * gadget driver. These defaults have been hard-coded in dwc2_set_default_params()
520 * auto-detect if the hardware does not support the in dwc2_set_default_params()
523 p->g_rx_fifo_size = 2048; in dwc2_set_default_params()
524 p->g_np_tx_fifo_size = 1024; in dwc2_set_default_params()
530 * dwc2_get_device_properties() - Read in device properties.
538 struct dwc2_core_params *p = &hsotg->params; in dwc2_get_device_properties()
541 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_get_device_properties()
542 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_get_device_properties()
543 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", in dwc2_get_device_properties()
544 &p->g_rx_fifo_size); in dwc2_get_device_properties()
546 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", in dwc2_get_device_properties()
547 &p->g_np_tx_fifo_size); in dwc2_get_device_properties()
549 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); in dwc2_get_device_properties()
552 memset(p->g_tx_fifo_size, 0, in dwc2_get_device_properties()
553 sizeof(p->g_tx_fifo_size)); in dwc2_get_device_properties()
554 device_property_read_u32_array(hsotg->dev, in dwc2_get_device_properties()
555 "g-tx-fifo-size", in dwc2_get_device_properties()
556 &p->g_tx_fifo_size[1], in dwc2_get_device_properties()
560 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); in dwc2_get_device_properties()
563 p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current"); in dwc2_get_device_properties()
570 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { in dwc2_check_param_otg_cap()
572 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) in dwc2_check_param_otg_cap()
574 } else if (!hsotg->params.otg_caps.hnp_support) { in dwc2_check_param_otg_cap()
576 if (hsotg->params.otg_caps.srp_support) { in dwc2_check_param_otg_cap()
577 switch (hsotg->hw_params.op_mode) { in dwc2_check_param_otg_cap()
603 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_check_param_phy_type()
604 fs_phy_type = hsotg->hw_params.fs_phy_type; in dwc2_check_param_phy_type()
606 switch (hsotg->params.phy_type) { in dwc2_check_param_phy_type()
632 int phy_type = hsotg->params.phy_type; in dwc2_check_param_speed()
633 int speed = hsotg->params.speed; in dwc2_check_param_speed()
637 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && in dwc2_check_param_speed()
656 int param = hsotg->params.phy_utmi_width; in dwc2_check_param_phy_utmi_width()
657 int width = hsotg->hw_params.utmi_phy_data_width; in dwc2_check_param_phy_utmi_width()
677 int param = hsotg->params.power_down; in dwc2_check_param_power_down()
683 if (hsotg->hw_params.power_optimized) in dwc2_check_param_power_down()
685 dev_dbg(hsotg->dev, in dwc2_check_param_power_down()
690 if (hsotg->hw_params.hibernation) in dwc2_check_param_power_down()
692 dev_dbg(hsotg->dev, in dwc2_check_param_power_down()
697 dev_err(hsotg->dev, in dwc2_check_param_power_down()
704 hsotg->params.power_down = param; in dwc2_check_param_power_down()
716 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; in dwc2_check_param_tx_fifo_sizes()
719 total += hsotg->params.g_tx_fifo_size[fifo]; in dwc2_check_param_tx_fifo_sizes()
722 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", in dwc2_check_param_tx_fifo_sizes()
728 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; in dwc2_check_param_tx_fifo_sizes()
730 if (hsotg->params.g_tx_fifo_size[fifo] < min || in dwc2_check_param_tx_fifo_sizes()
731 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { in dwc2_check_param_tx_fifo_sizes()
732 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", in dwc2_check_param_tx_fifo_sizes()
734 hsotg->params.g_tx_fifo_size[fifo]); in dwc2_check_param_tx_fifo_sizes()
735 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; in dwc2_check_param_tx_fifo_sizes()
741 if ((int)(hsotg->params._param) < (_min) || \
742 (hsotg->params._param) > (_max)) { \
743 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
744 __func__, #_param, hsotg->params._param); \
745 hsotg->params._param = (_def); \
750 if (hsotg->params._param && !(_check)) { \
751 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
752 __func__, #_param, hsotg->params._param); \
753 hsotg->params._param = false; \
759 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_check_params()
760 struct dwc2_core_params *p = &hsotg->params; in dwc2_check_params()
761 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); in dwc2_check_params()
768 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); in dwc2_check_params()
769 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); in dwc2_check_params()
770 CHECK_BOOL(i2c_enable, hw->i2c_enable); in dwc2_check_params()
771 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); in dwc2_check_params()
772 CHECK_BOOL(acg_enable, hw->acg_enable); in dwc2_check_params()
773 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); in dwc2_check_params()
774 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); in dwc2_check_params()
775 CHECK_BOOL(lpm, hw->lpm_mode); in dwc2_check_params()
776 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); in dwc2_check_params()
777 CHECK_BOOL(besl, hsotg->params.lpm); in dwc2_check_params()
778 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); in dwc2_check_params()
779 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); in dwc2_check_params()
780 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); in dwc2_check_params()
781 CHECK_BOOL(service_interval, hw->service_interval_mode); in dwc2_check_params()
783 15, hw->max_packet_count, in dwc2_check_params()
784 hw->max_packet_count); in dwc2_check_params()
786 2047, hw->max_transfer_size, in dwc2_check_params()
787 hw->max_transfer_size); in dwc2_check_params()
789 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || in dwc2_check_params()
790 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_check_params()
792 CHECK_BOOL(dma_desc_enable, p->host_dma); in dwc2_check_params()
793 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); in dwc2_check_params()
795 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); in dwc2_check_params()
797 1, hw->host_channels, in dwc2_check_params()
798 hw->host_channels); in dwc2_check_params()
800 16, hw->rx_fifo_size, in dwc2_check_params()
801 hw->rx_fifo_size); in dwc2_check_params()
803 16, hw->host_nperio_tx_fifo_size, in dwc2_check_params()
804 hw->host_nperio_tx_fifo_size); in dwc2_check_params()
806 16, hw->host_perio_tx_fifo_size, in dwc2_check_params()
807 hw->host_perio_tx_fifo_size); in dwc2_check_params()
810 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_check_params()
811 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_check_params()
813 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); in dwc2_check_params()
815 16, hw->rx_fifo_size, in dwc2_check_params()
816 hw->rx_fifo_size); in dwc2_check_params()
818 16, hw->dev_nperio_tx_fifo_size, in dwc2_check_params()
819 hw->dev_nperio_tx_fifo_size); in dwc2_check_params()
831 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_host_hwparams()
835 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) in dwc2_get_host_hwparams()
843 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_host_hwparams()
845 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_host_hwparams()
856 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_dev_hwparams()
860 if (hsotg->dr_mode == USB_DR_MODE_HOST) in dwc2_get_dev_hwparams()
870 hw->g_tx_fifo_size[fifo] = in dwc2_get_dev_hwparams()
875 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_dev_hwparams()
880 * dwc2_get_hwparams() - During device initialization, read various hardware
888 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_hwparams()
900 hw->dev_ep_dirs = hwcfg1; in dwc2_get_hwparams()
903 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> in dwc2_get_hwparams()
905 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> in dwc2_get_hwparams()
907 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); in dwc2_get_hwparams()
908 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> in dwc2_get_hwparams()
910 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> in dwc2_get_hwparams()
912 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> in dwc2_get_hwparams()
914 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> in dwc2_get_hwparams()
916 hw->nperio_tx_q_depth = in dwc2_get_hwparams()
919 hw->host_perio_tx_q_depth = in dwc2_get_hwparams()
922 hw->dev_token_q_depth = in dwc2_get_hwparams()
929 hw->max_transfer_size = (1 << (width + 11)) - 1; in dwc2_get_hwparams()
932 hw->max_packet_count = (1 << (width + 4)) - 1; in dwc2_get_hwparams()
933 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); in dwc2_get_hwparams()
934 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> in dwc2_get_hwparams()
936 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); in dwc2_get_hwparams()
939 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); in dwc2_get_hwparams()
940 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> in dwc2_get_hwparams()
942 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> in dwc2_get_hwparams()
944 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); in dwc2_get_hwparams()
945 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); in dwc2_get_hwparams()
946 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); in dwc2_get_hwparams()
947 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> in dwc2_get_hwparams()
949 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); in dwc2_get_hwparams()
950 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); in dwc2_get_hwparams()
951 hw->service_interval_mode = !!(hwcfg4 & in dwc2_get_hwparams()
955 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> in dwc2_get_hwparams()
977 set_params = device_get_match_data(hsotg->dev); in dwc2_init_params()
982 pci_match_id(dwc2_pci_ids, to_pci_dev(hsotg->dev->parent)); in dwc2_init_params()
984 if (pmatch && pmatch->driver_data) { in dwc2_init_params()
985 set_params = (set_params_cb)pmatch->driver_data; in dwc2_init_params()