Lines Matching +full:hba +full:- +full:cap
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
16 #include <linux/reset-controller.h>
25 #include "ufshcd-pltfrm.h"
26 #include "ufs-qcom.h"
94 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up);
105 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_enable()
106 qcom_ice_enable(host->ice); in ufs_qcom_ice_enable()
111 struct ufs_hba *hba = host->hba; in ufs_qcom_ice_init() local
112 struct device *dev = hba->dev; in ufs_qcom_ice_init()
116 if (ice == ERR_PTR(-EOPNOTSUPP)) { in ufs_qcom_ice_init()
124 host->ice = ice; in ufs_qcom_ice_init()
125 hba->caps |= UFSHCD_CAP_CRYPTO; in ufs_qcom_ice_init()
132 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_resume()
133 return qcom_ice_resume(host->ice); in ufs_qcom_ice_resume()
140 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_suspend()
141 return qcom_ice_suspend(host->ice); in ufs_qcom_ice_suspend()
146 static int ufs_qcom_ice_program_key(struct ufs_hba *hba, in ufs_qcom_ice_program_key() argument
150 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_ice_program_key()
151 union ufs_crypto_cap_entry cap; in ufs_qcom_ice_program_key() local
153 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; in ufs_qcom_ice_program_key()
155 /* Only AES-256-XTS has been tested so far. */ in ufs_qcom_ice_program_key()
156 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; in ufs_qcom_ice_program_key()
157 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || in ufs_qcom_ice_program_key()
158 cap.key_size != UFS_CRYPTO_KEY_SIZE_256) in ufs_qcom_ice_program_key()
159 return -EOPNOTSUPP; in ufs_qcom_ice_program_key()
162 return qcom_ice_program_key(host->ice, in ufs_qcom_ice_program_key()
165 cfg->crypto_key, in ufs_qcom_ice_program_key()
166 cfg->data_unit_size, slot); in ufs_qcom_ice_program_key()
168 return qcom_ice_evict_key(host->ice, slot); in ufs_qcom_ice_program_key()
197 if (!host->is_lane_clks_enabled) in ufs_qcom_disable_lane_clks()
200 clk_bulk_disable_unprepare(host->num_clks, host->clks); in ufs_qcom_disable_lane_clks()
202 host->is_lane_clks_enabled = false; in ufs_qcom_disable_lane_clks()
209 err = clk_bulk_prepare_enable(host->num_clks, host->clks); in ufs_qcom_enable_lane_clks()
213 host->is_lane_clks_enabled = true; in ufs_qcom_enable_lane_clks()
221 struct device *dev = host->hba->dev; in ufs_qcom_init_lane_clks()
226 err = devm_clk_bulk_get_all(dev, &host->clks); in ufs_qcom_init_lane_clks()
230 host->num_clks = err; in ufs_qcom_init_lane_clks()
235 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) in ufs_qcom_check_hibern8() argument
242 err = ufshcd_dme_get(hba, in ufs_qcom_check_hibern8()
258 err = ufshcd_dme_get(hba, in ufs_qcom_check_hibern8()
264 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_qcom_check_hibern8()
268 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", in ufs_qcom_check_hibern8()
277 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); in ufs_qcom_select_unipro_mode()
279 if (host->hw_ver.major >= 0x05) in ufs_qcom_select_unipro_mode()
280 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); in ufs_qcom_select_unipro_mode()
287 * ufs_qcom_host_reset - reset host controller and PHY
289 static int ufs_qcom_host_reset(struct ufs_hba *hba) in ufs_qcom_host_reset() argument
292 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_host_reset()
295 if (!host->core_reset) in ufs_qcom_host_reset()
298 reenable_intr = hba->is_irq_enabled; in ufs_qcom_host_reset()
299 ufshcd_disable_irq(hba); in ufs_qcom_host_reset()
301 ret = reset_control_assert(host->core_reset); in ufs_qcom_host_reset()
303 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", in ufs_qcom_host_reset()
310 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to in ufs_qcom_host_reset()
315 ret = reset_control_deassert(host->core_reset); in ufs_qcom_host_reset()
317 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", in ufs_qcom_host_reset()
325 ufshcd_enable_irq(hba); in ufs_qcom_host_reset()
330 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) in ufs_qcom_get_hs_gear() argument
332 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_get_hs_gear()
334 if (host->hw_ver.major >= 0x4) in ufs_qcom_get_hs_gear()
335 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); in ufs_qcom_get_hs_gear()
337 /* Default is HS-G3 */ in ufs_qcom_get_hs_gear()
341 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) in ufs_qcom_power_up_sequence() argument
343 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_power_up_sequence()
344 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_power_up_sequence()
345 struct phy *phy = host->generic_phy; in ufs_qcom_power_up_sequence()
350 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. in ufs_qcom_power_up_sequence()
351 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, in ufs_qcom_power_up_sequence()
352 * so that the subsequent power mode change shall stick to Rate-A. in ufs_qcom_power_up_sequence()
354 if (host->hw_ver.major == 0x5) { in ufs_qcom_power_up_sequence()
355 if (host->phy_gear == UFS_HS_G5) in ufs_qcom_power_up_sequence()
356 host_params->hs_rate = PA_HS_MODE_A; in ufs_qcom_power_up_sequence()
358 host_params->hs_rate = PA_HS_MODE_B; in ufs_qcom_power_up_sequence()
361 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; in ufs_qcom_power_up_sequence()
364 ret = ufs_qcom_host_reset(hba); in ufs_qcom_power_up_sequence()
368 /* phy initialization - calibrate the phy */ in ufs_qcom_power_up_sequence()
371 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in ufs_qcom_power_up_sequence()
376 ret = phy_set_mode_ext(phy, mode, host->phy_gear); in ufs_qcom_power_up_sequence()
380 /* power on phy - start serdes and phy's power and clocks */ in ufs_qcom_power_up_sequence()
383 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", in ufs_qcom_power_up_sequence()
400 * Internal hardware sub-modules within the UTP controller control the CGCs.
401 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
406 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) in ufs_qcom_enable_hw_clk_gating() argument
408 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, in ufs_qcom_enable_hw_clk_gating()
415 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, in ufs_qcom_hce_enable_notify() argument
418 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_hce_enable_notify()
423 err = ufs_qcom_power_up_sequence(hba); in ufs_qcom_hce_enable_notify()
436 err = ufs_qcom_check_hibern8(hba); in ufs_qcom_hce_enable_notify()
437 ufs_qcom_enable_hw_clk_gating(hba); in ufs_qcom_hce_enable_notify()
441 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); in ufs_qcom_hce_enable_notify()
442 err = -EINVAL; in ufs_qcom_hce_enable_notify()
449 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
451 * @hba: host controller instance
457 * Return: zero for success and non-zero in case of a failure.
459 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, in ufs_qcom_cfg_timers() argument
463 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_cfg_timers()
474 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) in ufs_qcom_cfg_timers()
478 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); in ufs_qcom_cfg_timers()
479 return -EINVAL; in ufs_qcom_cfg_timers()
482 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_cfg_timers()
483 if (!strcmp(clki->name, "core_clk")) { in ufs_qcom_cfg_timers()
485 core_clk_rate = clki->max_freq; in ufs_qcom_cfg_timers()
487 core_clk_rate = clk_get_rate(clki->clk); in ufs_qcom_cfg_timers()
498 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { in ufs_qcom_cfg_timers()
499 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); in ufs_qcom_cfg_timers()
510 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, in ufs_qcom_link_startup_notify() argument
517 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, in ufs_qcom_link_startup_notify()
519 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_link_startup_notify()
521 return -EINVAL; in ufs_qcom_link_startup_notify()
524 err = ufs_qcom_set_core_clk_ctrl(hba, true); in ufs_qcom_link_startup_notify()
526 dev_err(hba->dev, "cfg core clk ctrl failed\n"); in ufs_qcom_link_startup_notify()
534 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) in ufs_qcom_link_startup_notify()
535 err = ufshcd_disable_host_tx_lcc(hba); in ufs_qcom_link_startup_notify()
545 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) in ufs_qcom_device_reset_ctrl() argument
547 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_device_reset_ctrl()
550 if (!host->device_reset) in ufs_qcom_device_reset_ctrl()
553 gpiod_set_value_cansleep(host->device_reset, asserted); in ufs_qcom_device_reset_ctrl()
556 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, in ufs_qcom_suspend() argument
559 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_suspend()
560 struct phy *phy = host->generic_phy; in ufs_qcom_suspend()
565 if (ufs_qcom_is_link_off(hba)) { in ufs_qcom_suspend()
575 ufs_qcom_device_reset_ctrl(hba, true); in ufs_qcom_suspend()
577 } else if (!ufs_qcom_is_link_active(hba)) { in ufs_qcom_suspend()
584 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) in ufs_qcom_resume() argument
586 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_resume()
587 struct phy *phy = host->generic_phy; in ufs_qcom_resume()
590 if (ufs_qcom_is_link_off(hba)) { in ufs_qcom_resume()
593 dev_err(hba->dev, "%s: failed PHY power on: %d\n", in ufs_qcom_resume()
602 } else if (!ufs_qcom_is_link_active(hba)) { in ufs_qcom_resume()
613 if (host->dev_ref_clk_ctrl_mmio && in ufs_qcom_dev_ref_clk_ctrl()
614 (enable ^ host->is_dev_ref_clk_enabled)) { in ufs_qcom_dev_ref_clk_ctrl()
615 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
618 temp |= host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
620 temp &= ~host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
631 gating_wait = host->hba->dev_info.clk_gating_wait_us; in ufs_qcom_dev_ref_clk_ctrl()
639 * HS-MODE to LS-MODE or HIBERN8 state. Give it in ufs_qcom_dev_ref_clk_ctrl()
647 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
653 readl(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
663 host->is_dev_ref_clk_enabled = enable; in ufs_qcom_dev_ref_clk_ctrl()
669 struct device *dev = host->hba->dev; in ufs_qcom_icc_set_bw()
672 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); in ufs_qcom_icc_set_bw()
678 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); in ufs_qcom_icc_set_bw()
689 struct ufs_pa_layer_attr *p = &host->dev_req_params; in ufs_qcom_get_bw_table()
690 int gear = max_t(u32, p->gear_rx, p->gear_tx); in ufs_qcom_get_bw_table()
691 int lane = max_t(u32, p->lane_rx, p->lane_tx); in ufs_qcom_get_bw_table()
694 if (p->hs_rate == PA_HS_MODE_B) in ufs_qcom_get_bw_table()
712 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, in ufs_qcom_pwr_change_notify() argument
717 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_pwr_change_notify()
718 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_pwr_change_notify()
723 return -EINVAL; in ufs_qcom_pwr_change_notify()
730 dev_err(hba->dev, "%s: failed to determine capabilities\n", in ufs_qcom_pwr_change_notify()
741 if (hba->ufshcd_state == UFSHCD_STATE_RESET) in ufs_qcom_pwr_change_notify()
742 host->phy_gear = dev_req_params->gear_tx; in ufs_qcom_pwr_change_notify()
745 if (!ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
749 if (host->hw_ver.major >= 0x4) { in ufs_qcom_pwr_change_notify()
750 ufshcd_dme_configure_adapt(hba, in ufs_qcom_pwr_change_notify()
751 dev_req_params->gear_tx, in ufs_qcom_pwr_change_notify()
756 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, in ufs_qcom_pwr_change_notify()
757 dev_req_params->pwr_rx, in ufs_qcom_pwr_change_notify()
758 dev_req_params->hs_rate, false, false)) { in ufs_qcom_pwr_change_notify()
759 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_pwr_change_notify()
766 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
770 memcpy(&host->dev_req_params, in ufs_qcom_pwr_change_notify()
776 if (ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
781 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
788 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) in ufs_qcom_quirk_host_pa_saveconfigtime() argument
793 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), in ufs_qcom_quirk_host_pa_saveconfigtime()
799 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), in ufs_qcom_quirk_host_pa_saveconfigtime()
803 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) in ufs_qcom_apply_dev_quirks() argument
807 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) in ufs_qcom_apply_dev_quirks()
808 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); in ufs_qcom_apply_dev_quirks()
810 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) in ufs_qcom_apply_dev_quirks()
811 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; in ufs_qcom_apply_dev_quirks()
816 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) in ufs_qcom_get_ufs_hci_version() argument
822 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
823 * @hba: host controller instance
830 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) in ufs_qcom_advertise_quirks() argument
832 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_advertise_quirks()
834 if (host->hw_ver.major == 0x2) in ufs_qcom_advertise_quirks()
835 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; in ufs_qcom_advertise_quirks()
837 if (host->hw_ver.major > 0x3) in ufs_qcom_advertise_quirks()
838 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_advertise_quirks()
843 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_set_phy_gear()
846 host->phy_gear = host_params->hs_tx_gear; in ufs_qcom_set_phy_gear()
848 if (host->hw_ver.major < 0x4) { in ufs_qcom_set_phy_gear()
856 host->phy_gear = UFS_HS_G2; in ufs_qcom_set_phy_gear()
857 } else if (host->hw_ver.major >= 0x5) { in ufs_qcom_set_phy_gear()
858 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); in ufs_qcom_set_phy_gear()
867 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_set_phy_gear()
870 * For UFS 3.1 device and older, power up the PHY using HS-G4 in ufs_qcom_set_phy_gear()
874 host->phy_gear = UFS_HS_G4; in ufs_qcom_set_phy_gear()
878 static void ufs_qcom_set_host_params(struct ufs_hba *hba) in ufs_qcom_set_host_params() argument
880 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_set_host_params()
881 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_set_host_params()
886 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); in ufs_qcom_set_host_params()
889 static void ufs_qcom_set_caps(struct ufs_hba *hba) in ufs_qcom_set_caps() argument
891 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in ufs_qcom_set_caps()
892 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; in ufs_qcom_set_caps()
893 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; in ufs_qcom_set_caps()
894 hba->caps |= UFSHCD_CAP_WB_EN; in ufs_qcom_set_caps()
895 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; in ufs_qcom_set_caps()
896 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; in ufs_qcom_set_caps()
900 * ufs_qcom_setup_clocks - enables/disable clocks
901 * @hba: host controller instance
905 * Return: 0 on success, non-zero on failure.
907 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, in ufs_qcom_setup_clocks() argument
910 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_setup_clocks()
925 if (!ufs_qcom_is_link_active(hba)) { in ufs_qcom_setup_clocks()
934 if (ufshcd_is_hs_mode(&hba->pwr_info)) in ufs_qcom_setup_clocks()
951 ufs_qcom_assert_reset(host->hba); in ufs_qcom_reset_assert()
962 ufs_qcom_deassert_reset(host->hba); in ufs_qcom_reset_deassert()
979 struct device *dev = host->hba->dev; in ufs_qcom_icc_init()
982 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); in ufs_qcom_icc_init()
983 if (IS_ERR(host->icc_ddr)) in ufs_qcom_icc_init()
984 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), in ufs_qcom_icc_init()
987 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); in ufs_qcom_icc_init()
988 if (IS_ERR(host->icc_cpu)) in ufs_qcom_icc_init()
989 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), in ufs_qcom_icc_init()
1006 * ufs_qcom_init - bind phy with controller
1007 * @hba: host controller instance
1012 * Return: -EPROBE_DEFER if binding fails, returns negative error
1015 static int ufs_qcom_init(struct ufs_hba *hba) in ufs_qcom_init() argument
1018 struct device *dev = hba->dev; in ufs_qcom_init()
1024 return -ENOMEM; in ufs_qcom_init()
1026 /* Make a two way bind between the qcom host and the hba */ in ufs_qcom_init()
1027 host->hba = hba; in ufs_qcom_init()
1028 ufshcd_set_variant(hba, host); in ufs_qcom_init()
1031 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); in ufs_qcom_init()
1032 if (IS_ERR(host->core_reset)) { in ufs_qcom_init()
1033 err = dev_err_probe(dev, PTR_ERR(host->core_reset), in ufs_qcom_init()
1038 /* Fire up the reset controller. Failure here is non-fatal. */ in ufs_qcom_init()
1039 host->rcdev.of_node = dev->of_node; in ufs_qcom_init()
1040 host->rcdev.ops = &ufs_qcom_reset_ops; in ufs_qcom_init()
1041 host->rcdev.owner = dev->driver->owner; in ufs_qcom_init()
1042 host->rcdev.nr_resets = 1; in ufs_qcom_init()
1043 err = devm_reset_controller_register(dev, &host->rcdev); in ufs_qcom_init()
1048 host->generic_phy = devm_phy_get(dev, "ufsphy"); in ufs_qcom_init()
1049 if (IS_ERR(host->generic_phy)) { in ufs_qcom_init()
1050 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); in ufs_qcom_init()
1059 host->device_reset = devm_gpiod_get_optional(dev, "reset", in ufs_qcom_init()
1061 if (IS_ERR(host->device_reset)) { in ufs_qcom_init()
1062 err = dev_err_probe(dev, PTR_ERR(host->device_reset), in ufs_qcom_init()
1067 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, in ufs_qcom_init()
1068 &host->hw_ver.minor, &host->hw_ver.step); in ufs_qcom_init()
1070 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; in ufs_qcom_init()
1071 host->dev_ref_clk_en_mask = BIT(26); in ufs_qcom_init()
1073 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_init()
1074 if (!strcmp(clki->name, "core_clk_unipro")) in ufs_qcom_init()
1075 clki->keep_link_active = true; in ufs_qcom_init()
1082 ufs_qcom_set_caps(hba); in ufs_qcom_init()
1083 ufs_qcom_advertise_quirks(hba); in ufs_qcom_init()
1084 ufs_qcom_set_host_params(hba); in ufs_qcom_init()
1091 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); in ufs_qcom_init()
1096 /* Failure is non-fatal */ in ufs_qcom_init()
1103 ufshcd_set_variant(hba, NULL); in ufs_qcom_init()
1108 static void ufs_qcom_exit(struct ufs_hba *hba) in ufs_qcom_exit() argument
1110 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_exit()
1113 phy_power_off(host->generic_phy); in ufs_qcom_exit()
1114 phy_exit(host->generic_phy); in ufs_qcom_exit()
1118 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1120 * @hba: host controller instance
1126 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, in ufs_qcom_set_clk_40ns_cycles() argument
1129 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_set_clk_40ns_cycles()
1139 if (host->hw_ver.major < 4) in ufs_qcom_set_clk_40ns_cycles()
1173 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", in ufs_qcom_set_clk_40ns_cycles()
1175 return -EINVAL; in ufs_qcom_set_clk_40ns_cycles()
1178 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); in ufs_qcom_set_clk_40ns_cycles()
1185 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); in ufs_qcom_set_clk_40ns_cycles()
1188 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) in ufs_qcom_set_core_clk_ctrl() argument
1190 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_set_core_clk_ctrl()
1191 struct list_head *head = &hba->clk_list_head; in ufs_qcom_set_core_clk_ctrl()
1198 if (!IS_ERR_OR_NULL(clki->clk) && in ufs_qcom_set_core_clk_ctrl()
1199 !strcmp(clki->name, "core_clk_unipro")) { in ufs_qcom_set_core_clk_ctrl()
1201 cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); in ufs_qcom_set_core_clk_ctrl()
1203 cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000)); in ufs_qcom_set_core_clk_ctrl()
1208 err = ufshcd_dme_get(hba, in ufs_qcom_set_core_clk_ctrl()
1215 if (host->hw_ver.major >= 4) { in ufs_qcom_set_core_clk_ctrl()
1217 return -ERANGE; in ufs_qcom_set_core_clk_ctrl()
1222 return -ERANGE; in ufs_qcom_set_core_clk_ctrl()
1230 err = ufshcd_dme_set(hba, in ufs_qcom_set_core_clk_ctrl()
1237 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); in ufs_qcom_set_core_clk_ctrl()
1240 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) in ufs_qcom_clk_scale_up_pre_change() argument
1242 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_clk_scale_up_pre_change()
1243 struct ufs_pa_layer_attr *attr = &host->dev_req_params; in ufs_qcom_clk_scale_up_pre_change()
1246 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, in ufs_qcom_clk_scale_up_pre_change()
1247 attr->hs_rate, false, true); in ufs_qcom_clk_scale_up_pre_change()
1249 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); in ufs_qcom_clk_scale_up_pre_change()
1253 return ufs_qcom_set_core_clk_ctrl(hba, true); in ufs_qcom_clk_scale_up_pre_change()
1256 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) in ufs_qcom_clk_scale_up_post_change() argument
1261 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) in ufs_qcom_clk_scale_down_pre_change() argument
1266 err = ufshcd_dme_get(hba, in ufs_qcom_clk_scale_down_pre_change()
1274 err = ufshcd_dme_set(hba, in ufs_qcom_clk_scale_down_pre_change()
1282 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) in ufs_qcom_clk_scale_down_post_change() argument
1285 return ufs_qcom_set_core_clk_ctrl(hba, false); in ufs_qcom_clk_scale_down_post_change()
1288 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, in ufs_qcom_clk_scale_notify() argument
1291 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_clk_scale_notify()
1295 if (!ufshcd_is_hba_active(hba)) in ufs_qcom_clk_scale_notify()
1299 err = ufshcd_uic_hibern8_enter(hba); in ufs_qcom_clk_scale_notify()
1303 err = ufs_qcom_clk_scale_up_pre_change(hba); in ufs_qcom_clk_scale_notify()
1305 err = ufs_qcom_clk_scale_down_pre_change(hba); in ufs_qcom_clk_scale_notify()
1308 ufshcd_uic_hibern8_exit(hba); in ufs_qcom_clk_scale_notify()
1313 err = ufs_qcom_clk_scale_up_post_change(hba); in ufs_qcom_clk_scale_notify()
1315 err = ufs_qcom_clk_scale_down_post_change(hba); in ufs_qcom_clk_scale_notify()
1319 ufshcd_uic_hibern8_exit(hba); in ufs_qcom_clk_scale_notify()
1324 ufshcd_uic_hibern8_exit(hba); in ufs_qcom_clk_scale_notify()
1332 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, in ufs_qcom_enable_test_bus()
1334 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); in ufs_qcom_enable_test_bus()
1340 host->testbus.select_major = TSTBUS_UNIPRO; in ufs_qcom_get_default_testbus_cfg()
1341 host->testbus.select_minor = 37; in ufs_qcom_get_default_testbus_cfg()
1346 if (host->testbus.select_major >= TSTBUS_MAX) { in ufs_qcom_testbus_cfg_is_ok()
1347 dev_err(host->hba->dev, in ufs_qcom_testbus_cfg_is_ok()
1349 __func__, host->testbus.select_major); in ufs_qcom_testbus_cfg_is_ok()
1363 return -EINVAL; in ufs_qcom_testbus_config()
1366 return -EPERM; in ufs_qcom_testbus_config()
1368 switch (host->testbus.select_major) { in ufs_qcom_testbus_config()
1425 ufshcd_rmwl(host->hba, TEST_BUS_SEL, in ufs_qcom_testbus_config()
1426 (u32)host->testbus.select_major << 19, in ufs_qcom_testbus_config()
1428 ufshcd_rmwl(host->hba, mask, in ufs_qcom_testbus_config()
1429 (u32)host->testbus.select_minor << offset, in ufs_qcom_testbus_config()
1441 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) in ufs_qcom_dump_dbg_regs() argument
1446 host = ufshcd_get_variant(hba); in ufs_qcom_dump_dbg_regs()
1448 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, in ufs_qcom_dump_dbg_regs()
1452 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); in ufs_qcom_dump_dbg_regs()
1454 reg = ufshcd_readl(hba, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
1456 ufshcd_writel(hba, reg, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
1459 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); in ufs_qcom_dump_dbg_regs()
1462 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); in ufs_qcom_dump_dbg_regs()
1465 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); in ufs_qcom_dump_dbg_regs()
1467 /* clear bit 17 - UTP_DBG_RAMS_EN */ in ufs_qcom_dump_dbg_regs()
1468 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
1471 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); in ufs_qcom_dump_dbg_regs()
1474 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); in ufs_qcom_dump_dbg_regs()
1477 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); in ufs_qcom_dump_dbg_regs()
1480 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); in ufs_qcom_dump_dbg_regs()
1483 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); in ufs_qcom_dump_dbg_regs()
1486 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); in ufs_qcom_dump_dbg_regs()
1489 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); in ufs_qcom_dump_dbg_regs()
1493 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1494 * @hba: per-adapter instance
1498 static int ufs_qcom_device_reset(struct ufs_hba *hba) in ufs_qcom_device_reset() argument
1500 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_device_reset()
1503 if (!host->device_reset) in ufs_qcom_device_reset()
1504 return -EOPNOTSUPP; in ufs_qcom_device_reset()
1510 ufs_qcom_device_reset_ctrl(hba, true); in ufs_qcom_device_reset()
1513 ufs_qcom_device_reset_ctrl(hba, false); in ufs_qcom_device_reset()
1520 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, in ufs_qcom_config_scaling_param() argument
1524 p->polling_ms = 60; in ufs_qcom_config_scaling_param()
1525 p->timer = DEVFREQ_TIMER_DELAYED; in ufs_qcom_config_scaling_param()
1526 d->upthreshold = 70; in ufs_qcom_config_scaling_param()
1527 d->downdifferential = 5; in ufs_qcom_config_scaling_param()
1530 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, in ufs_qcom_config_scaling_param() argument
1537 static void ufs_qcom_reinit_notify(struct ufs_hba *hba) in ufs_qcom_reinit_notify() argument
1539 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_reinit_notify()
1541 phy_power_off(host->generic_phy); in ufs_qcom_reinit_notify()
1560 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) in ufs_qcom_mcq_config_resource() argument
1562 struct platform_device *pdev = to_platform_device(hba->dev); in ufs_qcom_mcq_config_resource()
1567 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); in ufs_qcom_mcq_config_resource()
1570 res = &hba->res[i]; in ufs_qcom_mcq_config_resource()
1571 res->resource = platform_get_resource_byname(pdev, in ufs_qcom_mcq_config_resource()
1573 res->name); in ufs_qcom_mcq_config_resource()
1574 if (!res->resource) { in ufs_qcom_mcq_config_resource()
1575 dev_info(hba->dev, "Resource %s not provided\n", res->name); in ufs_qcom_mcq_config_resource()
1577 return -ENODEV; in ufs_qcom_mcq_config_resource()
1580 res_mem = res->resource; in ufs_qcom_mcq_config_resource()
1581 res->base = hba->mmio_base; in ufs_qcom_mcq_config_resource()
1585 res->base = devm_ioremap_resource(hba->dev, res->resource); in ufs_qcom_mcq_config_resource()
1586 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1587 dev_err(hba->dev, "Failed to map res %s, err=%d\n", in ufs_qcom_mcq_config_resource()
1588 res->name, (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1589 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1590 res->base = NULL; in ufs_qcom_mcq_config_resource()
1596 res = &hba->res[RES_MCQ]; in ufs_qcom_mcq_config_resource()
1598 if (res->base) in ufs_qcom_mcq_config_resource()
1602 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); in ufs_qcom_mcq_config_resource()
1604 return -ENOMEM; in ufs_qcom_mcq_config_resource()
1606 res_mcq->start = res_mem->start + in ufs_qcom_mcq_config_resource()
1607 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); in ufs_qcom_mcq_config_resource()
1608 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; in ufs_qcom_mcq_config_resource()
1609 res_mcq->flags = res_mem->flags; in ufs_qcom_mcq_config_resource()
1610 res_mcq->name = "mcq"; in ufs_qcom_mcq_config_resource()
1614 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", in ufs_qcom_mcq_config_resource()
1619 res->base = devm_ioremap_resource(hba->dev, res_mcq); in ufs_qcom_mcq_config_resource()
1620 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1621 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", in ufs_qcom_mcq_config_resource()
1622 (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1623 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1628 hba->mcq_base = res->base; in ufs_qcom_mcq_config_resource()
1631 res->base = NULL; in ufs_qcom_mcq_config_resource()
1636 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) in ufs_qcom_op_runtime_config() argument
1642 mem_res = &hba->res[RES_UFS]; in ufs_qcom_op_runtime_config()
1643 sqdao_res = &hba->res[RES_MCQ_SQD]; in ufs_qcom_op_runtime_config()
1645 if (!mem_res->base || !sqdao_res->base) in ufs_qcom_op_runtime_config()
1646 return -EINVAL; in ufs_qcom_op_runtime_config()
1649 opr = &hba->mcq_opr[i]; in ufs_qcom_op_runtime_config()
1650 opr->offset = sqdao_res->resource->start - in ufs_qcom_op_runtime_config()
1651 mem_res->resource->start + 0x40 * i; in ufs_qcom_op_runtime_config()
1652 opr->stride = 0x100; in ufs_qcom_op_runtime_config()
1653 opr->base = sqdao_res->base + 0x40 * i; in ufs_qcom_op_runtime_config()
1659 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) in ufs_qcom_get_hba_mac() argument
1665 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, in ufs_qcom_get_outstanding_cqs() argument
1668 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; in ufs_qcom_get_outstanding_cqs()
1670 if (!mcq_vs_res->base) in ufs_qcom_get_outstanding_cqs()
1671 return -EINVAL; in ufs_qcom_get_outstanding_cqs()
1673 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); in ufs_qcom_get_outstanding_cqs()
1681 struct ufs_hba *hba = dev_get_drvdata(dev); in ufs_qcom_write_msi_msg() local
1683 ufshcd_mcq_config_esi(hba, msg); in ufs_qcom_write_msi_msg()
1690 struct ufs_hba *hba = dev_get_drvdata(dev); in ufs_qcom_mcq_esi_handler() local
1691 u32 id = desc->msi_index; in ufs_qcom_mcq_esi_handler()
1692 struct ufs_hw_queue *hwq = &hba->uhq[id]; in ufs_qcom_mcq_esi_handler()
1694 ufshcd_mcq_write_cqis(hba, 0x1, id); in ufs_qcom_mcq_esi_handler()
1695 ufshcd_mcq_poll_cqe_lock(hba, hwq); in ufs_qcom_mcq_esi_handler()
1700 static int ufs_qcom_config_esi(struct ufs_hba *hba) in ufs_qcom_config_esi() argument
1702 struct ufs_qcom_host *host = ufshcd_get_variant(hba); in ufs_qcom_config_esi()
1707 if (host->esi_enabled) in ufs_qcom_config_esi()
1714 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; in ufs_qcom_config_esi()
1715 ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, in ufs_qcom_config_esi()
1718 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); in ufs_qcom_config_esi()
1722 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1723 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1724 ret = devm_request_irq(hba->dev, desc->irq, in ufs_qcom_config_esi()
1726 IRQF_SHARED, "qcom-mcq-esi", desc); in ufs_qcom_config_esi()
1728 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", in ufs_qcom_config_esi()
1729 __func__, desc->irq, ret); in ufs_qcom_config_esi()
1734 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1738 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1739 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1742 devm_free_irq(hba->dev, desc->irq, hba); in ufs_qcom_config_esi()
1744 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1745 platform_msi_domain_free_irqs(hba->dev); in ufs_qcom_config_esi()
1747 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && in ufs_qcom_config_esi()
1748 host->hw_ver.step == 0) in ufs_qcom_config_esi()
1749 ufshcd_rmwl(hba, ESI_VEC_MASK, in ufs_qcom_config_esi()
1750 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), in ufs_qcom_config_esi()
1752 ufshcd_mcq_enable_esi(hba); in ufs_qcom_config_esi()
1753 host->esi_enabled = true; in ufs_qcom_config_esi()
1760 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1791 * ufs_qcom_probe - probe routine of the driver
1794 * Return: zero for success and non-zero for failure.
1799 struct device *dev = &pdev->dev; in ufs_qcom_probe()
1810 * ufs_qcom_remove - set driver_data of the device to NULL
1817 struct ufs_hba *hba = platform_get_drvdata(pdev); in ufs_qcom_remove() local
1819 pm_runtime_get_sync(&(pdev)->dev); in ufs_qcom_remove()
1820 ufshcd_remove(hba); in ufs_qcom_remove()
1821 platform_msi_domain_free_irqs(hba->dev); in ufs_qcom_remove()
1855 .name = "ufshcd-qcom",