Lines Matching full:ufs
3 * UFS Host Controller driver for Exynos specific extensions
21 #include <ufs/ufshcd.h>
23 #include <ufs/ufshci.h>
24 #include <ufs/unipro.h>
26 #include "ufs-exynos.h"
82 /* FSYS UFS Shareability */
144 * UFS Protector registers
155 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en);
156 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en);
158 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs) in exynos_ufs_enable_auto_ctrl_hcc() argument
160 exynos_ufs_auto_ctrl_hcc(ufs, true); in exynos_ufs_enable_auto_ctrl_hcc()
163 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs) in exynos_ufs_disable_auto_ctrl_hcc() argument
165 exynos_ufs_auto_ctrl_hcc(ufs, false); in exynos_ufs_disable_auto_ctrl_hcc()
169 struct exynos_ufs *ufs, u32 *val) in exynos_ufs_disable_auto_ctrl_hcc_save() argument
171 *val = hci_readl(ufs, HCI_MISC); in exynos_ufs_disable_auto_ctrl_hcc_save()
172 exynos_ufs_auto_ctrl_hcc(ufs, false); in exynos_ufs_disable_auto_ctrl_hcc_save()
176 struct exynos_ufs *ufs, u32 *val) in exynos_ufs_auto_ctrl_hcc_restore() argument
178 hci_writel(ufs, *val, HCI_MISC); in exynos_ufs_auto_ctrl_hcc_restore()
181 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs) in exynos_ufs_gate_clks() argument
183 exynos_ufs_ctrl_clkstop(ufs, true); in exynos_ufs_gate_clks()
186 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs) in exynos_ufs_ungate_clks() argument
188 exynos_ufs_ctrl_clkstop(ufs, false); in exynos_ufs_ungate_clks()
191 static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) in exynos7_ufs_drv_init() argument
196 static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) in exynosauto_ufs_drv_init() argument
198 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynosauto_ufs_drv_init()
201 if (ufs->sysreg) { in exynosauto_ufs_drv_init()
202 return regmap_update_bits(ufs->sysreg, in exynosauto_ufs_drv_init()
203 ufs->shareability_reg_offset, in exynosauto_ufs_drv_init()
212 static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs) in exynosauto_ufs_post_hce_enable() argument
214 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_hce_enable()
219 hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH); in exynosauto_ufs_post_hce_enable()
221 hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG); in exynosauto_ufs_post_hce_enable()
226 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs) in exynosauto_ufs_pre_link() argument
228 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_link()
232 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
233 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
236 for_each_ufs_rx_lane(ufs, i) { in exynosauto_ufs_pre_link()
238 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
253 for_each_ufs_tx_lane(ufs, i) { in exynosauto_ufs_pre_link()
255 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
280 static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs, in exynosauto_ufs_pre_pwr_change() argument
283 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_pwr_change()
293 static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs, in exynosauto_ufs_post_pwr_change() argument
296 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_pwr_change()
307 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs) in exynos7_ufs_pre_link() argument
309 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_pre_link()
310 u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite; in exynos7_ufs_pre_link()
314 for_each_ufs_tx_lane(ufs, i) in exynos7_ufs_pre_link()
316 for_each_ufs_rx_lane(ufs, i) { in exynos7_ufs_pre_link()
322 for_each_ufs_tx_lane(ufs, i) in exynos7_ufs_pre_link()
337 static int exynos7_ufs_post_link(struct exynos_ufs *ufs) in exynos7_ufs_post_link() argument
339 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_link()
343 for_each_ufs_tx_lane(ufs, i) { in exynos7_ufs_post_link()
347 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000))); in exynos7_ufs_post_link()
358 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs, in exynos7_ufs_pre_pwr_change() argument
361 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE); in exynos7_ufs_pre_pwr_change()
366 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs, in exynos7_ufs_post_pwr_change() argument
369 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_pwr_change()
387 * - Access to UFS protector's register
389 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en) in exynos_ufs_auto_ctrl_hcc() argument
391 u32 misc = hci_readl(ufs, HCI_MISC); in exynos_ufs_auto_ctrl_hcc()
394 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC); in exynos_ufs_auto_ctrl_hcc()
396 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC); in exynos_ufs_auto_ctrl_hcc()
399 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en) in exynos_ufs_ctrl_clkstop() argument
401 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL); in exynos_ufs_ctrl_clkstop()
402 u32 misc = hci_readl(ufs, HCI_MISC); in exynos_ufs_ctrl_clkstop()
405 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC); in exynos_ufs_ctrl_clkstop()
406 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL); in exynos_ufs_ctrl_clkstop()
408 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL); in exynos_ufs_ctrl_clkstop()
409 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC); in exynos_ufs_ctrl_clkstop()
413 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs) in exynos_ufs_get_clk_info() argument
415 struct ufs_hba *hba = ufs->hba; in exynos_ufs_get_clk_info()
429 ufs->clk_hci_core = clki->clk; in exynos_ufs_get_clk_info()
431 ufs->clk_unipro_main = clki->clk; in exynos_ufs_get_clk_info()
435 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) { in exynos_ufs_get_clk_info()
441 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main); in exynos_ufs_get_clk_info()
442 pclk_rate = clk_get_rate(ufs->clk_hci_core); in exynos_ufs_get_clk_info()
443 f_min = ufs->pclk_avail_min; in exynos_ufs_get_clk_info()
444 f_max = ufs->pclk_avail_max; in exynos_ufs_get_clk_info()
446 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_get_clk_info()
462 ufs->pclk_rate = pclk_rate; in exynos_ufs_get_clk_info()
463 ufs->pclk_div = div; in exynos_ufs_get_clk_info()
469 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs) in exynos_ufs_set_unipro_pclk_div() argument
471 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_set_unipro_pclk_div()
474 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL); in exynos_ufs_set_unipro_pclk_div()
475 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div), in exynos_ufs_set_unipro_pclk_div()
480 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs) in exynos_ufs_set_pwm_clk_div() argument
482 struct ufs_hba *hba = ufs->hba; in exynos_ufs_set_pwm_clk_div()
483 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_set_pwm_clk_div()
489 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs) in exynos_ufs_calc_pwm_clk_div() argument
491 struct ufs_hba *hba = ufs->hba; in exynos_ufs_calc_pwm_clk_div()
492 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_calc_pwm_clk_div()
500 clk_period = UNIPRO_PCLK_PERIOD(ufs); in exynos_ufs_calc_pwm_clk_div()
520 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period) in exynos_ufs_calc_time_cntr() argument
523 long pclk_rate = ufs->pclk_rate; in exynos_ufs_calc_time_cntr()
526 clk_period = UNIPRO_PCLK_PERIOD(ufs); in exynos_ufs_calc_time_cntr()
532 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs) in exynos_ufs_specify_phy_time_attr() argument
534 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_specify_phy_time_attr()
535 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_specify_phy_time_attr()
538 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
540 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); in exynos_ufs_specify_phy_time_attr()
542 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); in exynos_ufs_specify_phy_time_attr()
544 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
546 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
548 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
551 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
553 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); in exynos_ufs_specify_phy_time_attr()
555 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
557 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
559 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
561 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt); in exynos_ufs_specify_phy_time_attr()
564 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs) in exynos_ufs_config_phy_time_attr() argument
566 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_time_attr()
567 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_config_phy_time_attr()
570 exynos_ufs_set_pwm_clk_div(ufs); in exynos_ufs_config_phy_time_attr()
574 for_each_ufs_rx_lane(ufs, i) { in exynos_ufs_config_phy_time_attr()
576 ufs->drv_data->uic_attr->rx_filler_enable); in exynos_ufs_config_phy_time_attr()
593 for_each_ufs_tx_lane(ufs, i) { in exynos_ufs_config_phy_time_attr()
612 ufs->drv_data->uic_attr->tx_min_activatetime); in exynos_ufs_config_phy_time_attr()
618 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs) in exynos_ufs_config_phy_cap_attr() argument
620 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_cap_attr()
621 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_config_phy_cap_attr()
626 for_each_ufs_rx_lane(ufs, i) { in exynos_ufs_config_phy_cap_attr()
648 for_each_ufs_rx_lane(ufs, i) { in exynos_ufs_config_phy_cap_attr()
664 for_each_ufs_rx_lane(ufs, i) { in exynos_ufs_config_phy_cap_attr()
688 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs) in exynos_ufs_establish_connt() argument
690 struct ufs_hba *hba = ufs->hba; in exynos_ufs_establish_connt()
711 static void exynos_ufs_config_smu(struct exynos_ufs *ufs) in exynos_ufs_config_smu() argument
715 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); in exynos_ufs_config_smu()
718 reg = ufsp_readl(ufs, UFSPRSECURITY); in exynos_ufs_config_smu()
719 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY); in exynos_ufs_config_smu()
720 ufsp_writel(ufs, 0x0, UFSPSBEGIN0); in exynos_ufs_config_smu()
721 ufsp_writel(ufs, 0xffffffff, UFSPSEND0); in exynos_ufs_config_smu()
722 ufsp_writel(ufs, 0xff, UFSPSLUN0); in exynos_ufs_config_smu()
723 ufsp_writel(ufs, 0xf1, UFSPSCTRL0); in exynos_ufs_config_smu()
725 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); in exynos_ufs_config_smu()
728 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs, in exynos_ufs_config_sync_pattern_mask() argument
731 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_sync_pattern_mask()
750 mask = exynos_ufs_calc_time_cntr(ufs, sync_len); in exynos_ufs_config_sync_pattern_mask()
755 for_each_ufs_rx_lane(ufs, i) in exynos_ufs_config_sync_pattern_mask()
766 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_pwr_mode() local
767 struct phy *generic_phy = ufs->phy; in exynos_ufs_pre_pwr_mode()
785 if (ufs->drv_data->pre_pwr_change) in exynos_ufs_pre_pwr_mode()
786 ufs->drv_data->pre_pwr_change(ufs, dev_req_params); in exynos_ufs_pre_pwr_mode()
789 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params); in exynos_ufs_pre_pwr_mode()
813 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_pwr_mode() local
814 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_pwr_mode()
826 if (ufs->drv_data->post_pwr_change) in exynos_ufs_post_pwr_mode()
827 ufs->drv_data->post_pwr_change(ufs, pwr_req); in exynos_ufs_post_pwr_mode()
853 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_xfer_req() local
856 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_xfer_req()
859 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_xfer_req()
861 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_xfer_req()
867 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_tm_req() local
870 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_tm_req()
875 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_tm_req()
881 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_specify_nexus_t_tm_req()
886 static int exynos_ufs_phy_init(struct exynos_ufs *ufs) in exynos_ufs_phy_init() argument
888 struct ufs_hba *hba = ufs->hba; in exynos_ufs_phy_init()
889 struct phy *generic_phy = ufs->phy; in exynos_ufs_phy_init()
892 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) { in exynos_ufs_phy_init()
894 &ufs->avail_ln_rx); in exynos_ufs_phy_init()
896 &ufs->avail_ln_tx); in exynos_ufs_phy_init()
897 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx, in exynos_ufs_phy_init()
899 ufs->avail_ln_rx, ufs->avail_ln_tx); in exynos_ufs_phy_init()
902 phy_set_bus_width(generic_phy, ufs->avail_ln_rx); in exynos_ufs_phy_init()
922 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs) in exynos_ufs_config_unipro() argument
924 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_unipro()
927 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynos_ufs_config_unipro()
929 ufs->drv_data->uic_attr->tx_trailingclks); in exynos_ufs_config_unipro()
931 ufs->drv_data->uic_attr->pa_dbg_option_suite); in exynos_ufs_config_unipro()
934 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index) in exynos_ufs_config_intr() argument
938 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER); in exynos_ufs_config_intr()
941 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER); in exynos_ufs_config_intr()
944 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER); in exynos_ufs_config_intr()
947 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER); in exynos_ufs_config_intr()
950 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER); in exynos_ufs_config_intr()
958 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_setup_clocks() local
960 if (!ufs) in exynos_ufs_setup_clocks()
964 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
965 exynos_ufs_disable_auto_ctrl_hcc(ufs); in exynos_ufs_setup_clocks()
966 exynos_ufs_ungate_clks(ufs); in exynos_ufs_setup_clocks()
968 exynos_ufs_gate_clks(ufs); in exynos_ufs_setup_clocks()
969 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
970 exynos_ufs_enable_auto_ctrl_hcc(ufs); in exynos_ufs_setup_clocks()
978 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_link() local
981 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2); in exynos_ufs_pre_link()
982 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3); in exynos_ufs_pre_link()
983 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4); in exynos_ufs_pre_link()
984 exynos_ufs_set_unipro_pclk_div(ufs); in exynos_ufs_pre_link()
987 exynos_ufs_config_unipro(ufs); in exynos_ufs_pre_link()
990 exynos_ufs_phy_init(ufs); in exynos_ufs_pre_link()
991 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { in exynos_ufs_pre_link()
992 exynos_ufs_config_phy_time_attr(ufs); in exynos_ufs_pre_link()
993 exynos_ufs_config_phy_cap_attr(ufs); in exynos_ufs_pre_link()
998 if (ufs->drv_data->pre_link) in exynos_ufs_pre_link()
999 ufs->drv_data->pre_link(ufs); in exynos_ufs_pre_link()
1004 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs) in exynos_ufs_fit_aggr_timeout() argument
1008 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL); in exynos_ufs_fit_aggr_timeout()
1009 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL); in exynos_ufs_fit_aggr_timeout()
1014 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_link() local
1015 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_link()
1016 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_post_link()
1018 exynos_ufs_establish_connt(ufs); in exynos_ufs_post_link()
1019 exynos_ufs_fit_aggr_timeout(ufs); in exynos_ufs_post_link()
1021 hci_writel(ufs, 0xa, HCI_DATA_REORDER); in exynos_ufs_post_link()
1022 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_TXPRDT_ENTRY_SIZE); in exynos_ufs_post_link()
1023 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_RXPRDT_ENTRY_SIZE); in exynos_ufs_post_link()
1024 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_post_link()
1025 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_post_link()
1026 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN); in exynos_ufs_post_link()
1028 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) in exynos_ufs_post_link()
1042 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER)) in exynos_ufs_post_link()
1047 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_post_link()
1071 if (ufs->drv_data->post_link) in exynos_ufs_post_link()
1072 ufs->drv_data->post_link(ufs); in exynos_ufs_post_link()
1077 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs) in exynos_ufs_parse_dt() argument
1083 ufs->drv_data = device_get_match_data(dev); in exynos_ufs_parse_dt()
1085 if (ufs->drv_data && ufs->drv_data->uic_attr) { in exynos_ufs_parse_dt()
1086 attr = ufs->drv_data->uic_attr; in exynos_ufs_parse_dt()
1093 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); in exynos_ufs_parse_dt()
1094 if (IS_ERR(ufs->sysreg)) in exynos_ufs_parse_dt()
1095 ufs->sysreg = NULL; in exynos_ufs_parse_dt()
1098 &ufs->shareability_reg_offset)) { in exynos_ufs_parse_dt()
1100 ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET; in exynos_ufs_parse_dt()
1104 ufs->pclk_avail_min = PCLK_AVAIL_MIN; in exynos_ufs_parse_dt()
1105 ufs->pclk_avail_max = PCLK_AVAIL_MAX; in exynos_ufs_parse_dt()
1119 struct exynos_ufs *ufs) in exynos_ufs_priv_init() argument
1121 ufs->hba = hba; in exynos_ufs_priv_init()
1122 ufs->opts = ufs->drv_data->opts; in exynos_ufs_priv_init()
1123 ufs->rx_sel_idx = PA_MAXDATALANES; in exynos_ufs_priv_init()
1124 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX) in exynos_ufs_priv_init()
1125 ufs->rx_sel_idx = 0; in exynos_ufs_priv_init()
1126 hba->priv = (void *)ufs; in exynos_ufs_priv_init()
1127 hba->quirks = ufs->drv_data->quirks; in exynos_ufs_priv_init()
1134 struct exynos_ufs *ufs; in exynos_ufs_init() local
1137 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); in exynos_ufs_init()
1138 if (!ufs) in exynos_ufs_init()
1142 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynos_ufs_init()
1143 if (IS_ERR(ufs->reg_hci)) { in exynos_ufs_init()
1145 return PTR_ERR(ufs->reg_hci); in exynos_ufs_init()
1149 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro"); in exynos_ufs_init()
1150 if (IS_ERR(ufs->reg_unipro)) { in exynos_ufs_init()
1152 return PTR_ERR(ufs->reg_unipro); in exynos_ufs_init()
1155 /* ufs protector */ in exynos_ufs_init()
1156 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp"); in exynos_ufs_init()
1157 if (IS_ERR(ufs->reg_ufsp)) { in exynos_ufs_init()
1158 dev_err(dev, "cannot ioremap for ufs protector register\n"); in exynos_ufs_init()
1159 return PTR_ERR(ufs->reg_ufsp); in exynos_ufs_init()
1162 ret = exynos_ufs_parse_dt(dev, ufs); in exynos_ufs_init()
1168 ufs->phy = devm_phy_get(dev, "ufs-phy"); in exynos_ufs_init()
1169 if (IS_ERR(ufs->phy)) { in exynos_ufs_init()
1170 ret = PTR_ERR(ufs->phy); in exynos_ufs_init()
1171 dev_err(dev, "failed to get ufs-phy\n"); in exynos_ufs_init()
1175 exynos_ufs_priv_init(hba, ufs); in exynos_ufs_init()
1177 if (ufs->drv_data->drv_init) { in exynos_ufs_init()
1178 ret = ufs->drv_data->drv_init(dev, ufs); in exynos_ufs_init()
1185 ret = exynos_ufs_get_clk_info(ufs); in exynos_ufs_init()
1188 exynos_ufs_specify_phy_time_attr(ufs); in exynos_ufs_init()
1189 exynos_ufs_config_smu(ufs); in exynos_ufs_init()
1199 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_host_reset() local
1204 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val); in exynos_ufs_host_reset()
1206 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST); in exynos_ufs_host_reset()
1209 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK)) in exynos_ufs_host_reset()
1217 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val); in exynos_ufs_host_reset()
1223 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_dev_hw_reset() local
1225 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT); in exynos_ufs_dev_hw_reset()
1227 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT); in exynos_ufs_dev_hw_reset()
1232 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_hibern8() local
1233 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_pre_hibern8()
1236 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_pre_hibern8()
1237 exynos_ufs_disable_auto_ctrl_hcc(ufs); in exynos_ufs_pre_hibern8()
1238 exynos_ufs_ungate_clks(ufs); in exynos_ufs_pre_hibern8()
1240 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_pre_hibern8()
1251 ufs->entry_hibern8_t); in exynos_ufs_pre_hibern8()
1265 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_hibern8() local
1271 if (ufshcd_is_hs_mode(&ufs->dev_req_params)) in exynos_ufs_post_hibern8()
1284 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)) in exynos_ufs_post_hibern8()
1285 exynos_ufs_establish_connt(ufs); in exynos_ufs_post_hibern8()
1287 ufs->entry_hibern8_t = ktime_get(); in exynos_ufs_post_hibern8()
1288 exynos_ufs_gate_clks(ufs); in exynos_ufs_post_hibern8()
1289 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_post_hibern8()
1290 exynos_ufs_enable_auto_ctrl_hcc(ufs); in exynos_ufs_post_hibern8()
1297 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_hce_enable_notify() local
1310 if (ufs->drv_data->pre_hce_enable) { in exynos_ufs_hce_enable_notify()
1311 ret = ufs->drv_data->pre_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1322 exynos_ufs_calc_pwm_clk_div(ufs); in exynos_ufs_hce_enable_notify()
1323 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)) in exynos_ufs_hce_enable_notify()
1324 exynos_ufs_enable_auto_ctrl_hcc(ufs); in exynos_ufs_hce_enable_notify()
1326 if (ufs->drv_data->post_hce_enable) in exynos_ufs_hce_enable_notify()
1327 ret = ufs->drv_data->post_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1389 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_suspend() local
1395 phy_power_off(ufs->phy); in exynos_ufs_suspend()
1402 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_resume() local
1405 phy_power_on(ufs->phy); in exynos_ufs_resume()
1407 exynos_ufs_config_smu(ufs); in exynos_ufs_resume()
1449 struct exynos_ufs *ufs; in exynosauto_ufs_vh_init() local
1452 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL); in exynosauto_ufs_vh_init()
1453 if (!ufs) in exynosauto_ufs_vh_init()
1457 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynosauto_ufs_vh_init()
1458 if (IS_ERR(ufs->reg_hci)) { in exynosauto_ufs_vh_init()
1460 return PTR_ERR(ufs->reg_hci); in exynosauto_ufs_vh_init()
1467 ufs->drv_data = device_get_match_data(dev); in exynosauto_ufs_vh_init()
1468 if (!ufs->drv_data) in exynosauto_ufs_vh_init()
1471 exynos_ufs_priv_init(hba, ufs); in exynosauto_ufs_vh_init()
1476 static int fsd_ufs_pre_link(struct exynos_ufs *ufs) in fsd_ufs_pre_link() argument
1479 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_link()
1482 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1486 for_each_ufs_tx_lane(ufs, i) { in fsd_ufs_pre_link()
1488 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1492 for_each_ufs_rx_lane(ufs, i) { in fsd_ufs_pre_link()
1494 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1508 exynos_ufs_establish_connt(ufs); in fsd_ufs_pre_link()
1518 static int fsd_ufs_post_link(struct exynos_ufs *ufs) in fsd_ufs_post_link() argument
1521 struct ufs_hba *hba = ufs->hba; in fsd_ufs_post_link()
1544 for_each_ufs_rx_lane(ufs, i) { in fsd_ufs_post_link()
1556 static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs, in fsd_ufs_pre_pwr_change() argument
1559 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_pwr_change()
1567 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0); in fsd_ufs_pre_pwr_change()
1568 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1); in fsd_ufs_pre_pwr_change()
1569 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2); in fsd_ufs_pre_pwr_change()
1616 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_remove() local
1621 phy_power_off(ufs->phy); in exynos_ufs_remove()
1622 phy_exit(ufs->phy); in exynos_ufs_remove()
1741 { .compatible = "samsung,exynos7-ufs",
1743 { .compatible = "samsung,exynosautov9-ufs",
1745 { .compatible = "samsung,exynosautov9-ufs-vh",
1747 { .compatible = "tesla,fsd-ufs",
1772 MODULE_DESCRIPTION("Exynos UFS HCI Driver");