Lines Matching +full:virtual +full:- +full:wire +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
12 * If Soft-UART support is needed but not already present, then this driver
13 * will request and upload the "Soft-UART" microcode upon probe. The
30 #include <linux/dma-mapping.h>
43 * but Soft-UART is a hack and we want to keep everything related to it in
46 #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
49 * soft_uart is 1 if we need to use Soft-UART mode
58 mode */
62 * Documentation/admin-guide/devices.txt. For the QE
63 * UART, we have major number 204 and minor numbers 46 - 49, which are the
70 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
88 * sent over the wire.
106 __be16 cchars[8]; /* control characters 1-8 */
122 /* The rest is for Soft-UART only */
130 u8 res14[0xBC - 0x9F]; /* reserved */
134 u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */
136 u8 res15[0xD0 - 0xC8]; /* reserved */
142 /* SUPSMR definitions, for Soft-UART only */
176 /* Private per-port data structure */
198 void *bd_virt; /* virtual address of the BD buffers */
213 * Virtual to physical address translation.
215 * Given the virtual address for a character buffer, this function returns
220 if (likely((addr >= qe_port->bd_virt)) && in cpu2qe_addr()
221 (addr < (qe_port->bd_virt + qe_port->bd_size))) in cpu2qe_addr()
222 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt); in cpu2qe_addr()
231 * Physical to virtual address translation.
234 * returns the virtual equivalent.
239 if (likely((addr >= qe_port->bd_dma_addr) && in qe2cpu_addr()
240 (addr < (qe_port->bd_dma_addr + qe_port->bd_size)))) in qe2cpu_addr()
241 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr); in qe2cpu_addr()
261 struct qe_bd __iomem *bdp = qe_port->tx_bd_base; in qe_uart_tx_empty()
264 if (ioread16be(&bdp->status) & BD_SC_READY) in qe_uart_tx_empty()
268 if (ioread16be(&bdp->status) & BD_SC_WRAP) in qe_uart_tx_empty()
314 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); in qe_uart_stop_tx()
323 * A return value of non-zero indicates that it successfully stuffed all
336 struct uart_port *port = &qe_port->port; in qe_uart_tx_pump()
337 struct circ_buf *xmit = &port->state->xmit; in qe_uart_tx_pump()
340 if (port->x_char) { in qe_uart_tx_pump()
342 bdp = qe_port->tx_cur; in qe_uart_tx_pump()
344 p = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); in qe_uart_tx_pump()
346 *p++ = port->x_char; in qe_uart_tx_pump()
347 iowrite16be(1, &bdp->length); in qe_uart_tx_pump()
348 qe_setbits_be16(&bdp->status, BD_SC_READY); in qe_uart_tx_pump()
350 if (ioread16be(&bdp->status) & BD_SC_WRAP) in qe_uart_tx_pump()
351 bdp = qe_port->tx_bd_base; in qe_uart_tx_pump()
354 qe_port->tx_cur = bdp; in qe_uart_tx_pump()
356 port->icount.tx++; in qe_uart_tx_pump()
357 port->x_char = 0; in qe_uart_tx_pump()
367 bdp = qe_port->tx_cur; in qe_uart_tx_pump()
369 while (!(ioread16be(&bdp->status) & BD_SC_READY) && !uart_circ_empty(xmit)) { in qe_uart_tx_pump()
371 p = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); in qe_uart_tx_pump()
372 while (count < qe_port->tx_fifosize) { in qe_uart_tx_pump()
373 *p++ = xmit->buf[xmit->tail]; in qe_uart_tx_pump()
380 iowrite16be(count, &bdp->length); in qe_uart_tx_pump()
381 qe_setbits_be16(&bdp->status, BD_SC_READY); in qe_uart_tx_pump()
384 if (ioread16be(&bdp->status) & BD_SC_WRAP) in qe_uart_tx_pump()
385 bdp = qe_port->tx_bd_base; in qe_uart_tx_pump()
389 qe_port->tx_cur = bdp; in qe_uart_tx_pump()
417 if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX) in qe_uart_start_tx()
422 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); in qe_uart_start_tx()
433 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); in qe_uart_stop_rx()
448 ucc_slow_stop_tx(qe_port->us_private); in qe_uart_break_ctl()
450 ucc_slow_restart_tx(qe_port->us_private); in qe_uart_break_ctl()
461 struct uart_port *port = &qe_port->port; in qe_uart_int_rx()
462 struct tty_port *tport = &port->state->port; in qe_uart_int_rx()
470 bdp = qe_port->rx_cur; in qe_uart_int_rx()
472 status = ioread16be(&bdp->status); in qe_uart_int_rx()
479 i = ioread16be(&bdp->length); in qe_uart_int_rx()
485 dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n"); in qe_uart_int_rx()
490 cp = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); in qe_uart_int_rx()
493 while (i-- > 0) { in qe_uart_int_rx()
495 port->icount.rx++; in qe_uart_int_rx()
510 qe_clrsetbits_be16(&bdp->status, in qe_uart_int_rx()
513 if (ioread16be(&bdp->status) & BD_SC_WRAP) in qe_uart_int_rx()
514 bdp = qe_port->rx_bd_base; in qe_uart_int_rx()
521 qe_port->rx_cur = bdp; in qe_uart_int_rx()
533 port->icount.brk++; in qe_uart_int_rx()
535 port->icount.parity++; in qe_uart_int_rx()
537 port->icount.frame++; in qe_uart_int_rx()
539 port->icount.overrun++; in qe_uart_int_rx()
542 status &= port->read_status_mask; in qe_uart_int_rx()
555 port->sysrq = 0; in qe_uart_int_rx()
566 struct ucc_slow __iomem *uccp = qe_port->uccp; in qe_uart_int()
570 events = ioread16be(&uccp->ucce); in qe_uart_int()
571 iowrite16be(events, &uccp->ucce); in qe_uart_int()
574 uart_handle_break(&qe_port->port); in qe_uart_int()
596 * descriptors, and the virtual address for us to work with. in qe_uart_initbd()
598 bd_virt = qe_port->bd_virt; in qe_uart_initbd()
599 bdp = qe_port->rx_bd_base; in qe_uart_initbd()
600 qe_port->rx_cur = qe_port->rx_bd_base; in qe_uart_initbd()
601 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) { in qe_uart_initbd()
602 iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status); in qe_uart_initbd()
603 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); in qe_uart_initbd()
604 iowrite16be(0, &bdp->length); in qe_uart_initbd()
605 bd_virt += qe_port->rx_fifosize; in qe_uart_initbd()
610 iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status); in qe_uart_initbd()
611 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); in qe_uart_initbd()
612 iowrite16be(0, &bdp->length); in qe_uart_initbd()
616 * virtual address for us to work with. in qe_uart_initbd()
618 bd_virt = qe_port->bd_virt + in qe_uart_initbd()
619 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); in qe_uart_initbd()
620 qe_port->tx_cur = qe_port->tx_bd_base; in qe_uart_initbd()
621 bdp = qe_port->tx_bd_base; in qe_uart_initbd()
622 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) { in qe_uart_initbd()
623 iowrite16be(BD_SC_INTRPT, &bdp->status); in qe_uart_initbd()
624 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); in qe_uart_initbd()
625 iowrite16be(0, &bdp->length); in qe_uart_initbd()
626 bd_virt += qe_port->tx_fifosize; in qe_uart_initbd()
632 qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P); in qe_uart_initbd()
635 iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status); in qe_uart_initbd()
636 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); in qe_uart_initbd()
637 iowrite16be(0, &bdp->length); in qe_uart_initbd()
645 * does all the UART-specific stuff.
650 struct ucc_slow __iomem *uccp = qe_port->uccp; in qe_uart_init_ucc()
651 struct ucc_uart_pram __iomem *uccup = qe_port->uccup; in qe_uart_init_ucc()
656 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); in qe_uart_init_ucc()
659 iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr); in qe_uart_init_ucc()
660 iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr); in qe_uart_init_ucc()
661 iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr); in qe_uart_init_ucc()
662 iowrite16be(0x10, &uccup->maxidl); in qe_uart_init_ucc()
663 iowrite16be(1, &uccup->brkcr); in qe_uart_init_ucc()
664 iowrite16be(0, &uccup->parec); in qe_uart_init_ucc()
665 iowrite16be(0, &uccup->frmec); in qe_uart_init_ucc()
666 iowrite16be(0, &uccup->nosec); in qe_uart_init_ucc()
667 iowrite16be(0, &uccup->brkec); in qe_uart_init_ucc()
668 iowrite16be(0, &uccup->uaddr[0]); in qe_uart_init_ucc()
669 iowrite16be(0, &uccup->uaddr[1]); in qe_uart_init_ucc()
670 iowrite16be(0, &uccup->toseq); in qe_uart_init_ucc()
672 iowrite16be(0xC000, &uccup->cchars[i]); in qe_uart_init_ucc()
673 iowrite16be(0xc0ff, &uccup->rccm); in qe_uart_init_ucc()
677 /* Soft-UART requires a 1X multiplier for TX */ in qe_uart_init_ucc()
678 qe_clrsetbits_be32(&uccp->gumr_l, in qe_uart_init_ucc()
682 qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW, in qe_uart_init_ucc()
685 qe_clrsetbits_be32(&uccp->gumr_l, in qe_uart_init_ucc()
689 qe_clrsetbits_be32(&uccp->gumr_h, in qe_uart_init_ucc()
695 qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, in qe_uart_init_ucc()
697 qe_clrsetbits_be32(&uccp->gumr_h, in qe_uart_init_ucc()
703 iowrite16be(0, &uccp->uccm); in qe_uart_init_ucc()
704 iowrite16be(0xffff, &uccp->ucce); in qe_uart_init_ucc()
705 iowrite16be(0x7e7e, &uccp->udsr); in qe_uart_init_ucc()
708 iowrite16be(0, &uccp->upsmr); in qe_uart_init_ucc()
711 iowrite16be(0x30, &uccup->supsmr); in qe_uart_init_ucc()
712 iowrite16be(0, &uccup->res92); in qe_uart_init_ucc()
713 iowrite32be(0, &uccup->rx_state); in qe_uart_init_ucc()
714 iowrite32be(0, &uccup->rx_cnt); in qe_uart_init_ucc()
715 iowrite8(0, &uccup->rx_bitmark); in qe_uart_init_ucc()
716 iowrite8(10, &uccup->rx_length); in qe_uart_init_ucc()
717 iowrite32be(0x4000, &uccup->dump_ptr); in qe_uart_init_ucc()
718 iowrite8(0, &uccup->rx_temp_dlst_qe); in qe_uart_init_ucc()
719 iowrite32be(0, &uccup->rx_frame_rem); in qe_uart_init_ucc()
720 iowrite8(0, &uccup->rx_frame_rem_size); in qe_uart_init_ucc()
721 /* Soft-UART requires TX to be 1X */ in qe_uart_init_ucc()
723 &uccup->tx_mode); in qe_uart_init_ucc()
724 iowrite16be(0, &uccup->tx_state); in qe_uart_init_ucc()
725 iowrite8(0, &uccup->resD4); in qe_uart_init_ucc()
726 iowrite16be(0, &uccup->resD5); in qe_uart_init_ucc()
728 /* Set UART mode. in qe_uart_init_ucc()
733 * 1.GUMR_L register, set mode=0010 (QMC). in qe_uart_init_ucc()
734 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode). in qe_uart_init_ucc()
735 * 3.Set GUMR_H[19:20] (Transparent mode) in qe_uart_init_ucc()
740 qe_clrsetbits_be32(&uccp->gumr_l, in qe_uart_init_ucc()
744 qe_clrsetbits_be32(&uccp->gumr_h, in qe_uart_init_ucc()
749 qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, in qe_uart_init_ucc()
751 qe_clrbits_be32(&uccp->gumr_h, in qe_uart_init_ucc()
755 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); in qe_uart_init_ucc()
759 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); in qe_uart_init_ucc()
775 * If we're using Soft-UART mode, then we need to make sure the in qe_uart_startup()
779 dev_err(port->dev, "Soft-UART firmware not uploaded\n"); in qe_uart_startup()
780 return -ENODEV; in qe_uart_startup()
787 ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart", in qe_uart_startup()
790 dev_err(port->dev, "could not claim IRQ %u\n", port->irq); in qe_uart_startup()
794 /* Startup rx-int */ in qe_uart_startup()
795 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); in qe_uart_startup()
796 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX); in qe_uart_startup()
808 struct ucc_slow __iomem *uccp = qe_port->uccp; in qe_uart_shutdown()
815 if (!--timeout) { in qe_uart_shutdown()
816 dev_warn(port->dev, "shutdown timeout\n"); in qe_uart_shutdown()
823 if (qe_port->wait_closing) { in qe_uart_shutdown()
826 schedule_timeout(qe_port->wait_closing); in qe_uart_shutdown()
830 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); in qe_uart_shutdown()
831 qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX); in qe_uart_shutdown()
834 ucc_slow_graceful_stop_tx(qe_port->us_private); in qe_uart_shutdown()
837 free_irq(port->irq, qe_port); in qe_uart_shutdown()
849 struct ucc_slow __iomem *uccp = qe_port->uccp; in qe_uart_set_termios()
852 u16 upsmr = ioread16be(&uccp->upsmr); in qe_uart_set_termios()
853 struct ucc_uart_pram __iomem *uccup = qe_port->uccup; in qe_uart_set_termios()
854 u16 supsmr = ioread16be(&uccup->supsmr); in qe_uart_set_termios()
860 switch (termios->c_cflag & CSIZE) { in qe_uart_set_termios()
880 if (termios->c_cflag & CSTOPB) { in qe_uart_set_termios()
885 if (termios->c_cflag & PARENB) { in qe_uart_set_termios()
889 if (!(termios->c_cflag & PARODD)) { in qe_uart_set_termios()
904 port->read_status_mask = BD_SC_EMPTY | BD_SC_OV; in qe_uart_set_termios()
905 if (termios->c_iflag & INPCK) in qe_uart_set_termios()
906 port->read_status_mask |= BD_SC_FR | BD_SC_PR; in qe_uart_set_termios()
907 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in qe_uart_set_termios()
908 port->read_status_mask |= BD_SC_BR; in qe_uart_set_termios()
913 port->ignore_status_mask = 0; in qe_uart_set_termios()
914 if (termios->c_iflag & IGNPAR) in qe_uart_set_termios()
915 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; in qe_uart_set_termios()
916 if (termios->c_iflag & IGNBRK) { in qe_uart_set_termios()
917 port->ignore_status_mask |= BD_SC_BR; in qe_uart_set_termios()
922 if (termios->c_iflag & IGNPAR) in qe_uart_set_termios()
923 port->ignore_status_mask |= BD_SC_OV; in qe_uart_set_termios()
928 if ((termios->c_cflag & CREAD) == 0) in qe_uart_set_termios()
929 port->read_status_mask &= ~BD_SC_EMPTY; in qe_uart_set_termios()
931 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); in qe_uart_set_termios()
936 /* Update the per-port timeout. */ in qe_uart_set_termios()
937 uart_update_timeout(port, termios->c_cflag, baud); in qe_uart_set_termios()
939 iowrite16be(upsmr, &uccp->upsmr); in qe_uart_set_termios()
941 iowrite16be(supsmr, &uccup->supsmr); in qe_uart_set_termios()
942 iowrite8(tty_get_frame_size(termios->c_cflag), &uccup->rx_length); in qe_uart_set_termios()
944 /* Soft-UART requires a 1X multiplier for TX */ in qe_uart_set_termios()
945 qe_setbrg(qe_port->us_info.rx_clock, baud, 16); in qe_uart_set_termios()
946 qe_setbrg(qe_port->us_info.tx_clock, baud, 1); in qe_uart_set_termios()
948 qe_setbrg(qe_port->us_info.rx_clock, baud, 16); in qe_uart_set_termios()
949 qe_setbrg(qe_port->us_info.tx_clock, baud, 16); in qe_uart_set_termios()
971 struct ucc_slow_info *us_info = &qe_port->us_info; in qe_uart_request_port()
979 dev_err(port->dev, "could not initialize UCC%u\n", in qe_uart_request_port()
980 qe_port->ucc_num); in qe_uart_request_port()
984 qe_port->us_private = uccs; in qe_uart_request_port()
985 qe_port->uccp = uccs->us_regs; in qe_uart_request_port()
986 qe_port->uccup = (struct ucc_uart_pram __iomem *)uccs->us_pram; in qe_uart_request_port()
987 qe_port->rx_bd_base = uccs->rx_bd; in qe_uart_request_port()
988 qe_port->tx_bd_base = uccs->tx_bd; in qe_uart_request_port()
994 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); in qe_uart_request_port()
995 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize); in qe_uart_request_port()
997 bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr, in qe_uart_request_port()
1000 dev_err(port->dev, "could not allocate buffer descriptors\n"); in qe_uart_request_port()
1001 return -ENOMEM; in qe_uart_request_port()
1004 qe_port->bd_virt = bd_virt; in qe_uart_request_port()
1005 qe_port->bd_dma_addr = bd_dma_addr; in qe_uart_request_port()
1006 qe_port->bd_size = rx_size + tx_size; in qe_uart_request_port()
1008 qe_port->rx_buf = bd_virt; in qe_uart_request_port()
1009 qe_port->tx_buf = qe_port->rx_buf + rx_size; in qe_uart_request_port()
1017 * We say we're a CPM-type port because that's mostly true. Once the device
1024 port->type = PORT_CPM; in qe_uart_config_port()
1037 struct ucc_slow_private *uccs = qe_port->us_private; in qe_uart_release_port()
1039 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt, in qe_uart_release_port()
1040 qe_port->bd_dma_addr); in qe_uart_release_port()
1051 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) in qe_uart_verify_port()
1052 return -EINVAL; in qe_uart_verify_port()
1054 if (ser->irq < 0 || ser->irq >= nr_irqs) in qe_uart_verify_port()
1055 return -EINVAL; in qe_uart_verify_port()
1057 if (ser->baud_base < 9600) in qe_uart_verify_port()
1058 return -EINVAL; in qe_uart_verify_port()
1064 * Details on these functions can be found in Documentation/driver-api/serial/driver.rst
1124 soc_string = np->name; in soc_info()
1157 firmware = (struct qe_firmware *) fw->data; in uart_firmware_cont()
1159 if (be32_to_cpu(firmware->header.length) != fw->size) { in uart_firmware_cont()
1177 struct device_node *np = ofdev->dev.of_node; in soft_uart_init()
1181 if (of_property_read_bool(np, "soft-uart")) { in soft_uart_init()
1182 dev_dbg(&ofdev->dev, "using Soft-UART mode\n"); in soft_uart_init()
1191 if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) { in soft_uart_init()
1201 dev_err(&ofdev->dev, "unknown CPU model\n"); in soft_uart_init()
1202 return -ENXIO; in soft_uart_init()
1207 dev_info(&ofdev->dev, "waiting for firmware %s\n", in soft_uart_init()
1218 FW_ACTION_UEVENT, filename, &ofdev->dev, in soft_uart_init()
1219 GFP_KERNEL, &ofdev->dev, uart_firmware_cont); in soft_uart_init()
1221 dev_err(&ofdev->dev, in soft_uart_init()
1242 struct device_node *np = ofdev->dev.of_node; in ucc_uart_probe()
1250 * Determine if we need Soft-UART mode in ucc_uart_probe()
1258 dev_err(&ofdev->dev, "can't allocate QE port structure\n"); in ucc_uart_probe()
1259 return -ENOMEM; in ucc_uart_probe()
1265 dev_err(&ofdev->dev, "missing 'reg' property in device tree\n"); in ucc_uart_probe()
1269 dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n"); in ucc_uart_probe()
1270 ret = -EINVAL; in ucc_uart_probe()
1273 qe_port->port.mapbase = res.start; in ucc_uart_probe()
1276 /* UCCs are numbered 1-7 */ in ucc_uart_probe()
1277 if (of_property_read_u32(np, "cell-index", &val)) { in ucc_uart_probe()
1278 if (of_property_read_u32(np, "device-id", &val)) { in ucc_uart_probe()
1279 dev_err(&ofdev->dev, "UCC is unspecified in device tree\n"); in ucc_uart_probe()
1280 ret = -EINVAL; in ucc_uart_probe()
1286 dev_err(&ofdev->dev, "no support for UCC%u\n", val); in ucc_uart_probe()
1287 ret = -ENODEV; in ucc_uart_probe()
1290 qe_port->ucc_num = val - 1; in ucc_uart_probe()
1294 * device tree. If no clock-source is specified, then just pick a BRG in ucc_uart_probe()
1299 sprop = of_get_property(np, "rx-clock-name", NULL); in ucc_uart_probe()
1301 dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n"); in ucc_uart_probe()
1302 ret = -ENODEV; in ucc_uart_probe()
1306 qe_port->us_info.rx_clock = qe_clock_source(sprop); in ucc_uart_probe()
1307 if ((qe_port->us_info.rx_clock < QE_BRG1) || in ucc_uart_probe()
1308 (qe_port->us_info.rx_clock > QE_BRG16)) { in ucc_uart_probe()
1309 dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n"); in ucc_uart_probe()
1310 ret = -ENODEV; in ucc_uart_probe()
1315 /* In internal loopback mode, TX and RX must use the same clock */ in ucc_uart_probe()
1316 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock; in ucc_uart_probe()
1318 sprop = of_get_property(np, "tx-clock-name", NULL); in ucc_uart_probe()
1320 dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n"); in ucc_uart_probe()
1321 ret = -ENODEV; in ucc_uart_probe()
1324 qe_port->us_info.tx_clock = qe_clock_source(sprop); in ucc_uart_probe()
1326 if ((qe_port->us_info.tx_clock < QE_BRG1) || in ucc_uart_probe()
1327 (qe_port->us_info.tx_clock > QE_BRG16)) { in ucc_uart_probe()
1328 dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n"); in ucc_uart_probe()
1329 ret = -ENODEV; in ucc_uart_probe()
1333 /* Get the port number, numbered 0-3 */ in ucc_uart_probe()
1334 if (of_property_read_u32(np, "port-number", &val)) { in ucc_uart_probe()
1335 dev_err(&ofdev->dev, "missing port-number in device tree\n"); in ucc_uart_probe()
1336 ret = -EINVAL; in ucc_uart_probe()
1339 qe_port->port.line = val; in ucc_uart_probe()
1340 if (qe_port->port.line >= UCC_MAX_UART) { in ucc_uart_probe()
1341 dev_err(&ofdev->dev, "port-number must be 0-%u\n", in ucc_uart_probe()
1342 UCC_MAX_UART - 1); in ucc_uart_probe()
1343 ret = -EINVAL; in ucc_uart_probe()
1347 qe_port->port.irq = irq_of_parse_and_map(np, 0); in ucc_uart_probe()
1348 if (qe_port->port.irq == 0) { in ucc_uart_probe()
1349 dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n", in ucc_uart_probe()
1350 qe_port->ucc_num + 1); in ucc_uart_probe()
1351 ret = -EINVAL; in ucc_uart_probe()
1363 dev_err(&ofdev->dev, "could not find 'qe' node\n"); in ucc_uart_probe()
1364 ret = -EINVAL; in ucc_uart_probe()
1369 if (of_property_read_u32(np, "brg-frequency", &val)) { in ucc_uart_probe()
1370 dev_err(&ofdev->dev, in ucc_uart_probe()
1371 "missing brg-frequency in device tree\n"); in ucc_uart_probe()
1372 ret = -EINVAL; in ucc_uart_probe()
1377 qe_port->port.uartclk = val; in ucc_uart_probe()
1380 dev_err(&ofdev->dev, in ucc_uart_probe()
1381 "invalid brg-frequency in device tree\n"); in ucc_uart_probe()
1382 ret = -EINVAL; in ucc_uart_probe()
1387 * Older versions of U-Boot do not initialize the brg-frequency in ucc_uart_probe()
1391 if (of_property_read_u32(np, "bus-frequency", &val)) { in ucc_uart_probe()
1392 dev_err(&ofdev->dev, in ucc_uart_probe()
1393 "missing QE bus-frequency in device tree\n"); in ucc_uart_probe()
1394 ret = -EINVAL; in ucc_uart_probe()
1398 qe_port->port.uartclk = val / 2; in ucc_uart_probe()
1400 dev_err(&ofdev->dev, in ucc_uart_probe()
1401 "invalid QE bus-frequency in device tree\n"); in ucc_uart_probe()
1402 ret = -EINVAL; in ucc_uart_probe()
1407 spin_lock_init(&qe_port->port.lock); in ucc_uart_probe()
1408 qe_port->np = np; in ucc_uart_probe()
1409 qe_port->port.dev = &ofdev->dev; in ucc_uart_probe()
1410 qe_port->port.ops = &qe_uart_pops; in ucc_uart_probe()
1411 qe_port->port.iotype = UPIO_MEM; in ucc_uart_probe()
1413 qe_port->tx_nrfifos = TX_NUM_FIFO; in ucc_uart_probe()
1414 qe_port->tx_fifosize = TX_BUF_SIZE; in ucc_uart_probe()
1415 qe_port->rx_nrfifos = RX_NUM_FIFO; in ucc_uart_probe()
1416 qe_port->rx_fifosize = RX_BUF_SIZE; in ucc_uart_probe()
1418 qe_port->wait_closing = UCC_WAIT_CLOSING; in ucc_uart_probe()
1419 qe_port->port.fifosize = 512; in ucc_uart_probe()
1420 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; in ucc_uart_probe()
1422 qe_port->us_info.ucc_num = qe_port->ucc_num; in ucc_uart_probe()
1423 qe_port->us_info.regs = (phys_addr_t) res.start; in ucc_uart_probe()
1424 qe_port->us_info.irq = qe_port->port.irq; in ucc_uart_probe()
1426 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos; in ucc_uart_probe()
1427 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos; in ucc_uart_probe()
1430 qe_port->us_info.init_tx = 1; in ucc_uart_probe()
1431 qe_port->us_info.init_rx = 1; in ucc_uart_probe()
1433 /* Add the port to the uart sub-system. This will cause in ucc_uart_probe()
1437 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port); in ucc_uart_probe()
1439 dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n", in ucc_uart_probe()
1440 qe_port->port.line); in ucc_uart_probe()
1446 dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n", in ucc_uart_probe()
1447 qe_port->ucc_num + 1, qe_port->port.line); in ucc_uart_probe()
1450 dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n", in ucc_uart_probe()
1451 qe_port->port.line, SERIAL_QE_MAJOR, in ucc_uart_probe()
1452 SERIAL_QE_MINOR + qe_port->port.line); in ucc_uart_probe()
1466 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line); in ucc_uart_remove()
1468 uart_remove_one_port(&ucc_uart_driver, &qe_port->port); in ucc_uart_remove()
1470 of_node_put(qe_port->np); in ucc_uart_remove()
1481 .compatible = "fsl,t1040-ucc-uart",
1502 printk(KERN_INFO "ucc-uart: Using loopback mode\n"); in ucc_uart_init()
1507 printk(KERN_ERR "ucc-uart: could not register UART driver\n"); in ucc_uart_init()
1514 "ucc-uart: could not register platform driver\n"); in ucc_uart_init()