tty/serial/sunzilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
82 #define	SYNC_L_INH	0x2	/* Sync Character Load Inhibit */
98 #define	SYNC_ENAB	0	/* Sync Modes Enable */
103 #define	MONSYNC		0	/* 8 Bit Sync character */
104 #define	BISYNC		0x10	/* 16 bit sync character */
105 #define	SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
106 #define	EXTSYNC		0x30	/* External Sync Mode */
118 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
139 #define	EXT_RD_EN	0x40	/* Extended read register enable */
156 #define	BIT6	1	/* 6 bit/8bit sync */
206 #define	SYNCIE	0x10	/* Sync/hunt IE */
212 /* Read Register 0 */
217 #define	SYNC		0x10	/* Sync/hunt */  macro
222 /* Read Register 1 */
239 /* Read Register 2 (channel b only) - Interrupt vector */
250 /* Read Register 3 (interrupt pending register) ch a only */
258 /* Read Register 6 (LSB frame byte count [Not on NMOS]) */
260 /* Read Register 7 (MSB frame byte count and FIFO status [Not on NMOS]) */
262 /* Read Register 8 (receive data register) */
264 /* Read Register 10  (misc status bits) */
270 /* Read Register 12 (lower byte of baud rate generator constant) */
272 /* Read Register 13 (upper byte of baud rate generator constant) */
274 /* Read Register 15 (value of WR 15) */
277 #define ZS_CLEARERR(channel)    do { sbus_writeb(ERR_RES, &channel->control); \
280 #define ZS_CLEARSTAT(channel)   do { sbus_writeb(RES_EXT_INT, &channel->control); \
283 #define ZS_CLEARFIFO(channel)   do { sbus_readb(&channel->data); \
285 				     sbus_readb(&channel->data); \
287 				     sbus_readb(&channel->data); \