Lines Matching +full:fifo +full:- +full:watermark +full:- +full:aligned
1 // SPDX-License-Identifier: GPL-2.0
5 * High-speed serial driver for NVIDIA Tegra SoCs
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
16 #include <linux/dma-mapping.h>
56 * Tx fifo trigger level setting in tegra uart is in
79 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
80 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
83 * @fifo_mode_enable_status: Is FIFO mode enabled?
159 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
165 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
178 * RI - Ring detector is active in tegra_uart_get_mctrl()
179 * CD/DCD/CAR - Carrier detect is always active. For some reason in tegra_uart_get_mctrl()
181 * DSR - Data Set ready is active as the hardware doesn't support it. in tegra_uart_get_mctrl()
183 * CTS - Clear to send. Always set to active, as the hardware handles in tegra_uart_get_mctrl()
186 if (tup->enable_modem_interrupt) in tegra_uart_get_mctrl()
195 mcr = tup->mcr_shadow; in set_rts()
200 if (mcr != tup->mcr_shadow) { in set_rts()
202 tup->mcr_shadow = mcr; in set_rts()
210 mcr = tup->mcr_shadow; in set_dtr()
215 if (mcr != tup->mcr_shadow) { in set_dtr()
217 tup->mcr_shadow = mcr; in set_dtr()
223 unsigned long mcr = tup->mcr_shadow; in set_loopbk()
230 if (mcr != tup->mcr_shadow) { in set_loopbk()
232 tup->mcr_shadow = mcr; in set_loopbk()
241 tup->rts_active = !!(mctrl & TIOCM_RTS); in tegra_uart_set_mctrl()
242 set_rts(tup, tup->rts_active); in tegra_uart_set_mctrl()
256 lcr = tup->lcr_shadow; in tegra_uart_break_ctl()
262 tup->lcr_shadow = lcr; in tegra_uart_break_ctl()
277 if (tup->current_baud) in tegra_uart_wait_cycle_time()
278 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); in tegra_uart_wait_cycle_time()
281 /* Wait for a symbol-time. */
285 if (tup->current_baud) in tegra_uart_wait_sym_time()
286 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, in tegra_uart_wait_sym_time()
287 tup->current_baud)); in tegra_uart_wait_sym_time()
300 } while (--tmout); in tegra_uart_wait_fifo_mode_enabled()
302 return -ETIMEDOUT; in tegra_uart_wait_fifo_mode_enabled()
307 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset()
310 if (tup->rts_active) in tegra_uart_fifo_reset()
313 if (tup->cdata->allow_txfifo_reset_fifo_mode) { in tegra_uart_fifo_reset()
324 if (tup->cdata->fifo_mode_enable_status) in tegra_uart_fifo_reset()
343 } while (--tmout); in tegra_uart_fifo_reset()
345 if (tup->rts_active) in tegra_uart_fifo_reset()
354 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) { in tegra_get_tolerance_rate()
355 if (baud >= tup->baud_tolerance[i].lower_range_baud && in tegra_get_tolerance_rate()
356 baud <= tup->baud_tolerance[i].upper_range_baud) in tegra_get_tolerance_rate()
358 tup->baud_tolerance[i].tolerance) / 10000); in tegra_get_tolerance_rate()
368 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000) in tegra_check_rate_in_range()
369 / tup->required_rate; in tegra_check_rate_in_range()
370 if (diff < (tup->cdata->error_tolerance_low_range * 100) || in tegra_check_rate_in_range()
371 diff > (tup->cdata->error_tolerance_high_range * 100)) { in tegra_check_rate_in_range()
372 dev_err(tup->uport.dev, in tegra_check_rate_in_range()
374 return -EIO; in tegra_check_rate_in_range()
388 if (tup->current_baud == baud) in tegra_set_baudrate()
391 if (tup->cdata->support_clk_src_div) { in tegra_set_baudrate()
393 tup->required_rate = rate; in tegra_set_baudrate()
395 if (tup->n_adjustable_baud_rates) in tegra_set_baudrate()
398 ret = clk_set_rate(tup->uart_clk, rate); in tegra_set_baudrate()
400 dev_err(tup->uport.dev, in tegra_set_baudrate()
404 tup->configured_rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
410 rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
414 uart_port_lock_irqsave(&tup->uport, &flags); in tegra_set_baudrate()
415 lcr = tup->lcr_shadow; in tegra_set_baudrate()
427 uart_port_unlock_irqrestore(&tup->uport, flags); in tegra_set_baudrate()
429 tup->current_baud = baud; in tegra_set_baudrate()
445 tup->uport.icount.overrun++; in tegra_uart_decode_rx_error()
446 dev_dbg(tup->uport.dev, "Got overrun errors\n"); in tegra_uart_decode_rx_error()
450 tup->uport.icount.parity++; in tegra_uart_decode_rx_error()
451 dev_dbg(tup->uport.dev, "Got Parity errors\n"); in tegra_uart_decode_rx_error()
454 tup->uport.icount.frame++; in tegra_uart_decode_rx_error()
455 dev_dbg(tup->uport.dev, "Got frame errors\n"); in tegra_uart_decode_rx_error()
459 * If FIFO read error without any data, reset Rx FIFO in tegra_uart_decode_rx_error()
463 if (tup->uport.ignore_status_mask & UART_LSR_BI) in tegra_uart_decode_rx_error()
466 tup->uport.icount.brk++; in tegra_uart_decode_rx_error()
467 dev_dbg(tup->uport.dev, "Got Break\n"); in tegra_uart_decode_rx_error()
469 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag); in tegra_uart_decode_rx_error()
487 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_fill_tx_fifo()
492 if (tup->cdata->tx_fifo_full_status) { in tegra_uart_fill_tx_fifo()
497 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); in tegra_uart_fill_tx_fifo()
498 uart_xmit_advance(&tup->uport, 1); in tegra_uart_fill_tx_fifo()
508 tup->tx_in_progress = TEGRA_UART_TX_PIO; in tegra_uart_start_pio_tx()
509 tup->tx_bytes = bytes; in tegra_uart_start_pio_tx()
510 tup->ier_shadow |= UART_IER_THRI; in tegra_uart_start_pio_tx()
511 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_start_pio_tx()
517 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_tx_dma_complete()
522 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_tx_dma_complete()
523 count = tup->tx_bytes_requested - state.residue; in tegra_uart_tx_dma_complete()
524 async_tx_ack(tup->tx_dma_desc); in tegra_uart_tx_dma_complete()
525 uart_port_lock_irqsave(&tup->uport, &flags); in tegra_uart_tx_dma_complete()
526 uart_xmit_advance(&tup->uport, count); in tegra_uart_tx_dma_complete()
527 tup->tx_in_progress = 0; in tegra_uart_tx_dma_complete()
529 uart_write_wakeup(&tup->uport); in tegra_uart_tx_dma_complete()
531 uart_port_unlock_irqrestore(&tup->uport, flags); in tegra_uart_tx_dma_complete()
537 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_tx_dma()
540 tup->tx_bytes = count & ~(0xF); in tegra_uart_start_tx_dma()
541 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; in tegra_uart_start_tx_dma()
543 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr, in tegra_uart_start_tx_dma()
544 tup->tx_bytes, DMA_TO_DEVICE); in tegra_uart_start_tx_dma()
546 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, in tegra_uart_start_tx_dma()
547 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, in tegra_uart_start_tx_dma()
549 if (!tup->tx_dma_desc) { in tegra_uart_start_tx_dma()
550 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); in tegra_uart_start_tx_dma()
551 return -EIO; in tegra_uart_start_tx_dma()
554 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; in tegra_uart_start_tx_dma()
555 tup->tx_dma_desc->callback_param = tup; in tegra_uart_start_tx_dma()
556 tup->tx_in_progress = TEGRA_UART_TX_DMA; in tegra_uart_start_tx_dma()
557 tup->tx_bytes_requested = tup->tx_bytes; in tegra_uart_start_tx_dma()
558 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); in tegra_uart_start_tx_dma()
559 dma_async_issue_pending(tup->tx_dma_chan); in tegra_uart_start_tx_dma()
567 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_next_tx()
569 if (!tup->current_baud) in tegra_uart_start_next_tx()
572 tail = (unsigned long)&xmit->buf[xmit->tail]; in tegra_uart_start_next_tx()
573 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in tegra_uart_start_next_tx()
577 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA) in tegra_uart_start_next_tx()
585 /* Called by serial core driver with u->lock taken. */
589 struct circ_buf *xmit = &u->state->xmit; in tegra_uart_start_tx()
591 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) in tegra_uart_start_tx()
602 if (!tup->tx_in_progress) { in tegra_uart_tx_empty()
617 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) in tegra_uart_stop_tx()
620 dmaengine_pause(tup->tx_dma_chan); in tegra_uart_stop_tx()
621 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_stop_tx()
622 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_stop_tx()
623 count = tup->tx_bytes_requested - state.residue; in tegra_uart_stop_tx()
624 async_tx_ack(tup->tx_dma_desc); in tegra_uart_stop_tx()
625 uart_xmit_advance(&tup->uport, count); in tegra_uart_stop_tx()
626 tup->tx_in_progress = 0; in tegra_uart_stop_tx()
631 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_handle_tx_pio()
633 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); in tegra_uart_handle_tx_pio()
634 tup->tx_in_progress = 0; in tegra_uart_handle_tx_pio()
636 uart_write_wakeup(&tup->uport); in tegra_uart_handle_tx_pio()
656 tup->uport.icount.rx++; in tegra_uart_handle_rx_pio()
658 if (uart_handle_sysrq_char(&tup->uport, ch)) in tegra_uart_handle_rx_pio()
661 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_handle_rx_pio()
678 tup->uport.icount.rx += count; in tegra_uart_copy_rx_to_tty()
680 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_copy_rx_to_tty()
683 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
686 ((unsigned char *)(tup->rx_dma_buf_virt)), count); in tegra_uart_copy_rx_to_tty()
689 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); in tegra_uart_copy_rx_to_tty()
691 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
697 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); in do_handle_rx_pio()
698 struct tty_port *port = &tup->uport.state->port; in do_handle_rx_pio()
710 struct tty_port *port = &tup->uport.state->port; in tegra_uart_rx_buffer_push()
713 async_tx_ack(tup->rx_dma_desc); in tegra_uart_rx_buffer_push()
714 count = tup->rx_bytes_requested - residue; in tegra_uart_rx_buffer_push()
725 struct uart_port *u = &tup->uport; in tegra_uart_rx_dma_complete()
732 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_rx_dma_complete()
735 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); in tegra_uart_rx_dma_complete()
740 if (tup->rts_active) in tegra_uart_rx_dma_complete()
743 tup->rx_dma_active = false; in tegra_uart_rx_dma_complete()
748 if (tup->rts_active) in tegra_uart_rx_dma_complete()
759 if (!tup->rx_dma_active) { in tegra_uart_terminate_rx_dma()
764 dmaengine_pause(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
765 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_terminate_rx_dma()
766 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
769 tup->rx_dma_active = false; in tegra_uart_terminate_rx_dma()
775 if (tup->rts_active) in tegra_uart_handle_rx_dma()
780 if (tup->rts_active) in tegra_uart_handle_rx_dma()
788 if (tup->rx_dma_active) in tegra_uart_start_rx_dma()
791 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, in tegra_uart_start_rx_dma()
792 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, in tegra_uart_start_rx_dma()
794 if (!tup->rx_dma_desc) { in tegra_uart_start_rx_dma()
795 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); in tegra_uart_start_rx_dma()
796 return -EIO; in tegra_uart_start_rx_dma()
799 tup->rx_dma_active = true; in tegra_uart_start_rx_dma()
800 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; in tegra_uart_start_rx_dma()
801 tup->rx_dma_desc->callback_param = tup; in tegra_uart_start_rx_dma()
802 tup->rx_bytes_requested = count; in tegra_uart_start_rx_dma()
803 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); in tegra_uart_start_rx_dma()
804 dma_async_issue_pending(tup->rx_dma_chan); in tegra_uart_start_rx_dma()
818 tup->uport.icount.rng++; in tegra_uart_handle_modem_signal_change()
820 tup->uport.icount.dsr++; in tegra_uart_handle_modem_signal_change()
823 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); in tegra_uart_handle_modem_signal_change()
826 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); in tegra_uart_handle_modem_signal_change()
832 struct uart_port *u = &tup->uport; in tegra_uart_isr()
843 if (!tup->use_rx_pio && is_rx_int) { in tegra_uart_isr()
845 if (tup->rx_in_progress) { in tegra_uart_isr()
846 ier = tup->ier_shadow; in tegra_uart_isr()
849 tup->ier_shadow = ier; in tegra_uart_isr()
865 tup->ier_shadow &= ~UART_IER_THRI; in tegra_uart_isr()
866 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_isr()
872 if (!tup->use_rx_pio) { in tegra_uart_isr()
873 is_rx_int = tup->rx_in_progress; in tegra_uart_isr()
875 ier = tup->ier_shadow; in tegra_uart_isr()
878 tup->ier_shadow = ier; in tegra_uart_isr()
884 if (!tup->use_rx_pio) { in tegra_uart_isr()
885 is_rx_start = tup->rx_in_progress; in tegra_uart_isr()
886 tup->ier_shadow &= ~UART_IER_RDI; in tegra_uart_isr()
887 tegra_uart_write(tup, tup->ier_shadow, in tegra_uart_isr()
909 struct tty_port *port = &tup->uport.state->port; in tegra_uart_stop_rx()
912 if (tup->rts_active) in tegra_uart_stop_rx()
915 if (!tup->rx_in_progress) in tegra_uart_stop_rx()
920 ier = tup->ier_shadow; in tegra_uart_stop_rx()
923 tup->ier_shadow = ier; in tegra_uart_stop_rx()
925 tup->rx_in_progress = 0; in tegra_uart_stop_rx()
927 if (!tup->use_rx_pio) in tegra_uart_stop_rx()
936 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); in tegra_uart_hw_deinit()
937 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; in tegra_uart_hw_deinit()
951 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
952 "Tx Fifo not empty, CTS disabled, waiting\n"); in tegra_uart_hw_deinit()
954 /* Wait for Tx fifo to be empty */ in tegra_uart_hw_deinit()
958 fifo_empty_time -= wait_time; in tegra_uart_hw_deinit()
964 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
972 uart_port_lock_irqsave(&tup->uport, &flags); in tegra_uart_hw_deinit()
975 tup->current_baud = 0; in tegra_uart_hw_deinit()
976 uart_port_unlock_irqrestore(&tup->uport, flags); in tegra_uart_hw_deinit()
978 tup->rx_in_progress = 0; in tegra_uart_hw_deinit()
979 tup->tx_in_progress = 0; in tegra_uart_hw_deinit()
981 if (!tup->use_rx_pio) in tegra_uart_hw_deinit()
983 if (!tup->use_tx_pio) in tegra_uart_hw_deinit()
986 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_deinit()
993 tup->fcr_shadow = 0; in tegra_uart_hw_init()
994 tup->mcr_shadow = 0; in tegra_uart_hw_init()
995 tup->lcr_shadow = 0; in tegra_uart_hw_init()
996 tup->ier_shadow = 0; in tegra_uart_hw_init()
997 tup->current_baud = 0; in tegra_uart_hw_init()
999 ret = clk_prepare_enable(tup->uart_clk); in tegra_uart_hw_init()
1001 dev_err(tup->uport.dev, "could not enable clk\n"); in tegra_uart_hw_init()
1006 reset_control_assert(tup->rst); in tegra_uart_hw_init()
1008 reset_control_deassert(tup->rst); in tegra_uart_hw_init()
1010 tup->rx_in_progress = 0; in tegra_uart_hw_init()
1011 tup->tx_in_progress = 0; in tegra_uart_hw_init()
1020 * interrupt is received. Rx high watermark is set to 4. in tegra_uart_hw_init()
1023 * interrupt the CPU when the number of entries in the FIFO reaches the in tegra_uart_hw_init()
1024 * low watermark. Tx low watermark is set to 16 bytes. in tegra_uart_hw_init()
1031 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; in tegra_uart_hw_init()
1033 if (tup->use_rx_pio) { in tegra_uart_hw_init()
1034 tup->fcr_shadow |= UART_FCR_R_TRIG_11; in tegra_uart_hw_init()
1036 if (tup->cdata->max_dma_burst_bytes == 8) in tegra_uart_hw_init()
1037 tup->fcr_shadow |= UART_FCR_R_TRIG_10; in tegra_uart_hw_init()
1039 tup->fcr_shadow |= UART_FCR_R_TRIG_01; in tegra_uart_hw_init()
1042 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; in tegra_uart_hw_init()
1043 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1048 if (tup->cdata->fifo_mode_enable_status) { in tegra_uart_hw_init()
1051 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_init()
1052 dev_err(tup->uport.dev, in tegra_uart_hw_init()
1053 "Failed to enable FIFO mode: %d\n", ret); in tegra_uart_hw_init()
1060 * periods after enabling the TX fifo, otherwise data could in tegra_uart_hw_init()
1073 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_init()
1074 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_hw_init()
1077 if (!tup->use_rx_pio) { in tegra_uart_hw_init()
1078 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; in tegra_uart_hw_init()
1079 tup->fcr_shadow |= UART_FCR_DMA_SELECT; in tegra_uart_hw_init()
1080 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1082 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1084 tup->rx_in_progress = 1; in tegra_uart_hw_init()
1090 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when in tegra_uart_hw_init()
1091 * the DATA is sitting in the FIFO and couldn't be transferred to the in tegra_uart_hw_init()
1096 * For pauses in the data which is not aligned to 4 bytes, we get in tegra_uart_hw_init()
1097 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first in tegra_uart_hw_init()
1100 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI; in tegra_uart_hw_init()
1106 if (!tup->use_rx_pio) in tegra_uart_hw_init()
1107 tup->ier_shadow |= TEGRA_UART_IER_EORD; in tegra_uart_hw_init()
1109 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_hw_init()
1117 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1118 dma_release_channel(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1119 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, in tegra_uart_dma_channel_free()
1120 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); in tegra_uart_dma_channel_free()
1121 tup->rx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1122 tup->rx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1123 tup->rx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1125 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1126 dma_release_channel(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1127 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_dma_channel_free()
1129 tup->tx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1130 tup->tx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1131 tup->tx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1144 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx"); in tegra_uart_dma_channel_allocate()
1147 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1153 dma_buf = dma_alloc_coherent(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1157 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1160 return -ENOMEM; in tegra_uart_dma_channel_allocate()
1162 dma_sync_single_for_device(tup->uport.dev, dma_phys, in tegra_uart_dma_channel_allocate()
1165 dma_sconfig.src_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1167 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes; in tegra_uart_dma_channel_allocate()
1168 tup->rx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1169 tup->rx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1170 tup->rx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1172 dma_phys = dma_map_single(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1173 tup->uport.state->xmit.buf, UART_XMIT_SIZE, in tegra_uart_dma_channel_allocate()
1175 if (dma_mapping_error(tup->uport.dev, dma_phys)) { in tegra_uart_dma_channel_allocate()
1176 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); in tegra_uart_dma_channel_allocate()
1178 return -ENOMEM; in tegra_uart_dma_channel_allocate()
1180 dma_buf = tup->uport.state->xmit.buf; in tegra_uart_dma_channel_allocate()
1181 dma_sconfig.dst_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1184 tup->tx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1185 tup->tx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1186 tup->tx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1191 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1205 if (!tup->use_tx_pio) { in tegra_uart_startup()
1208 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", in tegra_uart_startup()
1214 if (!tup->use_rx_pio) { in tegra_uart_startup()
1217 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", in tegra_uart_startup()
1225 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); in tegra_uart_startup()
1229 ret = request_irq(u->irq, tegra_uart_isr, 0, in tegra_uart_startup()
1230 dev_name(u->dev), tup); in tegra_uart_startup()
1232 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); in tegra_uart_startup()
1238 /* tup->uart_clk is already enabled in tegra_uart_hw_init */ in tegra_uart_startup()
1239 clk_disable_unprepare(tup->uart_clk); in tegra_uart_startup()
1241 if (!tup->use_rx_pio) in tegra_uart_startup()
1244 if (!tup->use_tx_pio) in tegra_uart_startup()
1257 tup->tx_bytes = 0; in tegra_uart_flush_buffer()
1258 if (tup->tx_dma_chan) in tegra_uart_flush_buffer()
1259 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_flush_buffer()
1267 free_irq(u->irq, tup); in tegra_uart_shutdown()
1274 if (tup->enable_modem_interrupt) { in tegra_uart_enable_ms()
1275 tup->ier_shadow |= UART_IER_MSI; in tegra_uart_enable_ms()
1276 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_enable_ms()
1289 struct clk *parent_clk = clk_get_parent(tup->uart_clk); in tegra_uart_set_termios()
1291 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; in tegra_uart_set_termios()
1298 if (tup->rts_active) in tegra_uart_set_termios()
1302 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); in tegra_uart_set_termios()
1308 lcr = tup->lcr_shadow; in tegra_uart_set_termios()
1312 termios->c_cflag &= ~CMSPAR; in tegra_uart_set_termios()
1314 if ((termios->c_cflag & PARENB) == PARENB) { in tegra_uart_set_termios()
1315 if (termios->c_cflag & PARODD) { in tegra_uart_set_termios()
1326 char_bits = tty_get_char_size(termios->c_cflag); in tegra_uart_set_termios()
1331 if (termios->c_cflag & CSTOPB) in tegra_uart_set_termios()
1337 tup->lcr_shadow = lcr; in tegra_uart_set_termios()
1338 tup->symb_bit = tty_get_frame_size(termios->c_cflag); in tegra_uart_set_termios()
1347 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_set_termios()
1355 if (termios->c_cflag & CRTSCTS) { in tegra_uart_set_termios()
1356 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1357 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1358 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1360 if (tup->rts_active) in tegra_uart_set_termios()
1363 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1364 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1365 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1369 uart_update_timeout(u, termios->c_cflag, baud); in tegra_uart_set_termios()
1374 /* Re-enable interrupt */ in tegra_uart_set_termios()
1375 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_set_termios()
1378 tup->uport.ignore_status_mask = 0; in tegra_uart_set_termios()
1380 if ((termios->c_cflag & CREAD) == 0) in tegra_uart_set_termios()
1381 tup->uport.ignore_status_mask |= UART_LSR_DR; in tegra_uart_set_termios()
1382 if (termios->c_iflag & IGNBRK) in tegra_uart_set_termios()
1383 tup->uport.ignore_status_mask |= UART_LSR_BI; in tegra_uart_set_termios()
1422 struct device_node *np = pdev->dev.of_node; in tegra_uart_parse_dt()
1432 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); in tegra_uart_parse_dt()
1435 tup->uport.line = port; in tegra_uart_parse_dt()
1437 tup->enable_modem_interrupt = of_property_read_bool(np, in tegra_uart_parse_dt()
1438 "nvidia,enable-modem-interrupt"); in tegra_uart_parse_dt()
1440 index = of_property_match_string(np, "dma-names", "rx"); in tegra_uart_parse_dt()
1442 tup->use_rx_pio = true; in tegra_uart_parse_dt()
1443 dev_info(&pdev->dev, "RX in PIO mode\n"); in tegra_uart_parse_dt()
1445 index = of_property_match_string(np, "dma-names", "tx"); in tegra_uart_parse_dt()
1447 tup->use_tx_pio = true; in tegra_uart_parse_dt()
1448 dev_info(&pdev->dev, "TX in PIO mode\n"); in tegra_uart_parse_dt()
1451 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates"); in tegra_uart_parse_dt()
1453 tup->n_adjustable_baud_rates = n_entries / 3; in tegra_uart_parse_dt()
1454 tup->baud_tolerance = in tegra_uart_parse_dt()
1455 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) * in tegra_uart_parse_dt()
1456 sizeof(*tup->baud_tolerance), GFP_KERNEL); in tegra_uart_parse_dt()
1457 if (!tup->baud_tolerance) in tegra_uart_parse_dt()
1458 return -ENOMEM; in tegra_uart_parse_dt()
1463 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1466 tup->baud_tolerance[index].lower_range_baud = in tegra_uart_parse_dt()
1470 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1473 tup->baud_tolerance[index].upper_range_baud = in tegra_uart_parse_dt()
1477 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1480 tup->baud_tolerance[index].tolerance = in tegra_uart_parse_dt()
1484 tup->n_adjustable_baud_rates = 0; in tegra_uart_parse_dt()
1497 .error_tolerance_low_range = -4,
1508 .error_tolerance_low_range = -4,
1530 .error_tolerance_low_range = -2,
1536 .compatible = "nvidia,tegra30-hsuart",
1539 .compatible = "nvidia,tegra20-hsuart",
1542 .compatible = "nvidia,tegra186-hsuart",
1545 .compatible = "nvidia,tegra194-hsuart",
1560 cdata = of_device_get_match_data(&pdev->dev); in tegra_uart_probe()
1562 dev_err(&pdev->dev, "Error: No device match found\n"); in tegra_uart_probe()
1563 return -ENODEV; in tegra_uart_probe()
1566 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); in tegra_uart_probe()
1568 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); in tegra_uart_probe()
1569 return -ENOMEM; in tegra_uart_probe()
1576 u = &tup->uport; in tegra_uart_probe()
1577 u->dev = &pdev->dev; in tegra_uart_probe()
1578 u->ops = &tegra_uart_ops; in tegra_uart_probe()
1579 u->type = PORT_TEGRA; in tegra_uart_probe()
1580 u->fifosize = 32; in tegra_uart_probe()
1581 tup->cdata = cdata; in tegra_uart_probe()
1585 u->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &resource); in tegra_uart_probe()
1586 if (IS_ERR(u->membase)) in tegra_uart_probe()
1587 return PTR_ERR(u->membase); in tegra_uart_probe()
1588 u->mapbase = resource->start; in tegra_uart_probe()
1590 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
1591 if (IS_ERR(tup->uart_clk)) in tegra_uart_probe()
1592 return dev_err_probe(&pdev->dev, PTR_ERR(tup->uart_clk), "Couldn't get the clock"); in tegra_uart_probe()
1594 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial"); in tegra_uart_probe()
1595 if (IS_ERR(tup->rst)) { in tegra_uart_probe()
1596 dev_err(&pdev->dev, "Couldn't get the reset\n"); in tegra_uart_probe()
1597 return PTR_ERR(tup->rst); in tegra_uart_probe()
1600 u->iotype = UPIO_MEM32; in tegra_uart_probe()
1604 u->irq = ret; in tegra_uart_probe()
1605 u->regshift = 2; in tegra_uart_probe()
1608 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); in tegra_uart_probe()
1617 struct uart_port *u = &tup->uport; in tegra_uart_remove()
1626 struct uart_port *u = &tup->uport; in tegra_uart_suspend()
1634 struct uart_port *u = &tup->uport; in tegra_uart_resume()
1648 .name = "serial-tegra",
1666 cdata = match->data; in tegra_uart_init()
1668 tegra_uart_driver.nr = cdata->uart_max_port; in tegra_uart_init()
1696 MODULE_ALIAS("platform:serial-tegra");