Lines Matching +full:msm +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
18 #include <linux/soc/qcom/geni-se.h>
24 #include <dt-bindings/interconnect/qcom,icc.h>
26 /* UART specific GENI registers */
68 /* UART M_CMD OP codes */
70 /* UART S_CMD OP codes */
90 /* UART pin swap value */
190 struct platform_device *pdev = to_platform_device(uport->dev); in qcom_geni_serial_request_port()
193 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
194 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
195 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
196 port->se.base = uport->membase; in qcom_geni_serial_request_port()
203 uport->type = PORT_MSM; in qcom_geni_serial_config_port()
216 geni_ios = readl(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
234 port->loopback = RX_TX_CTS_RTS_SORTED; in qcom_geni_serial_set_mctrl()
236 if (!(mctrl & TIOCM_RTS) && !uport->suspended) in qcom_geni_serial_set_mctrl()
238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
243 return "MSM"; in qcom_geni_serial_get_type()
252 return ERR_PTR(-ENXIO); in get_port_from_line()
260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; in qcom_geni_serial_main_active()
265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; in qcom_geni_serial_secondary_active()
276 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_poll_bit()
278 if (private_data->drv) { in qcom_geni_serial_poll_bit()
280 baud = port->baud; in qcom_geni_serial_poll_bit()
283 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; in qcom_geni_serial_poll_bit()
297 reg = readl(uport->membase + offset); in qcom_geni_serial_poll_bit()
301 timeout_us -= 10; in qcom_geni_serial_poll_bit()
310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); in qcom_geni_serial_setup_tx()
312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); in qcom_geni_serial_setup_tx()
323 writel(M_GENI_CMD_ABORT, uport->membase + in qcom_geni_serial_poll_tx_done()
329 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_poll_tx_done()
336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); in qcom_geni_serial_abort_rx()
339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_abort_rx()
340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); in qcom_geni_serial_abort_rx()
346 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_get_char()
351 if (!private_data->poll_cached_bytes_cnt) { in qcom_geni_serial_get_char()
352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); in qcom_geni_serial_get_char()
353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_get_char()
355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_get_char()
356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_get_char()
358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); in qcom_geni_serial_get_char()
368 private_data->poll_cached_bytes_cnt = in qcom_geni_serial_get_char()
372 if (private_data->poll_cached_bytes_cnt == 0) in qcom_geni_serial_get_char()
373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; in qcom_geni_serial_get_char()
375 private_data->poll_cached_bytes = in qcom_geni_serial_get_char()
376 readl(uport->membase + SE_GENI_RX_FIFOn); in qcom_geni_serial_get_char()
379 private_data->poll_cached_bytes_cnt--; in qcom_geni_serial_get_char()
380 ret = private_data->poll_cached_bytes & 0xff; in qcom_geni_serial_get_char()
381 private_data->poll_cached_bytes >>= 8; in qcom_geni_serial_get_char()
389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); in qcom_geni_serial_poll_put_char()
393 writel(c, uport->membase + SE_GENI_TX_FIFOn); in qcom_geni_serial_poll_put_char()
394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_poll_put_char()
402 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_wr_char()
404 private_data->write_cached_bytes = in qcom_geni_serial_wr_char()
405 (private_data->write_cached_bytes >> 8) | (ch << 24); in qcom_geni_serial_wr_char()
406 private_data->write_cached_bytes_cnt++; in qcom_geni_serial_wr_char()
408 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { in qcom_geni_serial_wr_char()
409 writel(private_data->write_cached_bytes, in qcom_geni_serial_wr_char()
410 uport->membase + SE_GENI_TX_FIFOn); in qcom_geni_serial_wr_char()
411 private_data->write_cached_bytes_cnt = 0; in qcom_geni_serial_wr_char()
419 struct qcom_geni_private_data *private_data = uport->private_data; in __qcom_geni_serial_console_write()
433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); in __qcom_geni_serial_console_write()
437 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; in __qcom_geni_serial_console_write()
448 chars_to_write = min_t(size_t, count - i, avail / 2); in __qcom_geni_serial_console_write()
451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + in __qcom_geni_serial_console_write()
456 if (private_data->write_cached_bytes_cnt) { in __qcom_geni_serial_console_write()
457 private_data->write_cached_bytes >>= BITS_PER_BYTE * in __qcom_geni_serial_console_write()
458 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); in __qcom_geni_serial_console_write()
459 writel(private_data->write_cached_bytes, in __qcom_geni_serial_console_write()
460 uport->membase + SE_GENI_TX_FIFOn); in __qcom_geni_serial_console_write()
461 private_data->write_cached_bytes_cnt = 0; in __qcom_geni_serial_console_write()
477 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); in qcom_geni_serial_console_write()
479 port = get_port_from_line(co->index, true); in qcom_geni_serial_console_write()
483 uport = &port->uport; in qcom_geni_serial_console_write()
489 geni_status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_console_write()
493 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_console_write()
496 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_console_write()
499 writel(M_CMD_ABORT_EN, uport->membase + in qcom_geni_serial_console_write()
502 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_console_write()
503 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { in qcom_geni_serial_console_write()
510 if (!uart_circ_empty(&uport->state->xmit)) { in qcom_geni_serial_console_write()
511 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_console_write()
513 uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_console_write()
519 if (port->tx_remaining) in qcom_geni_serial_console_write()
520 qcom_geni_serial_setup_tx(uport, port->tx_remaining); in qcom_geni_serial_console_write()
533 tport = &uport->state->port; in handle_rx_console()
536 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); in handle_rx_console()
538 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); in handle_rx_console()
546 uport->icount.rx++; in handle_rx_console()
547 if (port->brk && buf[c] == 0) { in handle_rx_console()
548 port->brk = false; in handle_rx_console()
572 struct tty_port *tport = &uport->state->port; in handle_rx_uart()
575 ret = tty_insert_flip_string(tport, port->rx_buf, bytes); in handle_rx_uart()
577 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", in handle_rx_uart()
581 uport->icount.rx += ret; in handle_rx_uart()
587 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); in qcom_geni_serial_tx_empty()
598 if (port->tx_dma_addr) { in qcom_geni_serial_stop_tx_dma()
599 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, in qcom_geni_serial_stop_tx_dma()
600 port->tx_remaining); in qcom_geni_serial_stop_tx_dma()
601 port->tx_dma_addr = 0; in qcom_geni_serial_stop_tx_dma()
602 port->tx_remaining = 0; in qcom_geni_serial_stop_tx_dma()
605 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_stop_tx_dma()
610 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_stop_tx_dma()
614 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); in qcom_geni_serial_stop_tx_dma()
615 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_stop_tx_dma()
618 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_stop_tx_dma()
624 struct circ_buf *xmit = &uport->state->xmit; in qcom_geni_serial_start_tx_dma()
628 if (port->tx_dma_addr) in qcom_geni_serial_start_tx_dma()
634 xmit_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in qcom_geni_serial_start_tx_dma()
638 ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail], in qcom_geni_serial_start_tx_dma()
639 xmit_size, &port->tx_dma_addr); in qcom_geni_serial_start_tx_dma()
641 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); in qcom_geni_serial_start_tx_dma()
646 port->tx_remaining = xmit_size; in qcom_geni_serial_start_tx_dma()
657 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_tx_fifo()
660 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); in qcom_geni_serial_start_tx_fifo()
661 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_tx_fifo()
669 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_tx_fifo()
671 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); in qcom_geni_serial_stop_tx_fifo()
672 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_tx_fifo()
677 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_stop_tx_fifo()
680 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_stop_tx_fifo()
683 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_stop_tx_fifo()
685 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_stop_tx_fifo()
696 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); in qcom_geni_serial_handle_rx_fifo()
704 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); in qcom_geni_serial_handle_rx_fifo()
718 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
720 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
722 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
724 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_rx_fifo()
729 geni_se_cancel_s_cmd(&port->se); in qcom_geni_serial_stop_rx_fifo()
736 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_stop_rx_fifo()
740 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_stop_rx_fifo()
754 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); in qcom_geni_serial_start_rx_fifo()
756 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
758 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
760 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
762 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_rx_fifo()
772 geni_se_cancel_s_cmd(&port->se); in qcom_geni_serial_stop_rx_dma()
779 if (port->rx_dma_addr) { in qcom_geni_serial_stop_rx_dma()
780 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, in qcom_geni_serial_stop_rx_dma()
782 port->rx_dma_addr = 0; in qcom_geni_serial_stop_rx_dma()
794 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); in qcom_geni_serial_start_rx_dma()
796 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, in qcom_geni_serial_start_rx_dma()
798 &port->rx_dma_addr); in qcom_geni_serial_start_rx_dma()
800 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); in qcom_geni_serial_start_rx_dma()
814 if (!port->rx_dma_addr) in qcom_geni_serial_handle_rx_dma()
817 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); in qcom_geni_serial_handle_rx_dma()
818 port->rx_dma_addr = 0; in qcom_geni_serial_handle_rx_dma()
820 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); in qcom_geni_serial_handle_rx_dma()
822 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); in qcom_geni_serial_handle_rx_dma()
829 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, in qcom_geni_serial_handle_rx_dma()
831 &port->rx_dma_addr); in qcom_geni_serial_handle_rx_dma()
833 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); in qcom_geni_serial_handle_rx_dma()
840 uport->ops->start_rx(uport); in qcom_geni_serial_start_rx()
845 uport->ops->stop_rx(uport); in qcom_geni_serial_stop_rx()
850 uport->ops->stop_tx(uport); in qcom_geni_serial_stop_tx()
857 struct circ_buf *xmit = &uport->state->xmit; in qcom_geni_serial_send_chunk_fifo()
866 buf[c] = xmit->buf[xmit->tail]; in qcom_geni_serial_send_chunk_fifo()
870 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); in qcom_geni_serial_send_chunk_fifo()
872 remaining -= tx_bytes; in qcom_geni_serial_send_chunk_fifo()
873 port->tx_remaining -= tx_bytes; in qcom_geni_serial_send_chunk_fifo()
881 struct circ_buf *xmit = &uport->state->xmit; in qcom_geni_serial_handle_tx_fifo()
888 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); in qcom_geni_serial_handle_tx_fifo()
892 pending = port->tx_remaining; in qcom_geni_serial_handle_tx_fifo()
902 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); in qcom_geni_serial_handle_tx_fifo()
909 if (!port->tx_remaining) { in qcom_geni_serial_handle_tx_fifo()
911 port->tx_remaining = pending; in qcom_geni_serial_handle_tx_fifo()
913 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
916 uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
927 uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_handle_tx_fifo()
930 if (!port->tx_remaining) { in qcom_geni_serial_handle_tx_fifo()
931 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
934 uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx_fifo()
944 struct circ_buf *xmit = &uport->state->xmit; in qcom_geni_serial_handle_tx_dma()
946 uart_xmit_advance(uport, port->tx_remaining); in qcom_geni_serial_handle_tx_dma()
947 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); in qcom_geni_serial_handle_tx_dma()
948 port->tx_dma_addr = 0; in qcom_geni_serial_handle_tx_dma()
949 port->tx_remaining = 0; in qcom_geni_serial_handle_tx_dma()
969 struct tty_port *tport = &uport->state->port; in qcom_geni_serial_isr()
972 if (uport->suspended) in qcom_geni_serial_isr()
977 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); in qcom_geni_serial_isr()
978 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_isr()
979 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); in qcom_geni_serial_isr()
980 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); in qcom_geni_serial_isr()
981 geni_status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_isr()
982 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); in qcom_geni_serial_isr()
983 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_isr()
984 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_isr()
985 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_isr()
986 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); in qcom_geni_serial_isr()
987 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); in qcom_geni_serial_isr()
993 uport->icount.overrun++; in qcom_geni_serial_isr()
999 uport->icount.parity++; in qcom_geni_serial_isr()
1002 uport->icount.brk++; in qcom_geni_serial_isr()
1003 port->brk = true; in qcom_geni_serial_isr()
1015 uport->icount.parity++; in qcom_geni_serial_isr()
1020 uport->icount.brk++; in qcom_geni_serial_isr()
1045 u32 old_rx_fifo_depth = port->rx_fifo_depth; in setup_fifos()
1047 uport = &port->uport; in setup_fifos()
1048 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); in setup_fifos()
1049 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); in setup_fifos()
1050 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); in setup_fifos()
1051 uport->fifosize = in setup_fifos()
1052 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; in setup_fifos()
1054 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { in setup_fifos()
1060 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, in setup_fifos()
1061 port->rx_fifo_depth * sizeof(u32), in setup_fifos()
1063 if (!port->rx_buf) in setup_fifos()
1064 return -ENOMEM; in setup_fifos()
1073 disable_irq(uport->irq); in qcom_geni_serial_shutdown()
1090 proto = geni_se_read_proto(&port->se); in qcom_geni_serial_port_setup()
1092 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); in qcom_geni_serial_port_setup()
1093 return -ENXIO; in qcom_geni_serial_port_setup()
1102 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); in qcom_geni_serial_port_setup()
1104 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); in qcom_geni_serial_port_setup()
1105 if (port->rx_tx_swap) { in qcom_geni_serial_port_setup()
1109 if (port->cts_rts_swap) { in qcom_geni_serial_port_setup()
1113 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ in qcom_geni_serial_port_setup()
1114 if (port->rx_tx_swap || port->cts_rts_swap) in qcom_geni_serial_port_setup()
1115 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); in qcom_geni_serial_port_setup()
1123 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, in qcom_geni_serial_port_setup()
1125 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); in qcom_geni_serial_port_setup()
1126 geni_se_select_mode(&port->se, port->dev_data->mode); in qcom_geni_serial_port_setup()
1128 port->setup = true; in qcom_geni_serial_port_setup()
1138 if (!port->setup) { in qcom_geni_serial_startup()
1143 enable_irq(uport->irq); in qcom_geni_serial_startup()
1165 freq = clk_round_rate(clk, mult - offset); in find_clk_rate_in_tol()
1168 if (freq < mult - offset) in find_clk_rate_in_tol()
1172 * Re-calculate div in case rounding skipped rates but we in find_clk_rate_in_tol()
1178 achieved >= desired_clk - abs_tol) { in find_clk_rate_in_tol()
1230 port->baud = baud; in qcom_geni_serial_set_termios()
1234 ver = geni_se_get_qup_hw_version(&port->se); in qcom_geni_serial_set_termios()
1238 clk_rate = get_clk_div_rate(port->se.clk, baud, in qcom_geni_serial_set_termios()
1241 dev_err(port->se.dev, in qcom_geni_serial_set_termios()
1247 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", in qcom_geni_serial_set_termios()
1250 uport->uartclk = clk_rate; in qcom_geni_serial_set_termios()
1251 port->clk_rate = clk_rate; in qcom_geni_serial_set_termios()
1252 dev_pm_opp_set_rate(uport->dev, clk_rate); in qcom_geni_serial_set_termios()
1262 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; in qcom_geni_serial_set_termios()
1263 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); in qcom_geni_serial_set_termios()
1264 geni_icc_set_bw(&port->se); in qcom_geni_serial_set_termios()
1267 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_set_termios()
1268 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_set_termios()
1269 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_set_termios()
1270 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_set_termios()
1271 if (termios->c_cflag & PARENB) { in qcom_geni_serial_set_termios()
1276 if (termios->c_cflag & PARODD) { in qcom_geni_serial_set_termios()
1279 } else if (termios->c_cflag & CMSPAR) { in qcom_geni_serial_set_termios()
1294 bits_per_char = tty_get_char_size(termios->c_cflag); in qcom_geni_serial_set_termios()
1297 if (termios->c_cflag & CSTOPB) in qcom_geni_serial_set_termios()
1303 if (termios->c_cflag & CRTSCTS) in qcom_geni_serial_set_termios()
1309 uart_update_timeout(uport, termios->c_cflag, baud); in qcom_geni_serial_set_termios()
1312 writel(port->loopback, in qcom_geni_serial_set_termios()
1313 uport->membase + SE_UART_LOOPBACK_CFG); in qcom_geni_serial_set_termios()
1314 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_set_termios()
1315 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_set_termios()
1316 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_set_termios()
1317 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_set_termios()
1318 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); in qcom_geni_serial_set_termios()
1319 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); in qcom_geni_serial_set_termios()
1320 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); in qcom_geni_serial_set_termios()
1321 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); in qcom_geni_serial_set_termios()
1322 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); in qcom_geni_serial_set_termios()
1338 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) in qcom_geni_console_setup()
1339 return -ENXIO; in qcom_geni_console_setup()
1341 port = get_port_from_line(co->index, true); in qcom_geni_console_setup()
1343 pr_err("Invalid line %d\n", co->index); in qcom_geni_console_setup()
1347 uport = &port->uport; in qcom_geni_console_setup()
1349 if (unlikely(!uport->membase)) in qcom_geni_console_setup()
1350 return -ENXIO; in qcom_geni_console_setup()
1352 if (!port->setup) { in qcom_geni_console_setup()
1367 struct earlycon_device *dev = con->data; in qcom_geni_serial_earlycon_write()
1369 __qcom_geni_serial_console_write(&dev->port, s, n); in qcom_geni_serial_earlycon_write()
1376 struct earlycon_device *dev = con->data; in qcom_geni_serial_earlycon_read()
1377 struct uart_port *uport = &dev->port; in qcom_geni_serial_earlycon_read()
1395 con->read = qcom_geni_serial_earlycon_read; in qcom_geni_serial_enable_early_read()
1407 struct uart_port *uport = &dev->port; in qcom_geni_serial_earlycon_setup()
1412 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ in qcom_geni_serial_earlycon_setup()
1416 if (!uport->membase) in qcom_geni_serial_earlycon_setup()
1417 return -EINVAL; in qcom_geni_serial_earlycon_setup()
1419 uport->private_data = &earlycon_private_data; in qcom_geni_serial_earlycon_setup()
1422 se.base = uport->membase; in qcom_geni_serial_earlycon_setup()
1424 return -ENXIO; in qcom_geni_serial_earlycon_setup()
1440 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); in qcom_geni_serial_earlycon_setup()
1443 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_earlycon_setup()
1444 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_earlycon_setup()
1445 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_earlycon_setup()
1446 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_earlycon_setup()
1447 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); in qcom_geni_serial_earlycon_setup()
1448 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); in qcom_geni_serial_earlycon_setup()
1449 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); in qcom_geni_serial_earlycon_setup()
1451 dev->con->write = qcom_geni_serial_earlycon_write; in qcom_geni_serial_earlycon_setup()
1452 dev->con->setup = NULL; in qcom_geni_serial_earlycon_setup()
1453 qcom_geni_serial_enable_early_read(&se, dev->con); in qcom_geni_serial_earlycon_setup()
1457 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1476 .index = -1,
1515 geni_icc_enable(&port->se); in qcom_geni_serial_pm()
1516 if (port->clk_rate) in qcom_geni_serial_pm()
1517 dev_pm_opp_set_rate(uport->dev, port->clk_rate); in qcom_geni_serial_pm()
1518 geni_se_resources_on(&port->se); in qcom_geni_serial_pm()
1521 geni_se_resources_off(&port->se); in qcom_geni_serial_pm()
1522 dev_pm_opp_set_rate(uport->dev, 0); in qcom_geni_serial_pm()
1523 geni_icc_disable(&port->se); in qcom_geni_serial_pm()
1577 data = of_device_get_match_data(&pdev->dev); in qcom_geni_serial_probe()
1579 return -EINVAL; in qcom_geni_serial_probe()
1581 if (data->console) { in qcom_geni_serial_probe()
1583 line = of_alias_get_id(pdev->dev.of_node, "serial"); in qcom_geni_serial_probe()
1586 line = of_alias_get_id(pdev->dev.of_node, "serial"); in qcom_geni_serial_probe()
1587 if (line == -ENODEV) /* compat with non-standard aliases */ in qcom_geni_serial_probe()
1588 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); in qcom_geni_serial_probe()
1591 port = get_port_from_line(line, data->console); in qcom_geni_serial_probe()
1593 dev_err(&pdev->dev, "Invalid line %d\n", line); in qcom_geni_serial_probe()
1597 uport = &port->uport; in qcom_geni_serial_probe()
1599 if (uport->private_data) in qcom_geni_serial_probe()
1600 return -ENODEV; in qcom_geni_serial_probe()
1602 uport->dev = &pdev->dev; in qcom_geni_serial_probe()
1603 port->dev_data = data; in qcom_geni_serial_probe()
1604 port->se.dev = &pdev->dev; in qcom_geni_serial_probe()
1605 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); in qcom_geni_serial_probe()
1606 port->se.clk = devm_clk_get(&pdev->dev, "se"); in qcom_geni_serial_probe()
1607 if (IS_ERR(port->se.clk)) { in qcom_geni_serial_probe()
1608 ret = PTR_ERR(port->se.clk); in qcom_geni_serial_probe()
1609 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); in qcom_geni_serial_probe()
1615 return -EINVAL; in qcom_geni_serial_probe()
1616 uport->mapbase = res->start; in qcom_geni_serial_probe()
1618 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; in qcom_geni_serial_probe()
1619 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; in qcom_geni_serial_probe()
1620 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; in qcom_geni_serial_probe()
1622 if (!data->console) { in qcom_geni_serial_probe()
1623 port->rx_buf = devm_kzalloc(uport->dev, in qcom_geni_serial_probe()
1625 if (!port->rx_buf) in qcom_geni_serial_probe()
1626 return -ENOMEM; in qcom_geni_serial_probe()
1629 ret = geni_icc_get(&port->se, NULL); in qcom_geni_serial_probe()
1632 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; in qcom_geni_serial_probe()
1633 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in qcom_geni_serial_probe()
1636 ret = geni_icc_set_bw(&port->se); in qcom_geni_serial_probe()
1640 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, in qcom_geni_serial_probe()
1642 uart_console(uport) ? "console" : "uart", uport->line); in qcom_geni_serial_probe()
1643 if (!port->name) in qcom_geni_serial_probe()
1644 return -ENOMEM; in qcom_geni_serial_probe()
1649 uport->irq = irq; in qcom_geni_serial_probe()
1650 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); in qcom_geni_serial_probe()
1652 if (!data->console) in qcom_geni_serial_probe()
1653 port->wakeup_irq = platform_get_irq_optional(pdev, 1); in qcom_geni_serial_probe()
1655 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) in qcom_geni_serial_probe()
1656 port->rx_tx_swap = true; in qcom_geni_serial_probe()
1658 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) in qcom_geni_serial_probe()
1659 port->cts_rts_swap = true; in qcom_geni_serial_probe()
1661 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); in qcom_geni_serial_probe()
1665 ret = devm_pm_opp_of_add_table(&pdev->dev); in qcom_geni_serial_probe()
1666 if (ret && ret != -ENODEV) { in qcom_geni_serial_probe()
1667 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); in qcom_geni_serial_probe()
1671 port->private_data.drv = drv; in qcom_geni_serial_probe()
1672 uport->private_data = &port->private_data; in qcom_geni_serial_probe()
1675 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); in qcom_geni_serial_probe()
1676 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, in qcom_geni_serial_probe()
1677 IRQF_TRIGGER_HIGH, port->name, uport); in qcom_geni_serial_probe()
1679 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); in qcom_geni_serial_probe()
1687 if (port->wakeup_irq > 0) { in qcom_geni_serial_probe()
1688 device_init_wakeup(&pdev->dev, true); in qcom_geni_serial_probe()
1689 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, in qcom_geni_serial_probe()
1690 port->wakeup_irq); in qcom_geni_serial_probe()
1692 device_init_wakeup(&pdev->dev, false); in qcom_geni_serial_probe()
1704 struct uart_driver *drv = port->private_data.drv; in qcom_geni_serial_remove()
1706 dev_pm_clear_wake_irq(&pdev->dev); in qcom_geni_serial_remove()
1707 device_init_wakeup(&pdev->dev, false); in qcom_geni_serial_remove()
1708 uart_remove_one_port(drv, &port->uport); in qcom_geni_serial_remove()
1714 struct uart_port *uport = &port->uport; in qcom_geni_serial_sys_suspend()
1715 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_sys_suspend()
1722 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); in qcom_geni_serial_sys_suspend()
1723 geni_icc_set_bw(&port->se); in qcom_geni_serial_sys_suspend()
1725 return uart_suspend_port(private_data->drv, uport); in qcom_geni_serial_sys_suspend()
1732 struct uart_port *uport = &port->uport; in qcom_geni_serial_sys_resume()
1733 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_sys_resume()
1735 ret = uart_resume_port(private_data->drv, uport); in qcom_geni_serial_sys_resume()
1737 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); in qcom_geni_serial_sys_resume()
1738 geni_icc_set_bw(&port->se); in qcom_geni_serial_sys_resume()
1750 uport = &port->uport; in qcom_geni_serial_sys_hib_resume()
1751 private_data = uport->private_data; in qcom_geni_serial_sys_hib_resume()
1754 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); in qcom_geni_serial_sys_hib_resume()
1755 geni_icc_set_bw(&port->se); in qcom_geni_serial_sys_hib_resume()
1756 ret = uart_resume_port(private_data->drv, uport); in qcom_geni_serial_sys_hib_resume()
1759 * console UART won't call port setup during restore, in qcom_geni_serial_sys_hib_resume()
1760 * hence call port setup for console uart. in qcom_geni_serial_sys_hib_resume()
1767 * during next session. Clients of HS-UART will close and in qcom_geni_serial_sys_hib_resume()
1770 port->setup = false; in qcom_geni_serial_sys_hib_resume()
1796 .compatible = "qcom,geni-debug-uart",
1800 .compatible = "qcom,geni-uart",