tty/serial/pmac_zilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
25 	 * of "escc" node (ie. ch-a or ch-b)
64 	if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)  in pmz_get_port_A()
66 	return uap->mate;  in pmz_get_port_A()
78 		writeb(reg, port->control_reg);  in read_zsreg()
79 	return readb(port->control_reg);  in read_zsreg()
85 		writeb(reg, port->control_reg);  in write_zsreg()
86 	writeb(value, port->control_reg);  in write_zsreg()
91 	return readb(port->data_reg);  in read_zsdata()
96 	writeb(data, port->data_reg);  in write_zsdata()
101 	(void)readb(port->control_reg);  in zssync()
108 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
116 /* Write Register 0 */
148 /* Write Register 1 */
164 /* Write Register #2 (Interrupt Vector) */
166 /* Write Register 3 */
169 #define	SYNC_L_INH	0x2	/* Sync Character Load Inhibit */
180 /* Write Register 4 */
185 #define	SYNC_ENAB	0	/* Sync Modes Enable */
191 #define	MONSYNC		0	/* 8 Bit Sync character */
192 #define	BISYNC		0x10	/* 16 bit sync character */
193 #define	SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
194 #define	EXTSYNC		0x30	/* External Sync Mode */
202 /* Write Register 5 */
206 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
216 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
218 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
220 /* Write Register 7' (Some enhanced feature control) */
221 #define	ENEXREAD	0x40	/* Enable read of some write registers */
223 /* Write Register 8 (transmit buffer) */
225 /* Write Register 9 (Master interrupt control) */
231 #define	NORESET	0	/* No reset on write to R9 */
236 /* Write Register 10 (misc control bits) */
237 #define	BIT6	1	/* 6 bit/8bit sync */
248 /* Write Register 11 (Clock Mode control) */
264 /* Write Register 12 (lower byte of baud rate generator time constant) */
266 /* Write Register 13 (upper byte of baud rate generator time constant) */
268 /* Write Register 14 (Misc control bits) */
282 /* Write Register 15 (external/status interrupt control) */
283 #define	EN85C30	1	/* Enable some 85c30-enhanced registers */
287 #define	SYNCIE	0x10	/* Sync/hunt IE */
298 #define	SYNC_HUNT	0x10	/* Sync/hunt */
320 /* Read Register 2 (channel b only) - Interrupt vector */
361 #define ZS_IS_CONS(UP)			((UP)->flags & PMACZILOG_FLAG_IS_CONS)
362 #define ZS_IS_KGDB(UP)			((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
363 #define ZS_IS_CHANNEL_A(UP)		((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
364 #define ZS_REGS_HELD(UP)		((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
365 #define ZS_TX_STOPPED(UP)		((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
366 #define ZS_TX_ACTIVE(UP)		((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
367 #define ZS_WANTS_MODEM_STATUS(UP)	((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
368 #define ZS_IS_IRDA(UP)			((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
369 #define ZS_IS_INTMODEM(UP)		((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
370 #define ZS_IS_OPEN(UP)			((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
371 #define ZS_IS_EXTCLK(UP)		((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)