Lines Matching +full:port +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
54 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
55 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
117 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
118 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
131 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
139 * 00 -> 5 bit words
140 * 01 -> 6 bit words
141 * 10 -> 7 bit words
142 * 11 -> 8 bit words
147 * 0 -> 1 stop bit
148 * 1 -> 1-1.5 stop bits if
154 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
162 /* Flow control trigger level register masks */
163 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
164 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
168 /* FIFO interrupt trigger level register masks */
169 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
170 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
186 * 00 -> no transmitter flow
188 * 01 -> receiver compares
192 * 10 -> receiver compares
196 * 11 -> receiver compares
205 * 00 -> no received flow
207 * 01 -> transmitter generates
209 * 10 -> transmitter generates
211 * 11 -> transmitter generates
240 /* Port startup definitions */
244 /* Crystal-related definitions */
277 struct uart_port port; member
286 container_of(_port, struct max310x_one, port)
310 static u8 max310x_port_read(struct uart_port *port, u8 reg) in max310x_port_read() argument
312 struct max310x_one *one = to_max310x_port(port); in max310x_port_read()
315 regmap_read(one->regmap, reg, &val); in max310x_port_read()
320 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) in max310x_port_write() argument
322 struct max310x_one *one = to_max310x_port(port); in max310x_port_write()
324 regmap_write(one->regmap, reg, val); in max310x_port_write()
327 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) in max310x_port_update() argument
329 struct max310x_one *one = to_max310x_port(port); in max310x_port_update()
331 regmap_update_bits(one->regmap, reg, mask, val); in max310x_port_update()
340 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); in max3107_detect()
346 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max3107_detect()
347 return -ENODEV; in max3107_detect()
362 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); in max3108_detect()
367 dev_err(dev, "%s not present\n", s->devtype->name); in max3108_detect()
368 return -ENODEV; in max3108_detect()
380 ret = s->if_cfg->extended_reg_enable(dev, true); in max3109_detect()
384 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); in max3109_detect()
385 s->if_cfg->extended_reg_enable(dev, false); in max3109_detect()
388 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max3109_detect()
389 return -ENODEV; in max3109_detect()
395 static void max310x_power(struct uart_port *port, int on) in max310x_power() argument
397 max310x_port_update(port, MAX310X_MODE1_REG, in max310x_power()
410 ret = s->if_cfg->extended_reg_enable(dev, true); in max14830_detect()
414 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); in max14830_detect()
415 s->if_cfg->extended_reg_enable(dev, false); in max14830_detect()
418 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max14830_detect()
419 return -ENODEV; in max14830_detect()
425 static void max14830_power(struct uart_port *port, int on) in max14830_power() argument
427 max310x_port_update(port, MAX310X_BRGCFG_REG, in max14830_power()
541 static int max310x_set_baud(struct uart_port *port, int baud) in max310x_set_baud() argument
547 * in case if the requested baud is too high for the pre-defined in max310x_set_baud()
550 div = port->uartclk / baud; in max310x_set_baud()
569 frac = (16*(port->uartclk % F)) / F; in max310x_set_baud()
573 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); in max310x_set_baud()
574 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); in max310x_set_baud()
575 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); in max310x_set_baud()
578 return (16*port->uartclk) / (c*(16*div + frac)); in max310x_set_baud()
598 long besterr = -1; in max310x_set_ref_clk()
644 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); in max310x_set_ref_clk()
648 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); in max310x_set_ref_clk()
657 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); in max310x_set_ref_clk()
664 return dev_err_probe(dev, -EAGAIN, in max310x_set_ref_clk()
671 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) in max310x_batch_write() argument
673 struct max310x_one *one = to_max310x_port(port); in max310x_batch_write()
675 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len); in max310x_batch_write()
678 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) in max310x_batch_read() argument
680 struct max310x_one *one = to_max310x_port(port); in max310x_batch_read()
682 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); in max310x_batch_read()
685 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) in max310x_handle_rx() argument
687 struct max310x_one *one = to_max310x_port(port); in max310x_handle_rx()
691 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { in max310x_handle_rx()
693 * Break condition, parity checking, framing errors -- they in max310x_handle_rx()
694 * are all ignored. That means that we can do a batch-read. in max310x_handle_rx()
703 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); in max310x_handle_rx()
704 max310x_batch_read(port, one->rx_buf, rxlen); in max310x_handle_rx()
706 port->icount.rx += rxlen; in max310x_handle_rx()
708 sts &= port->read_status_mask; in max310x_handle_rx()
711 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); in max310x_handle_rx()
712 port->icount.overrun++; in max310x_handle_rx()
715 for (i = 0; i < (rxlen - 1); ++i) in max310x_handle_rx()
716 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); in max310x_handle_rx()
723 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, in max310x_handle_rx()
724 one->rx_buf[rxlen-1], flag); in max310x_handle_rx()
727 if (unlikely(rxlen >= port->fifosize)) { in max310x_handle_rx()
728 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); in max310x_handle_rx()
729 port->icount.buf_overrun++; in max310x_handle_rx()
730 /* Ensure sanity of RX level */ in max310x_handle_rx()
731 rxlen = port->fifosize; in max310x_handle_rx()
734 while (rxlen--) { in max310x_handle_rx()
735 ch = max310x_port_read(port, MAX310X_RHR_REG); in max310x_handle_rx()
736 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); in max310x_handle_rx()
741 port->icount.rx++; in max310x_handle_rx()
746 port->icount.brk++; in max310x_handle_rx()
747 if (uart_handle_break(port)) in max310x_handle_rx()
750 port->icount.parity++; in max310x_handle_rx()
752 port->icount.frame++; in max310x_handle_rx()
754 port->icount.overrun++; in max310x_handle_rx()
756 sts &= port->read_status_mask; in max310x_handle_rx()
767 if (uart_handle_sysrq_char(port, ch)) in max310x_handle_rx()
770 if (sts & port->ignore_status_mask) in max310x_handle_rx()
773 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); in max310x_handle_rx()
777 tty_flip_buffer_push(&port->state->port); in max310x_handle_rx()
780 static void max310x_handle_tx(struct uart_port *port) in max310x_handle_tx() argument
782 struct circ_buf *xmit = &port->state->xmit; in max310x_handle_tx()
785 if (unlikely(port->x_char)) { in max310x_handle_tx()
786 max310x_port_write(port, MAX310X_THR_REG, port->x_char); in max310x_handle_tx()
787 port->icount.tx++; in max310x_handle_tx()
788 port->x_char = 0; in max310x_handle_tx()
792 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) in max310x_handle_tx()
797 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in max310x_handle_tx()
800 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); in max310x_handle_tx()
801 txlen = port->fifosize - txlen; in max310x_handle_tx()
805 /* It's a circ buffer -- wrap around. in max310x_handle_tx()
807 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); in max310x_handle_tx()
808 max310x_batch_write(port, xmit->buf, to_send - until_end); in max310x_handle_tx()
810 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); in max310x_handle_tx()
812 uart_xmit_advance(port, to_send); in max310x_handle_tx()
816 uart_write_wakeup(port); in max310x_handle_tx()
819 static void max310x_start_tx(struct uart_port *port) in max310x_start_tx() argument
821 struct max310x_one *one = to_max310x_port(port); in max310x_start_tx()
823 schedule_work(&one->tx_work); in max310x_start_tx()
828 struct uart_port *port = &s->p[portno].port; in max310x_port_irq() local
834 /* Read IRQ status & RX FIFO level */ in max310x_port_irq()
835 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); in max310x_port_irq()
836 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); in max310x_port_irq()
843 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); in max310x_port_irq()
844 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); in max310x_port_irq()
847 max310x_handle_rx(port, rxlen); in max310x_port_irq()
849 max310x_start_tx(port); in max310x_port_irq()
859 if (s->devtype->nr > 1) { in max310x_ist()
863 WARN_ON_ONCE(regmap_read(s->regmap, in max310x_ist()
865 val = ((1 << s->devtype->nr) - 1) & ~val; in max310x_ist()
868 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) in max310x_ist()
883 max310x_handle_tx(&one->port); in max310x_tx_proc()
886 static unsigned int max310x_tx_empty(struct uart_port *port) in max310x_tx_empty() argument
888 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); in max310x_tx_empty()
893 static unsigned int max310x_get_mctrl(struct uart_port *port) in max310x_get_mctrl() argument
905 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_md_proc()
907 (one->port.mctrl & TIOCM_LOOP) ? in max310x_md_proc()
911 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) in max310x_set_mctrl() argument
913 struct max310x_one *one = to_max310x_port(port); in max310x_set_mctrl()
915 schedule_work(&one->md_work); in max310x_set_mctrl()
918 static void max310x_break_ctl(struct uart_port *port, int break_state) in max310x_break_ctl() argument
920 max310x_port_update(port, MAX310X_LCR_REG, in max310x_break_ctl()
925 static void max310x_set_termios(struct uart_port *port, in max310x_set_termios() argument
933 termios->c_cflag &= ~CMSPAR; in max310x_set_termios()
936 switch (termios->c_cflag & CSIZE) { in max310x_set_termios()
952 if (termios->c_cflag & PARENB) { in max310x_set_termios()
954 if (!(termios->c_cflag & PARODD)) in max310x_set_termios()
959 if (termios->c_cflag & CSTOPB) in max310x_set_termios()
963 max310x_port_write(port, MAX310X_LCR_REG, lcr); in max310x_set_termios()
966 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; in max310x_set_termios()
967 if (termios->c_iflag & INPCK) in max310x_set_termios()
968 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
970 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in max310x_set_termios()
971 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
974 port->ignore_status_mask = 0; in max310x_set_termios()
975 if (termios->c_iflag & IGNBRK) in max310x_set_termios()
976 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
977 if (!(termios->c_cflag & CREAD)) in max310x_set_termios()
978 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
984 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); in max310x_set_termios()
985 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); in max310x_set_termios()
990 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { in max310x_set_termios()
991 max310x_port_update(port, MAX310X_MODE1_REG, in max310x_set_termios()
996 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); in max310x_set_termios()
998 if (termios->c_cflag & CRTSCTS) { in max310x_set_termios()
1000 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in max310x_set_termios()
1004 if (termios->c_iflag & IXON) in max310x_set_termios()
1007 if (termios->c_iflag & IXOFF) { in max310x_set_termios()
1008 port->status |= UPSTAT_AUTOXOFF; in max310x_set_termios()
1012 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); in max310x_set_termios()
1017 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { in max310x_set_termios()
1018 max310x_port_update(port, MAX310X_MODE1_REG, in max310x_set_termios()
1024 baud = uart_get_baud_rate(port, termios, old, in max310x_set_termios()
1025 port->uartclk / 16 / 0xffff, in max310x_set_termios()
1026 port->uartclk / 4); in max310x_set_termios()
1029 baud = max310x_set_baud(port, baud); in max310x_set_termios()
1032 uart_update_timeout(port, termios->c_cflag, baud); in max310x_set_termios()
1040 delay = (one->port.rs485.delay_rts_before_send << 4) | in max310x_rs_proc()
1041 one->port.rs485.delay_rts_after_send; in max310x_rs_proc()
1042 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); in max310x_rs_proc()
1044 if (one->port.rs485.flags & SER_RS485_ENABLED) { in max310x_rs_proc()
1047 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) in max310x_rs_proc()
1051 max310x_port_update(&one->port, MAX310X_MODE1_REG, in max310x_rs_proc()
1053 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_rs_proc()
1057 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios, in max310x_rs485_config() argument
1060 struct max310x_one *one = to_max310x_port(port); in max310x_rs485_config()
1062 if ((rs485->delay_rts_before_send > 0x0f) || in max310x_rs485_config()
1063 (rs485->delay_rts_after_send > 0x0f)) in max310x_rs485_config()
1064 return -ERANGE; in max310x_rs485_config()
1066 port->rs485 = *rs485; in max310x_rs485_config()
1068 schedule_work(&one->rs_work); in max310x_rs485_config()
1073 static int max310x_startup(struct uart_port *port) in max310x_startup() argument
1075 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_startup()
1078 s->devtype->power(port, 1); in max310x_startup()
1081 max310x_port_update(port, MAX310X_MODE1_REG, in max310x_startup()
1086 max310x_port_write(port, MAX310X_MODE2_REG, val); in max310x_startup()
1087 max310x_port_update(port, MAX310X_MODE2_REG, in max310x_startup()
1091 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | in max310x_startup()
1092 clamp(port->rs485.delay_rts_after_send, 0U, 15U); in max310x_startup()
1093 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); in max310x_startup()
1095 if (port->rs485.flags & SER_RS485_ENABLED) { in max310x_startup()
1096 max310x_port_update(port, MAX310X_MODE1_REG, in max310x_startup()
1100 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in max310x_startup()
1101 max310x_port_update(port, MAX310X_MODE2_REG, in max310x_startup()
1107 /* Flow control halt level 96, resume level 48 */ in max310x_startup()
1108 max310x_port_write(port, MAX310X_FLOWLVL_REG, in max310x_startup()
1112 max310x_port_read(port, MAX310X_IRQSTS_REG); in max310x_startup()
1116 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); in max310x_startup()
1121 static void max310x_shutdown(struct uart_port *port) in max310x_shutdown() argument
1123 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_shutdown()
1126 max310x_port_write(port, MAX310X_IRQEN_REG, 0); in max310x_shutdown()
1128 s->devtype->power(port, 0); in max310x_shutdown()
1131 static const char *max310x_type(struct uart_port *port) in max310x_type() argument
1133 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_type()
1135 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; in max310x_type()
1138 static int max310x_request_port(struct uart_port *port) in max310x_request_port() argument
1144 static void max310x_config_port(struct uart_port *port, int flags) in max310x_config_port() argument
1147 port->type = PORT_MAX310X; in max310x_config_port()
1150 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) in max310x_verify_port() argument
1152 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) in max310x_verify_port()
1153 return -EINVAL; in max310x_verify_port()
1154 if (s->irq != port->irq) in max310x_verify_port()
1155 return -EINVAL; in max310x_verify_port()
1160 static void max310x_null_void(struct uart_port *port) in max310x_null_void() argument
1188 for (i = 0; i < s->devtype->nr; i++) { in max310x_suspend()
1189 uart_suspend_port(&max310x_uart, &s->p[i].port); in max310x_suspend()
1190 s->devtype->power(&s->p[i].port, 0); in max310x_suspend()
1201 for (i = 0; i < s->devtype->nr; i++) { in max310x_resume()
1202 s->devtype->power(&s->p[i].port, 1); in max310x_resume()
1203 uart_resume_port(&max310x_uart, &s->p[i].port); in max310x_resume()
1216 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_get() local
1218 val = max310x_port_read(port, MAX310X_GPIODATA_REG); in max310x_gpio_get()
1226 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set() local
1228 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), in max310x_gpio_set()
1235 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_input() local
1237 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); in max310x_gpio_direction_input()
1246 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_output() local
1248 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), in max310x_gpio_direction_output()
1250 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), in max310x_gpio_direction_output()
1260 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set_config() local
1264 max310x_port_update(port, MAX310X_GPIOCFG_REG, in max310x_gpio_set_config()
1269 max310x_port_update(port, MAX310X_GPIOCFG_REG, in max310x_gpio_set_config()
1273 return -ENOTSUPP; in max310x_gpio_set_config()
1293 for (i = 0; i < devtype->nr; i++) in max310x_probe()
1297 /* Alloc port structure */ in max310x_probe()
1298 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); in max310x_probe()
1300 dev_err(dev, "Error allocating port structure\n"); in max310x_probe()
1301 return -ENOMEM; in max310x_probe()
1305 device_property_read_u32(dev, "clock-frequency", &uartclk); in max310x_probe()
1307 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; in max310x_probe()
1309 s->clk = devm_clk_get_optional(dev, "xtal"); in max310x_probe()
1311 s->clk = devm_clk_get_optional(dev, "osc"); in max310x_probe()
1312 if (IS_ERR(s->clk)) in max310x_probe()
1313 return PTR_ERR(s->clk); in max310x_probe()
1315 ret = clk_prepare_enable(s->clk); in max310x_probe()
1319 freq = clk_get_rate(s->clk); in max310x_probe()
1324 ret = -EINVAL; in max310x_probe()
1338 ret = -ERANGE; in max310x_probe()
1342 s->regmap = regmaps[0]; in max310x_probe()
1343 s->devtype = devtype; in max310x_probe()
1344 s->if_cfg = if_cfg; in max310x_probe()
1348 ret = devtype->detect(dev); in max310x_probe()
1352 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1356 /* Reset port */ in max310x_probe()
1359 /* Clear port reset */ in max310x_probe()
1362 /* Wait for port startup */ in max310x_probe()
1372 ret = dev_err_probe(dev, -EAGAIN, "port reset failed\n"); in max310x_probe()
1376 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); in max310x_probe()
1387 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1392 ret = -ERANGE; in max310x_probe()
1396 /* Initialize port data */ in max310x_probe()
1397 s->p[i].port.line = line; in max310x_probe()
1398 s->p[i].port.dev = dev; in max310x_probe()
1399 s->p[i].port.irq = irq; in max310x_probe()
1400 s->p[i].port.type = PORT_MAX310X; in max310x_probe()
1401 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; in max310x_probe()
1402 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; in max310x_probe()
1403 s->p[i].port.iotype = UPIO_PORT; in max310x_probe()
1404 s->p[i].port.iobase = i; in max310x_probe()
1410 s->p[i].port.membase = (void __iomem *)~0; in max310x_probe()
1411 s->p[i].port.uartclk = uartclk; in max310x_probe()
1412 s->p[i].port.rs485_config = max310x_rs485_config; in max310x_probe()
1413 s->p[i].port.rs485_supported = max310x_rs485_supported; in max310x_probe()
1414 s->p[i].port.ops = &max310x_ops; in max310x_probe()
1415 s->p[i].regmap = regmaps[i]; in max310x_probe()
1418 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); in max310x_probe()
1420 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); in max310x_probe()
1422 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); in max310x_probe()
1424 INIT_WORK(&s->p[i].md_work, max310x_md_proc); in max310x_probe()
1426 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); in max310x_probe()
1428 /* Register port */ in max310x_probe()
1429 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); in max310x_probe()
1431 s->p[i].port.dev = NULL; in max310x_probe()
1437 devtype->power(&s->p[i].port, 0); in max310x_probe()
1442 s->gpio.owner = THIS_MODULE; in max310x_probe()
1443 s->gpio.parent = dev; in max310x_probe()
1444 s->gpio.label = devtype->name; in max310x_probe()
1445 s->gpio.direction_input = max310x_gpio_direction_input; in max310x_probe()
1446 s->gpio.get = max310x_gpio_get; in max310x_probe()
1447 s->gpio.direction_output= max310x_gpio_direction_output; in max310x_probe()
1448 s->gpio.set = max310x_gpio_set; in max310x_probe()
1449 s->gpio.set_config = max310x_gpio_set_config; in max310x_probe()
1450 s->gpio.base = -1; in max310x_probe()
1451 s->gpio.ngpio = devtype->nr * 4; in max310x_probe()
1452 s->gpio.can_sleep = 1; in max310x_probe()
1453 ret = devm_gpiochip_add_data(dev, &s->gpio, s); in max310x_probe()
1467 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1468 if (s->p[i].port.dev) { in max310x_probe()
1469 uart_remove_one_port(&max310x_uart, &s->p[i].port); in max310x_probe()
1470 clear_bit(s->p[i].port.line, max310x_lines); in max310x_probe()
1475 clk_disable_unprepare(s->clk); in max310x_probe()
1485 for (i = 0; i < s->devtype->nr; i++) { in max310x_remove()
1486 cancel_work_sync(&s->p[i].tx_work); in max310x_remove()
1487 cancel_work_sync(&s->p[i].md_work); in max310x_remove()
1488 cancel_work_sync(&s->p[i].rs_work); in max310x_remove()
1489 uart_remove_one_port(&max310x_uart, &s->p[i].port); in max310x_remove()
1490 clear_bit(s->p[i].port.line, max310x_lines); in max310x_remove()
1491 s->devtype->power(&s->p[i].port, 0); in max310x_remove()
1494 clk_disable_unprepare(s->clk); in max310x_remove()
1526 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, in max310x_spi_extended_reg_enable()
1543 spi->bits_per_word = 8; in max310x_spi_probe()
1544 spi->mode = spi->mode ? : SPI_MODE_0; in max310x_spi_probe()
1545 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; in max310x_spi_probe()
1550 devtype = device_get_match_data(&spi->dev); in max310x_spi_probe()
1552 devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data; in max310x_spi_probe()
1554 for (i = 0; i < devtype->nr; i++) { in max310x_spi_probe()
1561 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); in max310x_spi_probe()
1566 max310x_remove(&spi->dev); in max310x_spi_remove()
1623 * UART1 - UART0 = 0x10 in max310x_i2c_slave_addr()
1624 * UART2 - UART1 = 0x20 + 0x10 in max310x_i2c_slave_addr()
1625 * UART3 - UART2 = 0x10 in max310x_i2c_slave_addr()
1628 addr -= nr * 0x10; in max310x_i2c_slave_addr()
1631 addr -= 0x20; in max310x_i2c_slave_addr()
1639 device_get_match_data(&client->dev); in max310x_i2c_probe()
1645 if (client->addr < devtype->slave_addr.min || in max310x_i2c_probe()
1646 client->addr > devtype->slave_addr.max) in max310x_i2c_probe()
1647 return dev_err_probe(&client->dev, -EINVAL, in max310x_i2c_probe()
1649 client->addr, devtype->slave_addr.min, in max310x_i2c_probe()
1650 devtype->slave_addr.max); in max310x_i2c_probe()
1654 for (i = 1; i < devtype->nr; i++) { in max310x_i2c_probe()
1655 port_addr = max310x_i2c_slave_addr(client->addr, i); in max310x_i2c_probe()
1656 port_client = devm_i2c_new_dummy_device(&client->dev, in max310x_i2c_probe()
1657 client->adapter, in max310x_i2c_probe()
1663 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, in max310x_i2c_probe()
1664 regmaps, client->irq); in max310x_i2c_probe()
1669 max310x_remove(&client->dev); in max310x_i2c_remove()