tty/serial/ip22zilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
38 /* Write Register 0 */
60 #define	RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
69 /* Write Register 1 */
76 #define	RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
77 #define	INT_ALL_Rx	0x10	/* Int on all Rx Characters or error */
78 #define	INT_ERR_Rx	0x18	/* Int on error only */
81 #define	WT_RDY_RT	0x20	/* Wait/Ready on R/T */
82 #define	WT_FN_RDYFN	0x40	/* Wait/FN/Ready FN */
83 #define	WT_RDY_ENAB	0x80	/* Wait/Ready Enable */
85 /* Write Register #2 (Interrupt Vector) */
87 /* Write Register 3 */
101 /* Write Register 4 */
122 /* Write Register 5 */
126 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
140 /* Write Register 8 (transmit buffer) */
142 /* Write Register 9 (Master interrupt control) */
148 #define	NORESET	0	/* No reset on write to R9 */
153 /* Write Register 10 (misc control bits) */
156 #define	ABUNDER	4	/* Abort/flag on SDLC xmit underrun */
157 #define	MARKIDLE 8	/* Mark/flag on idle */
158 #define	GAOP	0x10	/* Go active on poll */
165 /* Write Register 11 (Clock Mode control) */
181 /* Write Register 12 (lower byte of baud rate generator time constant) */
183 /* Write Register 13 (upper byte of baud rate generator time constant) */
185 /* Write Register 14 (Misc control bits) */
199 /* Write Register 15 (external/status interrupt control) */
235 /* Read Register 2 (channel b only) - Interrupt vector */
257 #define	ONLOOP	2		/* On loop */
269 #define ZS_CLEARERR(channel)    do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel)   do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel)   do { readb(&channel->data); \
277 				     readb(&channel->data); \
279 				     readb(&channel->data); \