Lines Matching +full:sync +full:- +full:read

1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
90 #define	SYNC_L_INH	0x2	/* Sync Character Load Inhibit */
106 #define	SYNC_ENAB	0	/* Sync Modes Enable */
111 #define	MONSYNC		0	/* 8 Bit Sync character */
112 #define	BISYNC		0x10	/* 16 bit sync character */
113 #define	SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
114 #define	EXTSYNC		0x30	/* External Sync Mode */
126 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
154 #define	BIT6	1	/* 6 bit/8bit sync */
202 #define	SYNCIE	0x10	/* Sync/hunt IE */
208 /* Read Register 0 */
213 #define	SYNC		0x10	/* Sync/hunt */  macro
218 /* Read Register 1 */
235 /* Read Register 2 (channel b only) - Interrupt vector */
246 /* Read Register 3 (interrupt pending register) ch a only */
254 /* Read Register 8 (receive data register) */
256 /* Read Register 10  (misc status bits) */
262 /* Read Register 12 (lower byte of baud rate generator constant) */
264 /* Read Register 13 (upper byte of baud rate generator constant) */
266 /* Read Register 15 (value of WR 15) */
269 #define ZS_CLEARERR(channel)    do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel)   do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel)   do { readb(&channel->data); \
277 				     readb(&channel->data); \
279 				     readb(&channel->data); \