Lines Matching +full:rs485 +full:- +full:rts +full:- +full:active +full:- +full:low
1 // SPDX-License-Identifier: GPL-2.0+
29 #include <linux/dma-mapping.h>
32 #include <linux/dma/imx-dma.h>
73 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
81 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
123 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
126 #define USR1_RTSS (1<<14) /* RTS pin status */
128 #define USR1_RTSD (1<<12) /* RTS delta */
146 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
159 /* We've been assigned a range on the "Low-density serial ports" major */
172 #define DRIVER_NAME "IMX-uart"
254 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
255 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
258 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
259 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
260 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
267 writel(val, sport->port.membase + offset); in imx_uart_writel()
272 return readl(sport->port.membase + offset); in imx_uart_readl()
277 return sport->devdata->uts_reg; in imx_uart_uts_reg()
282 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
293 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
294 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
295 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
302 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
303 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
304 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
313 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); in imx_uart_rts_active()
322 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); in imx_uart_rts_inactive()
341 * and UTS[6-3]". in imx_uart_soft_reset()
354 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_soft_reset()
362 sport->idle_counter = 0; in imx_uart_soft_reset()
386 if (sport->dma_is_enabled) { in imx_uart_start_rx()
405 if (sport->tx_state == OFF) in imx_uart_stop_tx()
412 if (sport->dma_is_txing) in imx_uart_stop_tx()
428 /* in rs485 mode disable transmitter */ in imx_uart_stop_tx()
429 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
430 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
431 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
433 if (port->rs485.delay_rts_after_send > 0) { in imx_uart_stop_tx()
434 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
435 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
442 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
443 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
446 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
449 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
455 if (!port->rs485_rx_during_tx_gpio) in imx_uart_stop_tx()
458 sport->tx_state = OFF; in imx_uart_stop_tx()
461 sport->tx_state = OFF; in imx_uart_stop_tx()
474 if (sport->dma_is_enabled) { in imx_uart_stop_rx_with_loopback_ctrl()
485 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_stop_rx_with_loopback_ctrl()
486 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_stop_rx_with_loopback_ctrl()
487 sport->have_rtscts && !sport->have_rtsgpio && loopback) { in imx_uart_stop_rx_with_loopback_ctrl()
503 * Stop RX and enable loopback in order to make sure RS485 bus in imx_uart_stop_rx()
514 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
516 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
524 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
526 if (sport->port.x_char) { in imx_uart_transmit_buffer()
528 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
529 sport->port.icount.tx++; in imx_uart_transmit_buffer()
530 sport->port.x_char = 0; in imx_uart_transmit_buffer()
534 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
535 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
539 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
542 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
547 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
560 /* send xmit->buf[xmit->tail] in imx_uart_transmit_buffer()
562 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
563 uart_xmit_advance(&sport->port, 1); in imx_uart_transmit_buffer()
567 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
570 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
576 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
577 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
581 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_dma_tx_callback()
583 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
589 uart_xmit_advance(&sport->port, sport->tx_bytes); in imx_uart_dma_tx_callback()
591 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
593 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
596 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
598 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
600 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
606 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_dma_tx_callback()
612 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
613 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
615 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
616 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
620 if (sport->dma_is_txing) in imx_uart_dma_tx()
627 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
629 if (xmit->tail < xmit->head || xmit->head == 0) { in imx_uart_dma_tx()
630 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
631 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
633 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
635 sg_set_buf(sgl, xmit->buf + xmit->tail, in imx_uart_dma_tx()
636 UART_XMIT_SIZE - xmit->tail); in imx_uart_dma_tx()
637 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in imx_uart_dma_tx()
640 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
648 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
653 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
654 desc->callback_param = sport; in imx_uart_dma_tx()
664 sport->dma_is_txing = 1; in imx_uart_dma_tx()
676 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
680 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
685 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
686 if (sport->tx_state == OFF) { in imx_uart_start_tx()
688 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
699 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && in imx_uart_start_tx()
700 !port->rs485_rx_during_tx_gpio) in imx_uart_start_tx()
703 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
705 if (port->rs485.delay_rts_before_send > 0) { in imx_uart_start_tx()
706 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
707 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
714 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
715 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
717 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
722 * tx-callback. in imx_uart_start_tx()
724 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
730 sport->tx_state = SEND; in imx_uart_start_tx()
733 sport->tx_state = SEND; in imx_uart_start_tx()
736 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
741 if (sport->dma_is_enabled) { in imx_uart_start_tx()
742 if (sport->port.x_char) { in imx_uart_start_tx()
743 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
744 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
752 if (!uart_circ_empty(&port->state->xmit) && in imx_uart_start_tx()
766 uart_handle_cts_change(&sport->port, usr1); in __imx_uart_rtsint()
767 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
777 uart_port_lock(&sport->port); in imx_uart_rtsint()
781 uart_port_unlock(&sport->port); in imx_uart_rtsint()
790 uart_port_lock(&sport->port); in imx_uart_txint()
792 uart_port_unlock(&sport->port); in imx_uart_txint()
830 * We count interrupts, not chars in 'idle-counter' for simplicity. in imx_uart_check_flood()
835 sport->idle_counter = 0; in imx_uart_check_flood()
836 } else if (++sport->idle_counter > 3) { in imx_uart_check_flood()
837 dev_warn(sport->port.dev, "RX flood detected: soft reset."); in imx_uart_check_flood()
838 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ in imx_uart_check_flood()
845 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
855 sport->port.icount.rx++; in __imx_uart_rxint()
859 sport->port.icount.brk++; in __imx_uart_rxint()
860 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
864 sport->port.icount.parity++; in __imx_uart_rxint()
866 sport->port.icount.frame++; in __imx_uart_rxint()
868 sport->port.icount.overrun++; in __imx_uart_rxint()
870 if (rx & sport->port.ignore_status_mask) in __imx_uart_rxint()
873 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
884 sport->port.sysrq = 0; in __imx_uart_rxint()
885 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) { in __imx_uart_rxint()
889 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
893 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
906 uart_port_lock(&sport->port); in imx_uart_rxint()
910 uart_port_unlock(&sport->port); in imx_uart_rxint()
918 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
933 if (sport->dte_mode) in imx_uart_get_hwmctrl()
948 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
953 sport->old_status = status; in imx_uart_mctrl_check()
956 sport->port.icount.rng++; in imx_uart_mctrl_check()
958 sport->port.icount.dsr++; in imx_uart_mctrl_check()
960 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
962 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
964 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
973 uart_port_lock(&sport->port); in imx_uart_int()
1038 sport->port.icount.overrun++; in imx_uart_int()
1043 uart_port_unlock(&sport->port); in imx_uart_int()
1059 if (sport->dma_is_txing) in imx_uart_tx_empty()
1071 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1082 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1086 * Turn off autoRTS if RTS is lowered and restore autoRTS in imx_uart_set_mctrl()
1087 * setting if RTS is raised. in imx_uart_set_mctrl()
1114 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1126 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_break_ctl()
1135 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_break_ctl()
1139 * This is our per-port timeout handler, for checking the
1147 if (sport->port.state) { in imx_uart_timeout()
1148 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_timeout()
1150 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_timeout()
1152 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1167 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1168 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1169 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1171 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1177 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1180 uart_port_lock(&sport->port); in imx_uart_dma_rx_callback()
1182 uart_port_unlock(&sport->port); in imx_uart_dma_rx_callback()
1187 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1190 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1192 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1198 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1201 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1202 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1204 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1205 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1208 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1211 uart_port_lock(&sport->port); in imx_uart_dma_rx_callback()
1213 uart_port_unlock(&sport->port); in imx_uart_dma_rx_callback()
1215 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1218 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1222 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1225 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1229 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1231 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1234 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1235 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1240 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1246 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1247 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1248 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1252 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1253 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1255 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1259 return -EINVAL; in imx_uart_start_rx_dma()
1263 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1269 return -EINVAL; in imx_uart_start_rx_dma()
1271 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1272 desc->callback_param = sport; in imx_uart_start_rx_dma()
1275 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1276 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1283 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1290 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1292 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1294 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1298 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1301 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1307 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1311 sport->idle_counter = 0; in imx_uart_clear_rx_errors()
1333 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1334 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1335 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1336 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1337 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1338 kfree(sport->rx_buf); in imx_uart_dma_exit()
1339 sport->rx_buf = NULL; in imx_uart_dma_exit()
1342 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1343 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1344 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1345 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1352 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1360 sport->dma_chan_rx = NULL; in imx_uart_dma_init()
1364 sport->dma_chan_rx = chan; in imx_uart_dma_init()
1367 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1370 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1371 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1377 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1378 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1379 if (!sport->rx_buf) { in imx_uart_dma_init()
1380 ret = -ENOMEM; in imx_uart_dma_init()
1383 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1389 sport->dma_chan_tx = NULL; in imx_uart_dma_init()
1393 sport->dma_chan_tx = chan; in imx_uart_dma_init()
1396 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1399 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1422 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1436 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1450 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1453 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1455 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1474 lockdep_set_subclass(&port->lock, 1); in imx_uart_startup()
1478 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_startup()
1491 if (sport->have_rtscts) in imx_uart_startup()
1499 if (sport->inverted_rx) in imx_uart_startup()
1507 if (sport->inverted_tx) in imx_uart_startup()
1513 if (sport->dte_mode) in imx_uart_startup()
1521 if (!sport->have_rtscts) in imx_uart_startup()
1524 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1534 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1551 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_startup()
1562 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1563 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1564 if (sport->dma_is_txing) { in imx_uart_shutdown()
1565 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1566 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1567 sport->dma_is_txing = 0; in imx_uart_shutdown()
1569 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1570 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1571 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1573 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1576 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1580 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1584 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1586 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1590 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1595 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1601 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_shutdown()
1607 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_shutdown()
1608 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_shutdown()
1609 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_shutdown()
1623 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_shutdown()
1625 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1626 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1633 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1635 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1638 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1639 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1640 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1643 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1648 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1663 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1671 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1672 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1673 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1674 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1678 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1683 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1686 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_set_termios()
1696 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1699 if (!sport->have_rtscts) in imx_uart_set_termios()
1700 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1702 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1704 * RTS is mandatory for rs485 operation, so keep in imx_uart_set_termios()
1708 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1713 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1715 * Only let receiver control RTS output if we were not requested in imx_uart_set_termios()
1716 * to have RTS inactive (which then should take precedence). in imx_uart_set_termios()
1722 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1724 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1726 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1728 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1732 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1733 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1734 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1735 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1736 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1741 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1742 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1743 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1744 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1745 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1750 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1751 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1754 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1755 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1758 * Update the per-port timeout. in imx_uart_set_termios()
1760 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1762 /* custom-baudrate handling */ in imx_uart_set_termios()
1763 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1765 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1767 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1773 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1776 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1782 num -= 1; in imx_uart_set_termios()
1783 denom -= 1; in imx_uart_set_termios()
1796 * RTS/CTS handshake and suddenly gets broken bytes. in imx_uart_set_termios()
1806 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1811 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1812 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1814 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_set_termios()
1819 return port->type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1828 port->type = PORT_IMX; in imx_uart_config_port()
1841 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1842 ret = -EINVAL; in imx_uart_verify_port()
1843 if (port->irq != ser->irq) in imx_uart_verify_port()
1844 ret = -EINVAL; in imx_uart_verify_port()
1845 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1846 ret = -EINVAL; in imx_uart_verify_port()
1847 if (port->uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1848 ret = -EINVAL; in imx_uart_verify_port()
1849 if (port->mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1850 ret = -EINVAL; in imx_uart_verify_port()
1851 if (port->iobase != ser->port) in imx_uart_verify_port()
1852 ret = -EINVAL; in imx_uart_verify_port()
1853 if (ser->hub6 != 0) in imx_uart_verify_port()
1854 ret = -EINVAL; in imx_uart_verify_port()
1867 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1870 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1872 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1876 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_poll_init()
1904 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_poll_init()
1945 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
1946 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
1947 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1948 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
1949 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
1953 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
1960 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
1961 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
1962 rs485conf->flags & SER_RS485_RX_DURING_TX) in imx_uart_rs485_config()
2010 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write()
2016 if (sport->port.sysrq) in imx_uart_console_write()
2019 locked = uart_port_trylock_irqsave(&sport->port, &flags); in imx_uart_console_write()
2021 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_console_write()
2038 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2049 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_console_write()
2089 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2091 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2110 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2130 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2131 co->index = 0; in imx_uart_console_setup()
2132 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2134 return -ENODEV; in imx_uart_console_setup()
2137 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2148 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2151 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2155 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2157 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2166 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_exit()
2168 clk_disable_unprepare(sport->clk_per); in imx_uart_console_exit()
2169 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_exit()
2182 .index = -1,
2207 uart_port_lock_irqsave(&sport->port, &flags); in imx_trigger_start_tx()
2208 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2209 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2210 uart_port_unlock_irqrestore(&sport->port, flags); in imx_trigger_start_tx()
2220 uart_port_lock_irqsave(&sport->port, &flags); in imx_trigger_stop_tx()
2221 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2222 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2223 uart_port_unlock_irqrestore(&sport->port, flags); in imx_trigger_stop_tx()
2241 struct device_node *np = pdev->dev.of_node; in imx_uart_probe()
2250 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2252 return -ENOMEM; in imx_uart_probe()
2254 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2258 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe()
2261 sport->port.line = ret; in imx_uart_probe()
2263 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") || in imx_uart_probe()
2264 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */ in imx_uart_probe()
2266 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode"); in imx_uart_probe()
2268 sport->have_rtsgpio = of_property_present(np, "rts-gpios"); in imx_uart_probe()
2270 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx"); in imx_uart_probe()
2272 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx"); in imx_uart_probe()
2274 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { in imx_uart_probe()
2275 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2276 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2278 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2279 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2282 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2283 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2284 sport->port.line); in imx_uart_probe()
2285 return -EINVAL; in imx_uart_probe()
2298 sport->port.dev = &pdev->dev; in imx_uart_probe()
2299 sport->port.mapbase = res->start; in imx_uart_probe()
2300 sport->port.membase = base; in imx_uart_probe()
2301 sport->port.type = PORT_IMX; in imx_uart_probe()
2302 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2303 sport->port.irq = rxirq; in imx_uart_probe()
2304 sport->port.fifosize = 32; in imx_uart_probe()
2305 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2306 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2307 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2308 /* RTS is required to control the RS485 transmitter */ in imx_uart_probe()
2309 if (sport->have_rtscts || sport->have_rtsgpio) in imx_uart_probe()
2310 sport->port.rs485_supported = imx_rs485_supported; in imx_uart_probe()
2311 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2312 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2314 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2315 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2316 return PTR_ERR(sport->gpios); in imx_uart_probe()
2318 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2319 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2320 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2321 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2325 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2326 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2327 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2328 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2332 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2335 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2337 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret); in imx_uart_probe()
2341 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2346 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) in imx_uart_probe()
2347 * signal cannot be set low during transmission in case the in imx_uart_probe()
2350 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2351 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2352 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2353 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2354 dev_err(&pdev->dev, in imx_uart_probe()
2355 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2368 * In case RS485 is enabled without GPIO RTS control, the UART IP in imx_uart_probe()
2377 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2378 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_probe()
2392 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2423 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2424 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2425 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2426 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2433 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2434 dev_name(&pdev->dev), sport); in imx_uart_probe()
2436 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2441 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2442 dev_name(&pdev->dev), sport); in imx_uart_probe()
2444 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2449 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2450 dev_name(&pdev->dev), sport); in imx_uart_probe()
2452 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2457 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2458 dev_name(&pdev->dev), sport); in imx_uart_probe()
2460 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2465 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2469 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2472 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2481 uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2488 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_restore_context()
2489 if (!sport->context_saved) { in imx_uart_restore_context()
2490 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_restore_context()
2494 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2495 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2496 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2497 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2498 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2499 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2500 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2501 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2502 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2503 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2504 sport->context_saved = false; in imx_uart_restore_context()
2505 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_restore_context()
2513 uart_port_lock_irqsave(&sport->port, &flags); in imx_uart_save_context()
2514 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2515 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2516 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2517 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2518 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2519 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2520 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2521 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2522 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2523 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2524 sport->context_saved = true; in imx_uart_save_context()
2525 uart_port_unlock_irqrestore(&sport->port, flags); in imx_uart_save_context()
2541 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2559 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2573 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2587 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2588 disable_irq(sport->port.irq); in imx_uart_suspend()
2590 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2607 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2608 enable_irq(sport->port.irq); in imx_uart_resume()
2610 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2619 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2621 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2628 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2630 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2653 .name = "imx-uart",
2685 MODULE_ALIAS("platform:imx-uart");