1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * Copyright 2012-2016 Freescale Semiconductor, Inc.
6  * Copyright 2017-2019 NXP
20 /* All registers are 32-bit width */
115 #define DRIVER_NAME	"fsl-linflexuart"
125 		.compatible = "fsl,s32v234-linflexuart",
147 	ier = readl(port->membase + LINIER);  in linflex_stop_tx()
149 	writel(ier, port->membase + LINIER);  in linflex_stop_tx()
156 	ier = readl(port->membase + LINIER);  in linflex_stop_rx()
157 	writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER);  in linflex_stop_rx()
164 	writeb(c, sport->membase + BDRL);  in linflex_put_char()
167 	while (((status = readl(sport->membase + UARTSR)) &  in linflex_put_char()
172 	writel(status | LINFLEXD_UARTSR_DTFTFF, sport->membase + UARTSR);  in linflex_put_char()
177 	struct circ_buf *xmit = &sport->state->xmit;  in linflex_transmit_buffer()
180 		linflex_put_char(sport, xmit->buf[xmit->tail]);  in linflex_transmit_buffer()
196 	ier = readl(port->membase + LINIER);  in linflex_start_tx()
197 	writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER);  in linflex_start_tx()
203 	struct circ_buf *xmit = &sport->state->xmit;  in linflex_txint()
208 	if (sport->x_char) {  in linflex_txint()
209 		linflex_put_char(sport, sport->x_char);  in linflex_txint()
228 	struct tty_port *port = &sport->state->port;  in linflex_rxint()
235 	status = readl(sport->membase + UARTSR);  in linflex_rxint()
237 		rx = readb(sport->membase + BDRM);  in linflex_rxint()
240 		sport->icount.rx++;  in linflex_rxint()
245 				sport->icount.overrun++;  in linflex_rxint()
249 					sport->icount.brk++;  in linflex_rxint()
251 					sport->icount.frame++;  in linflex_rxint()
254 				sport->icount.parity++;  in linflex_rxint()
257 		writel(status, sport->membase + UARTSR);  in linflex_rxint()
258 		status = readl(sport->membase + UARTSR);  in linflex_rxint()
281 	status = readl(sport->membase + UARTSR);  in linflex_int()
296 	status = readl(port->membase + UARTSR) & LINFLEXD_UARTSR_DTFTFF;  in linflex_tx_empty()
319 	ier = readl(sport->membase + LINIER);  in linflex_setup_watermark()
321 	writel(ier, sport->membase + LINIER);  in linflex_setup_watermark()
323 	cr = readl(sport->membase + UARTCR);  in linflex_setup_watermark()
325 	writel(cr, sport->membase + UARTCR);  in linflex_setup_watermark()
329 	/* set the Linflex in master mode and activate by-pass filter */  in linflex_setup_watermark()
332 	writel(cr1, sport->membase + LINCR1);  in linflex_setup_watermark()
335 	while ((readl(sport->membase + LINSR)  in linflex_setup_watermark()
341 	 *	UART = 0x1;		- Linflex working in UART mode  in linflex_setup_watermark()
342 	 *	TXEN = 0x1;		- Enable transmission of data now  in linflex_setup_watermark()
343 	 *	RXEn = 0x1;		- Receiver enabled  in linflex_setup_watermark()
344 	 *	WL0 = 0x1;		- 8 bit data  in linflex_setup_watermark()
345 	 *	PCE = 0x0;		- No parity  in linflex_setup_watermark()
349 	writel(LINFLEXD_UARTCR_UART, sport->membase + UARTCR);  in linflex_setup_watermark()
354 	writel(cr, sport->membase + UARTCR);  in linflex_setup_watermark()
358 	writel(cr1, sport->membase + LINCR1);  in linflex_setup_watermark()
360 	ier = readl(sport->membase + LINIER);  in linflex_setup_watermark()
364 	writel(ier, sport->membase + LINIER);  in linflex_setup_watermark()
378 	ret = devm_request_irq(port->dev, port->irq, linflex_int, 0,  in linflex_startup()
392 	ier = readl(port->membase + LINIER);  in linflex_shutdown()
394 	writel(ier, port->membase + LINIER);  in linflex_shutdown()
398 	devm_free_irq(port->dev, port->irq, port);  in linflex_shutdown()
407 	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;  in linflex_set_termios()
409 	cr = readl(port->membase + UARTCR);  in linflex_set_termios()
413 	cr1 = readl(port->membase + LINCR1);  in linflex_set_termios()
415 	writel(cr1, port->membase + LINCR1);  in linflex_set_termios()
418 	while ((readl(port->membase + LINSR)  in linflex_set_termios()
426 	 *	- (7,e/o,1)  in linflex_set_termios()
427 	 *	- (8,n,1)  in linflex_set_termios()
428 	 *	- (8,e/o,1)  in linflex_set_termios()
432 	while ((termios->c_cflag & CSIZE) != CS8 &&  in linflex_set_termios()
433 	       (termios->c_cflag & CSIZE) != CS7) {  in linflex_set_termios()
434 		termios->c_cflag &= ~CSIZE;  in linflex_set_termios()
435 		termios->c_cflag |= old_csize;  in linflex_set_termios()
439 	if ((termios->c_cflag & CSIZE) == CS7) {  in linflex_set_termios()
444 	if ((termios->c_cflag & CSIZE) == CS8) {  in linflex_set_termios()
449 	if (termios->c_cflag & CMSPAR) {  in linflex_set_termios()
450 		if ((termios->c_cflag & CSIZE) != CS8) {  in linflex_set_termios()
451 			termios->c_cflag &= ~CSIZE;  in linflex_set_termios()
452 			termios->c_cflag |= CS8;  in linflex_set_termios()
458 	if (termios->c_cflag & CSTOPB)  in linflex_set_termios()
459 		termios->c_cflag &= ~CSTOPB;  in linflex_set_termios()
461 	/* parity must be enabled when CS7 to match 8-bits format */  in linflex_set_termios()
462 	if ((termios->c_cflag & CSIZE) == CS7)  in linflex_set_termios()
463 		termios->c_cflag |= PARENB;  in linflex_set_termios()
465 	if ((termios->c_cflag & PARENB)) {  in linflex_set_termios()
467 		if (termios->c_cflag & PARODD)  in linflex_set_termios()
479 	port->read_status_mask = 0;  in linflex_set_termios()
481 	if (termios->c_iflag & INPCK)  in linflex_set_termios()
482 		port->read_status_mask |=	(LINFLEXD_UARTSR_FEF |  in linflex_set_termios()
487 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))  in linflex_set_termios()
488 		port->read_status_mask |= LINFLEXD_UARTSR_FEF;  in linflex_set_termios()
491 	port->ignore_status_mask = 0;  in linflex_set_termios()
492 	if (termios->c_iflag & IGNPAR)  in linflex_set_termios()
493 		port->ignore_status_mask |= LINFLEXD_UARTSR_PE;  in linflex_set_termios()
494 	if (termios->c_iflag & IGNBRK) {  in linflex_set_termios()
495 		port->ignore_status_mask |= LINFLEXD_UARTSR_PE;  in linflex_set_termios()
500 		if (termios->c_iflag & IGNPAR)  in linflex_set_termios()
501 			port->ignore_status_mask |= LINFLEXD_UARTSR_BOF;  in linflex_set_termios()
504 	writel(cr, port->membase + UARTCR);  in linflex_set_termios()
508 	writel(cr1, port->membase + LINCR1);  in linflex_set_termios()
528 /* configure/auto-configure the port */
532 		port->type = PORT_LINFLEXUART;  in linflex_config_port()
559 	cr = readl(port->membase + UARTCR);  in linflex_console_putchar()
561 	writeb(ch, port->membase + BDRL);  in linflex_console_putchar()
564 		while ((readl(port->membase + UARTSR) &  in linflex_console_putchar()
569 		while (readl(port->membase + UARTSR) &  in linflex_console_putchar()
574 		writel((readl(port->membase + UARTSR) |  in linflex_console_putchar()
576 					port->membase + UARTSR);  in linflex_console_putchar()
627 	ier = readl(sport->membase + LINIER);  in linflex_string_write()
630 	cr = readl(sport->membase + UARTCR);  in linflex_string_write()
632 	writel(cr, sport->membase + UARTCR);  in linflex_string_write()
636 	writel(ier, sport->membase + LINIER);  in linflex_string_write()
642 	struct uart_port *sport = linflex_ports[co->index];  in linflex_console_write()
646 	if (sport->sysrq)  in linflex_console_write()
668 	cr = readl(sport->membase + UARTCR);  in linflex_console_get_options()
707 	if (co->index == -1 || co->index >= ARRAY_SIZE(linflex_ports))  in linflex_console_setup()
708 		co->index = 0;  in linflex_console_setup()
710 	sport = linflex_ports[co->index];  in linflex_console_setup()
712 		return -ENODEV;  in linflex_console_setup()
719 	if (earlycon_port && sport->mapbase == earlycon_port->mapbase) {  in linflex_console_setup()
766 	.index		= -1,
773 	struct earlycon_device *dev = con->data;  in linflex_earlycon_write()
775 	uart_console_write(&dev->port, s, n, linflex_earlycon_putchar);  in linflex_earlycon_write()
781 	if (!device->port.membase)  in linflex_early_console_setup()
782 		return -ENODEV;  in linflex_early_console_setup()
784 	device->con->write = linflex_earlycon_write;  in linflex_early_console_setup()
785 	earlycon_port = &device->port;  in linflex_early_console_setup()
790 OF_EARLYCON_DECLARE(linflex, "fsl,s32v234-linflexuart",
808 	struct device_node *np = pdev->dev.of_node;  in linflex_probe()
813 	sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);  in linflex_probe()
815 		return -ENOMEM;  in linflex_probe()
819 		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);  in linflex_probe()
823 		dev_err(&pdev->dev, "driver limited to %d serial ports\n",  in linflex_probe()
825 		return -ENOMEM;  in linflex_probe()
828 	sport->line = ret;  in linflex_probe()
830 	sport->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in linflex_probe()
831 	if (IS_ERR(sport->membase))  in linflex_probe()
832 		return PTR_ERR(sport->membase);  in linflex_probe()
833 	sport->mapbase = res->start;  in linflex_probe()
839 	sport->dev = &pdev->dev;  in linflex_probe()
840 	sport->type = PORT_LINFLEXUART;  in linflex_probe()
841 	sport->iotype = UPIO_MEM;  in linflex_probe()
842 	sport->irq = ret;  in linflex_probe()
843 	sport->ops = &linflex_pops;  in linflex_probe()
844 	sport->flags = UPF_BOOT_AUTOCONF;  in linflex_probe()
845 	sport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE);  in linflex_probe()
847 	linflex_ports[sport->line] = sport;  in linflex_probe()