85 	return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) &  in digicolor_uart_tx_full()
91 	return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) &  in digicolor_uart_rx_empty()
97 	u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);  in digicolor_uart_stop_tx()
100 	writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);  in digicolor_uart_stop_tx()
105 	u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);  in digicolor_uart_start_tx()
108 	writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);  in digicolor_uart_start_tx()
113 	u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);  in digicolor_uart_stop_rx()
116 	writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);  in digicolor_uart_stop_rx()
127 		writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET);  in digicolor_rx_poll()
144 		ch = readb_relaxed(port->membase + UA_EMI_REC);  in digicolor_uart_rx()
145 		status = readb_relaxed(port->membase + UA_STATUS);  in digicolor_uart_rx()
191 		writeb_relaxed(port->x_char, port->membase + UA_EMI_REC);  in digicolor_uart_tx()
203 		writeb(xmit->buf[xmit->tail], port->membase + UA_EMI_REC);  in digicolor_uart_tx()
220 	u8 int_status = readb_relaxed(port->membase + UA_INT_STATUS);  in digicolor_uart_int()
223 		       port->membase + UA_INTFLAG_CLEAR);  in digicolor_uart_int()
235 	u8 status = readb_relaxed(port->membase + UA_STATUS);  in digicolor_uart_tx_empty()
258 	writeb_relaxed(UA_ENABLE_ENABLE, port->membase + UA_ENABLE);  in digicolor_uart_startup()
259 	writeb_relaxed(UA_CONTROL_SOFT_RESET, port->membase + UA_CONTROL);  in digicolor_uart_startup()
260 	writeb_relaxed(0, port->membase + UA_CONTROL);  in digicolor_uart_startup()
264 		       port->membase + UA_CONFIG_FIFO);  in digicolor_uart_startup()
266 		       port->membase + UA_STATUS_FIFO);  in digicolor_uart_startup()
268 		       port->membase + UA_CONTROL);  in digicolor_uart_startup()
270 		       port->membase + UA_INT_ENABLE);  in digicolor_uart_startup()
282 	writeb_relaxed(0, port->membase + UA_ENABLE);  in digicolor_uart_shutdown()
340 	writeb_relaxed(config, port->membase + UA_CONFIG);  in digicolor_uart_set_termios()
341 	writeb_relaxed(divisor & 0xff, port->membase + UA_HBAUD_LO);  in digicolor_uart_set_termios()
342 	writeb_relaxed(divisor >> 8, port->membase + UA_HBAUD_HI);  in digicolor_uart_set_termios()
389 	writeb_relaxed(ch, port->membase + UA_EMI_REC);  in digicolor_uart_console_putchar()
412 		status = readb_relaxed(port->membase + UA_STATUS);  in digicolor_uart_console_write()
474 	dp->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in digicolor_uart_probe()
475 	if (IS_ERR(dp->port.membase))  in digicolor_uart_probe()
476 		return PTR_ERR(dp->port.membase);  in digicolor_uart_probe()