Lines Matching +full:auto +full:- +full:baud
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
35 #include <linux/dma-mapping.h>
82 /* The size of the array - must be last */
262 unsigned int fifosize; /* vendor-specific */
263 unsigned int fixed_baud; /* vendor-set fixed baud rate */
282 return uap->reg_offset[reg]; in pl011_reg_to_offset()
288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_read()
290 return (uap->port.iotype == UPIO_MEM32) ? in pl011_read()
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_write()
299 if (uap->port.iotype == UPIO_MEM32) in pl011_write()
325 uap->port.icount.rx++; in pl011_fifo_to_tty()
330 uap->port.icount.brk++; in pl011_fifo_to_tty()
331 if (uart_handle_break(&uap->port)) in pl011_fifo_to_tty()
334 uap->port.icount.parity++; in pl011_fifo_to_tty()
336 uap->port.icount.frame++; in pl011_fifo_to_tty()
339 uap->port.icount.overrun++; in pl011_fifo_to_tty()
341 ch &= uap->port.read_status_mask; in pl011_fifo_to_tty()
351 uart_port_unlock(&uap->port); in pl011_fifo_to_tty()
352 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); in pl011_fifo_to_tty()
353 uart_port_lock(&uap->port); in pl011_fifo_to_tty()
356 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); in pl011_fifo_to_tty()
374 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE, in pl011_dmabuf_init()
375 &db->dma, GFP_KERNEL); in pl011_dmabuf_init()
376 if (!db->buf) in pl011_dmabuf_init()
377 return -ENOMEM; in pl011_dmabuf_init()
378 db->len = PL011_DMA_BUFFER_SIZE; in pl011_dmabuf_init()
386 if (db->buf) { in pl011_dmabuf_free()
387 dma_free_coherent(chan->device->dev, in pl011_dmabuf_free()
388 PL011_DMA_BUFFER_SIZE, db->buf, db->dma); in pl011_dmabuf_free()
395 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); in pl011_dma_probe()
396 struct device *dev = uap->port.dev; in pl011_dma_probe()
398 .dst_addr = uap->port.mapbase + in pl011_dma_probe()
402 .dst_maxburst = uap->fifosize >> 1, in pl011_dma_probe()
408 uap->dma_probed = true; in pl011_dma_probe()
411 if (PTR_ERR(chan) == -EPROBE_DEFER) { in pl011_dma_probe()
412 uap->dma_probed = false; in pl011_dma_probe()
417 if (!plat || !plat->dma_filter) { in pl011_dma_probe()
418 dev_dbg(uap->port.dev, "no DMA platform data\n"); in pl011_dma_probe()
426 chan = dma_request_channel(mask, plat->dma_filter, in pl011_dma_probe()
427 plat->dma_tx_param); in pl011_dma_probe()
429 dev_err(uap->port.dev, "no TX DMA channel!\n"); in pl011_dma_probe()
435 uap->dmatx.chan = chan; in pl011_dma_probe()
437 dev_info(uap->port.dev, "DMA channel TX %s\n", in pl011_dma_probe()
438 dma_chan_name(uap->dmatx.chan)); in pl011_dma_probe()
443 if (IS_ERR(chan) && plat && plat->dma_rx_param) { in pl011_dma_probe()
444 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); in pl011_dma_probe()
447 dev_err(uap->port.dev, "no RX DMA channel!\n"); in pl011_dma_probe()
454 .src_addr = uap->port.mapbase + in pl011_dma_probe()
458 .src_maxburst = uap->fifosize >> 2, in pl011_dma_probe()
472 dev_info(uap->port.dev, in pl011_dma_probe()
473 "RX DMA disabled - no residue processing\n"); in pl011_dma_probe()
478 uap->dmarx.chan = chan; in pl011_dma_probe()
480 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
481 if (plat && plat->dma_rx_poll_enable) { in pl011_dma_probe()
483 if (plat->dma_rx_poll_rate) { in pl011_dma_probe()
484 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
485 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; in pl011_dma_probe()
490 * the baud rate at set_termios. in pl011_dma_probe()
492 uap->dmarx.auto_poll_rate = true; in pl011_dma_probe()
493 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
496 if (plat->dma_rx_poll_timeout) in pl011_dma_probe()
497 uap->dmarx.poll_timeout = in pl011_dma_probe()
498 plat->dma_rx_poll_timeout; in pl011_dma_probe()
500 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
501 } else if (!plat && dev->of_node) { in pl011_dma_probe()
502 uap->dmarx.auto_poll_rate = in pl011_dma_probe()
503 of_property_read_bool(dev->of_node, "auto-poll"); in pl011_dma_probe()
504 if (uap->dmarx.auto_poll_rate) { in pl011_dma_probe()
507 if (of_property_read_u32(dev->of_node, "poll-rate-ms", &x) == 0) in pl011_dma_probe()
508 uap->dmarx.poll_rate = x; in pl011_dma_probe()
510 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
511 if (of_property_read_u32(dev->of_node, "poll-timeout-ms", &x) == 0) in pl011_dma_probe()
512 uap->dmarx.poll_timeout = x; in pl011_dma_probe()
514 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
517 dev_info(uap->port.dev, "DMA channel RX %s\n", in pl011_dma_probe()
518 dma_chan_name(uap->dmarx.chan)); in pl011_dma_probe()
524 if (uap->dmatx.chan) in pl011_dma_remove()
525 dma_release_channel(uap->dmatx.chan); in pl011_dma_remove()
526 if (uap->dmarx.chan) in pl011_dma_remove()
527 dma_release_channel(uap->dmarx.chan); in pl011_dma_remove()
541 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_callback()
545 uart_port_lock_irqsave(&uap->port, &flags); in pl011_dma_tx_callback()
546 if (uap->dmatx.queued) in pl011_dma_tx_callback()
547 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma, in pl011_dma_tx_callback()
548 dmatx->len, DMA_TO_DEVICE); in pl011_dma_tx_callback()
550 dmacr = uap->dmacr; in pl011_dma_tx_callback()
551 uap->dmacr = dmacr & ~UART011_TXDMAE; in pl011_dma_tx_callback()
552 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_callback()
556 * some reason (eg, XOFF received, or we want to send an X-char.) in pl011_dma_tx_callback()
559 * and the rest of the driver - if the driver disables TX DMA while in pl011_dma_tx_callback()
563 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
564 uart_circ_empty(&uap->port.state->xmit)) { in pl011_dma_tx_callback()
565 uap->dmatx.queued = false; in pl011_dma_tx_callback()
566 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_tx_callback()
573 * have data pending to be sent. Re-enable the TX IRQ. in pl011_dma_tx_callback()
577 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_tx_callback()
590 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_refill()
591 struct dma_chan *chan = dmatx->chan; in pl011_dma_tx_refill()
592 struct dma_device *dma_dev = chan->device; in pl011_dma_tx_refill()
594 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_dma_tx_refill()
604 if (count < (uap->fifosize >> 1)) { in pl011_dma_tx_refill()
605 uap->dmatx.queued = false; in pl011_dma_tx_refill()
613 count -= 1; in pl011_dma_tx_refill()
619 if (xmit->tail < xmit->head) { in pl011_dma_tx_refill()
620 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); in pl011_dma_tx_refill()
622 size_t first = UART_XMIT_SIZE - xmit->tail; in pl011_dma_tx_refill()
627 second = count - first; in pl011_dma_tx_refill()
629 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); in pl011_dma_tx_refill()
631 memcpy(&dmatx->buf[first], &xmit->buf[0], second); in pl011_dma_tx_refill()
634 dmatx->len = count; in pl011_dma_tx_refill()
635 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count, in pl011_dma_tx_refill()
637 if (dmatx->dma == DMA_MAPPING_ERROR) { in pl011_dma_tx_refill()
638 uap->dmatx.queued = false; in pl011_dma_tx_refill()
639 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); in pl011_dma_tx_refill()
640 return -EBUSY; in pl011_dma_tx_refill()
643 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV, in pl011_dma_tx_refill()
646 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE); in pl011_dma_tx_refill()
647 uap->dmatx.queued = false; in pl011_dma_tx_refill()
652 dev_dbg(uap->port.dev, "TX DMA busy\n"); in pl011_dma_tx_refill()
653 return -EBUSY; in pl011_dma_tx_refill()
657 desc->callback = pl011_dma_tx_callback; in pl011_dma_tx_refill()
658 desc->callback_param = uap; in pl011_dma_tx_refill()
664 dma_dev->device_issue_pending(chan); in pl011_dma_tx_refill()
666 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_refill()
667 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_refill()
668 uap->dmatx.queued = true; in pl011_dma_tx_refill()
674 uart_xmit_advance(&uap->port, count); in pl011_dma_tx_refill()
677 uart_write_wakeup(&uap->port); in pl011_dma_tx_refill()
683 * We received a transmit interrupt without a pending X-char but with
692 if (!uap->using_tx_dma) in pl011_dma_tx_irq()
697 * TX interrupt, it will be because we've just sent an X-char. in pl011_dma_tx_irq()
700 if (uap->dmatx.queued) { in pl011_dma_tx_irq()
701 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_irq()
702 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_irq()
703 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
704 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
713 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
714 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
726 if (uap->dmatx.queued) { in pl011_dma_tx_stop()
727 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_stop()
728 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_stop()
744 if (!uap->using_tx_dma) in pl011_dma_tx_start()
747 if (!uap->port.x_char) { in pl011_dma_tx_start()
748 /* no X-char, try to push chars out in DMA mode */ in pl011_dma_tx_start()
751 if (!uap->dmatx.queued) { in pl011_dma_tx_start()
753 uap->im &= ~UART011_TXIM; in pl011_dma_tx_start()
754 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_start()
758 } else if (!(uap->dmacr & UART011_TXDMAE)) { in pl011_dma_tx_start()
759 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_start()
760 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
766 * We have an X-char to send. Disable DMA to prevent it loading in pl011_dma_tx_start()
769 dmacr = uap->dmacr; in pl011_dma_tx_start()
770 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_start()
771 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
777 * loaded the character, we should just re-enable DMA. in pl011_dma_tx_start()
782 pl011_write(uap->port.x_char, uap, REG_DR); in pl011_dma_tx_start()
783 uap->port.icount.tx++; in pl011_dma_tx_start()
784 uap->port.x_char = 0; in pl011_dma_tx_start()
786 /* Success - restore the DMA state */ in pl011_dma_tx_start()
787 uap->dmacr = dmacr; in pl011_dma_tx_start()
798 __releases(&uap->port.lock) in pl011_dma_flush_buffer()
799 __acquires(&uap->port.lock) in pl011_dma_flush_buffer()
804 if (!uap->using_tx_dma) in pl011_dma_flush_buffer()
807 dmaengine_terminate_async(uap->dmatx.chan); in pl011_dma_flush_buffer()
809 if (uap->dmatx.queued) { in pl011_dma_flush_buffer()
810 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma, in pl011_dma_flush_buffer()
811 uap->dmatx.len, DMA_TO_DEVICE); in pl011_dma_flush_buffer()
812 uap->dmatx.queued = false; in pl011_dma_flush_buffer()
813 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_flush_buffer()
814 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_flush_buffer()
822 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_trigger_dma()
823 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_trigger_dma()
828 return -EIO; in pl011_dma_rx_trigger_dma()
831 dbuf = uap->dmarx.use_buf_b ? in pl011_dma_rx_trigger_dma()
832 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_trigger_dma()
833 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len, in pl011_dma_rx_trigger_dma()
842 uap->dmarx.running = false; in pl011_dma_rx_trigger_dma()
844 return -EBUSY; in pl011_dma_rx_trigger_dma()
848 desc->callback = pl011_dma_rx_callback; in pl011_dma_rx_trigger_dma()
849 desc->callback_param = uap; in pl011_dma_rx_trigger_dma()
850 dmarx->cookie = dmaengine_submit(desc); in pl011_dma_rx_trigger_dma()
853 uap->dmacr |= UART011_RXDMAE; in pl011_dma_rx_trigger_dma()
854 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_trigger_dma()
855 uap->dmarx.running = true; in pl011_dma_rx_trigger_dma()
857 uap->im &= ~UART011_RXIM; in pl011_dma_rx_trigger_dma()
858 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_trigger_dma()
866 * with the port spinlock uap->port.lock held.
872 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_chars()
874 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_chars()
878 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_chars()
881 if (uap->dmarx.poll_rate) { in pl011_dma_rx_chars()
883 dmataken = dbuf->len - dmarx->last_residue; in pl011_dma_rx_chars()
886 pending -= dmataken; in pl011_dma_rx_chars()
896 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, pending); in pl011_dma_rx_chars()
898 uap->port.icount.rx += dma_count; in pl011_dma_rx_chars()
900 dev_warn(uap->port.dev, in pl011_dma_rx_chars()
905 if (uap->dmarx.poll_rate) in pl011_dma_rx_chars()
906 dmarx->last_residue = dbuf->len; in pl011_dma_rx_chars()
931 dev_vdbg(uap->port.dev, in pl011_dma_rx_chars()
939 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_irq()
940 struct dma_chan *rxchan = dmarx->chan; in pl011_dma_rx_irq()
941 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? in pl011_dma_rx_irq()
942 &dmarx->dbuf_b : &dmarx->dbuf_a; in pl011_dma_rx_irq()
953 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
954 dmastat = rxchan->device->device_tx_status(rxchan, in pl011_dma_rx_irq()
955 dmarx->cookie, &state); in pl011_dma_rx_irq()
957 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
959 /* Disable RX DMA - incoming data will wait in the FIFO */ in pl011_dma_rx_irq()
960 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_irq()
961 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_irq()
962 uap->dmarx.running = false; in pl011_dma_rx_irq()
964 pending = dbuf->len - state.residue; in pl011_dma_rx_irq()
966 /* Then we terminate the transfer - we now know our residue */ in pl011_dma_rx_irq()
973 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); in pl011_dma_rx_irq()
975 /* Switch buffer & re-trigger DMA job */ in pl011_dma_rx_irq()
976 dmarx->use_buf_b = !dmarx->use_buf_b; in pl011_dma_rx_irq()
978 dev_dbg(uap->port.dev, in pl011_dma_rx_irq()
980 uap->im |= UART011_RXIM; in pl011_dma_rx_irq()
981 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_irq()
988 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_callback()
989 struct dma_chan *rxchan = dmarx->chan; in pl011_dma_rx_callback()
990 bool lastbuf = dmarx->use_buf_b; in pl011_dma_rx_callback()
991 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? in pl011_dma_rx_callback()
992 &dmarx->dbuf_b : &dmarx->dbuf_a; in pl011_dma_rx_callback()
1004 uart_port_lock_irq(&uap->port); in pl011_dma_rx_callback()
1009 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); in pl011_dma_rx_callback()
1010 pending = dbuf->len - state.residue; in pl011_dma_rx_callback()
1012 /* Then we terminate the transfer - we now know our residue */ in pl011_dma_rx_callback()
1015 uap->dmarx.running = false; in pl011_dma_rx_callback()
1016 dmarx->use_buf_b = !lastbuf; in pl011_dma_rx_callback()
1020 uart_port_unlock_irq(&uap->port); in pl011_dma_rx_callback()
1026 dev_dbg(uap->port.dev, in pl011_dma_rx_callback()
1028 uap->im |= UART011_RXIM; in pl011_dma_rx_callback()
1029 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_callback()
1040 if (!uap->using_rx_dma) in pl011_dma_rx_stop()
1044 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_stop()
1045 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_stop()
1056 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_poll()
1057 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_poll()
1058 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_poll()
1066 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_poll()
1067 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); in pl011_dma_rx_poll()
1068 if (likely(state.residue < dmarx->last_residue)) { in pl011_dma_rx_poll()
1069 dmataken = dbuf->len - dmarx->last_residue; in pl011_dma_rx_poll()
1070 size = dmarx->last_residue - state.residue; in pl011_dma_rx_poll()
1071 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, in pl011_dma_rx_poll()
1074 dmarx->last_residue = state.residue; in pl011_dma_rx_poll()
1075 dmarx->last_jiffies = jiffies; in pl011_dma_rx_poll()
1083 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) in pl011_dma_rx_poll()
1084 > uap->dmarx.poll_timeout) { in pl011_dma_rx_poll()
1085 uart_port_lock_irqsave(&uap->port, &flags); in pl011_dma_rx_poll()
1087 uap->im |= UART011_RXIM; in pl011_dma_rx_poll()
1088 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_poll()
1089 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_rx_poll()
1091 uap->dmarx.running = false; in pl011_dma_rx_poll()
1093 del_timer(&uap->dmarx.timer); in pl011_dma_rx_poll()
1095 mod_timer(&uap->dmarx.timer, in pl011_dma_rx_poll()
1096 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_rx_poll()
1104 if (!uap->dma_probed) in pl011_dma_startup()
1107 if (!uap->dmatx.chan) in pl011_dma_startup()
1110 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); in pl011_dma_startup()
1111 if (!uap->dmatx.buf) { in pl011_dma_startup()
1112 uap->port.fifosize = uap->fifosize; in pl011_dma_startup()
1116 uap->dmatx.len = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1119 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1120 uap->using_tx_dma = true; in pl011_dma_startup()
1122 if (!uap->dmarx.chan) in pl011_dma_startup()
1126 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a, in pl011_dma_startup()
1129 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1134 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b, in pl011_dma_startup()
1137 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1139 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, in pl011_dma_startup()
1144 uap->using_rx_dma = true; in pl011_dma_startup()
1148 uap->dmacr |= UART011_DMAONERR; in pl011_dma_startup()
1149 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_startup()
1156 if (uap->vendor->dma_threshold) in pl011_dma_startup()
1160 if (uap->using_rx_dma) { in pl011_dma_startup()
1162 dev_dbg(uap->port.dev, in pl011_dma_startup()
1164 if (uap->dmarx.poll_rate) { in pl011_dma_startup()
1165 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); in pl011_dma_startup()
1166 mod_timer(&uap->dmarx.timer, in pl011_dma_startup()
1167 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_startup()
1168 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1169 uap->dmarx.last_jiffies = jiffies; in pl011_dma_startup()
1176 if (!(uap->using_tx_dma || uap->using_rx_dma)) in pl011_dma_shutdown()
1180 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) in pl011_dma_shutdown()
1183 uart_port_lock_irq(&uap->port); in pl011_dma_shutdown()
1184 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); in pl011_dma_shutdown()
1185 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_shutdown()
1186 uart_port_unlock_irq(&uap->port); in pl011_dma_shutdown()
1188 if (uap->using_tx_dma) { in pl011_dma_shutdown()
1190 dmaengine_terminate_all(uap->dmatx.chan); in pl011_dma_shutdown()
1191 if (uap->dmatx.queued) { in pl011_dma_shutdown()
1192 dma_unmap_single(uap->dmatx.chan->device->dev, in pl011_dma_shutdown()
1193 uap->dmatx.dma, uap->dmatx.len, in pl011_dma_shutdown()
1195 uap->dmatx.queued = false; in pl011_dma_shutdown()
1198 kfree(uap->dmatx.buf); in pl011_dma_shutdown()
1199 uap->using_tx_dma = false; in pl011_dma_shutdown()
1202 if (uap->using_rx_dma) { in pl011_dma_shutdown()
1203 dmaengine_terminate_all(uap->dmarx.chan); in pl011_dma_shutdown()
1205 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1206 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1207 if (uap->dmarx.poll_rate) in pl011_dma_shutdown()
1208 del_timer_sync(&uap->dmarx.timer); in pl011_dma_shutdown()
1209 uap->using_rx_dma = false; in pl011_dma_shutdown()
1215 return uap->using_rx_dma; in pl011_dma_rx_available()
1220 return uap->using_rx_dma && uap->dmarx.running; in pl011_dma_rx_running()
1261 return -EIO; in pl011_dma_rx_trigger_dma()
1283 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2; in pl011_rs485_tx_stop()
1284 struct uart_port *port = &uap->port; in pl011_rs485_tx_stop()
1291 dev_warn(port->dev, in pl011_rs485_tx_stop()
1296 udelay(uap->rs485_tx_drain_interval); in pl011_rs485_tx_stop()
1300 if (port->rs485.delay_rts_after_send) in pl011_rs485_tx_stop()
1301 mdelay(port->rs485.delay_rts_after_send); in pl011_rs485_tx_stop()
1305 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in pl011_rs485_tx_stop()
1315 uap->rs485_tx_started = false; in pl011_rs485_tx_stop()
1323 uap->im &= ~UART011_TXIM; in pl011_stop_tx()
1324 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_tx()
1327 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) in pl011_stop_tx()
1337 uap->im |= UART011_TXIM; in pl011_start_tx_pio()
1338 pl011_write(uap->im, uap, REG_IMSC); in pl011_start_tx_pio()
1344 struct uart_port *port = &uap->port; in pl011_rs485_tx_start()
1351 /* Disable receiver if half-duplex */ in pl011_rs485_tx_start()
1352 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in pl011_rs485_tx_start()
1355 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in pl011_rs485_tx_start()
1362 if (port->rs485.delay_rts_before_send) in pl011_rs485_tx_start()
1363 mdelay(port->rs485.delay_rts_before_send); in pl011_rs485_tx_start()
1365 uap->rs485_tx_started = true; in pl011_rs485_tx_start()
1373 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && in pl011_start_tx()
1374 !uap->rs485_tx_started) in pl011_start_tx()
1386 uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM | in pl011_stop_rx()
1388 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_rx()
1407 uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM; in pl011_enable_ms()
1408 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_ms()
1412 __releases(&uap->port.lock) in pl011_rx_chars()
1413 __acquires(&uap->port.lock) in pl011_rx_chars()
1417 uart_port_unlock(&uap->port); in pl011_rx_chars()
1418 tty_flip_buffer_push(&uap->port.state->port); in pl011_rx_chars()
1425 dev_dbg(uap->port.dev, in pl011_rx_chars()
1427 uap->im |= UART011_RXIM; in pl011_rx_chars()
1428 pl011_write(uap->im, uap, REG_IMSC); in pl011_rx_chars()
1432 if (uap->dmarx.poll_rate) { in pl011_rx_chars()
1433 uap->dmarx.last_jiffies = jiffies; in pl011_rx_chars()
1434 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_rx_chars()
1435 mod_timer(&uap->dmarx.timer, in pl011_rx_chars()
1436 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_rx_chars()
1441 uart_port_lock(&uap->port); in pl011_rx_chars()
1452 uap->port.icount.tx++; in pl011_tx_char()
1460 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_tx_chars()
1461 int count = uap->fifosize >> 1; in pl011_tx_chars()
1463 if (uap->port.x_char) { in pl011_tx_chars()
1464 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) in pl011_tx_chars()
1466 uap->port.x_char = 0; in pl011_tx_chars()
1467 --count; in pl011_tx_chars()
1469 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { in pl011_tx_chars()
1470 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1479 if (likely(from_irq) && count-- == 0) in pl011_tx_chars()
1482 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) in pl011_tx_chars()
1485 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in pl011_tx_chars()
1489 uart_write_wakeup(&uap->port); in pl011_tx_chars()
1492 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1504 delta = status ^ uap->old_status; in pl011_modem_status()
1505 uap->old_status = status; in pl011_modem_status()
1511 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); in pl011_modem_status()
1513 if (delta & uap->vendor->fr_dsr) in pl011_modem_status()
1514 uap->port.icount.dsr++; in pl011_modem_status()
1516 if (delta & uap->vendor->fr_cts) in pl011_modem_status()
1517 uart_handle_cts_change(&uap->port, in pl011_modem_status()
1518 status & uap->vendor->fr_cts); in pl011_modem_status()
1520 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); in pl011_modem_status()
1525 if (!uap->vendor->cts_event_workaround) in check_apply_cts_event_workaround()
1547 uart_port_lock_irqsave(&uap->port, &flags); in pl011_int()
1548 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1568 if (pass_counter-- == 0) in pl011_int()
1571 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1576 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_int()
1587 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; in pl011_tx_empty()
1589 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? in pl011_tx_empty()
1607 pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR); in pl011_get_mctrl()
1608 pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS); in pl011_get_mctrl()
1609 pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG); in pl011_get_mctrl()
1636 if (port->status & UPSTAT_AUTORTS) { in pl011_set_mctrl()
1637 /* We need to disable auto-RTS if we want to turn RTS off */ in pl011_set_mctrl()
1651 uart_port_lock_irqsave(&uap->port, &flags); in pl011_break_ctl()
1653 if (break_state == -1) in pl011_break_ctl()
1658 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_break_ctl()
1725 pinctrl_pm_select_default_state(port->dev); in pl011_hwinit()
1730 retval = clk_prepare_enable(uap->clk); in pl011_hwinit()
1734 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_hwinit()
1745 uap->im = pl011_read(uap, REG_IMSC); in pl011_hwinit()
1748 if (dev_get_platdata(uap->port.dev)) { in pl011_hwinit()
1751 plat = dev_get_platdata(uap->port.dev); in pl011_hwinit()
1752 if (plat->init) in pl011_hwinit()
1753 plat->init(); in pl011_hwinit()
1781 pl011_write(uap->im, uap, REG_IMSC); in pl011_allocate_irq()
1783 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); in pl011_allocate_irq()
1796 uart_port_lock_irqsave(&uap->port, &flags); in pl011_enable_interrupts()
1807 for (i = 0; i < uap->fifosize * 2; ++i) { in pl011_enable_interrupts()
1814 uap->im = UART011_RTIM; in pl011_enable_interrupts()
1816 uap->im |= UART011_RXIM; in pl011_enable_interrupts()
1817 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_interrupts()
1818 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_enable_interrupts()
1826 uart_port_lock_irqsave(&uap->port, &flags); in pl011_unthrottle_rx()
1828 uap->im = UART011_RTIM; in pl011_unthrottle_rx()
1830 uap->im |= UART011_RXIM; in pl011_unthrottle_rx()
1832 pl011_write(uap->im, uap, REG_IMSC); in pl011_unthrottle_rx()
1834 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_unthrottle_rx()
1852 pl011_write(uap->vendor->ifls, uap, REG_IFLS); in pl011_startup()
1854 uart_port_lock_irq(&uap->port); in pl011_startup()
1860 if (!(port->rs485.flags & SER_RS485_ENABLED)) in pl011_startup()
1865 uart_port_unlock_irq(&uap->port); in pl011_startup()
1870 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; in pl011_startup()
1880 clk_disable_unprepare(uap->clk); in pl011_startup()
1899 uap->old_status = 0; in sbsa_uart_startup()
1924 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_disable_uart()
1925 uart_port_lock_irq(&uap->port); in pl011_disable_uart()
1930 uart_port_unlock_irq(&uap->port); in pl011_disable_uart()
1942 uart_port_lock_irq(&uap->port); in pl011_disable_interrupts()
1945 uap->im = 0; in pl011_disable_interrupts()
1946 pl011_write(uap->im, uap, REG_IMSC); in pl011_disable_interrupts()
1949 uart_port_unlock_irq(&uap->port); in pl011_disable_interrupts()
1961 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) in pl011_shutdown()
1964 free_irq(uap->port.irq, uap); in pl011_shutdown()
1971 clk_disable_unprepare(uap->clk); in pl011_shutdown()
1973 pinctrl_pm_select_sleep_state(port->dev); in pl011_shutdown()
1975 if (dev_get_platdata(uap->port.dev)) { in pl011_shutdown()
1978 plat = dev_get_platdata(uap->port.dev); in pl011_shutdown()
1979 if (plat->exit) in pl011_shutdown()
1980 plat->exit(); in pl011_shutdown()
1983 if (uap->port.ops->flush_buffer) in pl011_shutdown()
1984 uap->port.ops->flush_buffer(port); in pl011_shutdown()
1994 free_irq(uap->port.irq, uap); in sbsa_uart_shutdown()
1996 if (uap->port.ops->flush_buffer) in sbsa_uart_shutdown()
1997 uap->port.ops->flush_buffer(port); in sbsa_uart_shutdown()
2003 port->read_status_mask = UART011_DR_OE | 255; in pl011_setup_status_masks()
2004 if (termios->c_iflag & INPCK) in pl011_setup_status_masks()
2005 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
2006 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in pl011_setup_status_masks()
2007 port->read_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
2012 port->ignore_status_mask = 0; in pl011_setup_status_masks()
2013 if (termios->c_iflag & IGNPAR) in pl011_setup_status_masks()
2014 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
2015 if (termios->c_iflag & IGNBRK) { in pl011_setup_status_masks()
2016 port->ignore_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
2021 if (termios->c_iflag & IGNPAR) in pl011_setup_status_masks()
2022 port->ignore_status_mask |= UART011_DR_OE; in pl011_setup_status_masks()
2028 if ((termios->c_cflag & CREAD) == 0) in pl011_setup_status_masks()
2029 port->ignore_status_mask |= UART_DUMMY_DR_RX; in pl011_setup_status_masks()
2040 unsigned int baud, quot, clkdiv; in pl011_set_termios() local
2043 if (uap->vendor->oversampling) in pl011_set_termios()
2051 baud = uart_get_baud_rate(port, termios, old, 0, in pl011_set_termios()
2052 port->uartclk / clkdiv); in pl011_set_termios()
2055 * Adjust RX DMA polling rate with baud rate if not specified. in pl011_set_termios()
2057 if (uap->dmarx.auto_poll_rate) in pl011_set_termios()
2058 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); in pl011_set_termios()
2061 if (baud > port->uartclk / 16) in pl011_set_termios()
2062 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); in pl011_set_termios()
2064 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); in pl011_set_termios()
2066 switch (termios->c_cflag & CSIZE) { in pl011_set_termios()
2080 if (termios->c_cflag & CSTOPB) in pl011_set_termios()
2082 if (termios->c_cflag & PARENB) { in pl011_set_termios()
2084 if (!(termios->c_cflag & PARODD)) in pl011_set_termios()
2086 if (termios->c_cflag & CMSPAR) in pl011_set_termios()
2089 if (uap->fifosize > 1) in pl011_set_termios()
2092 bits = tty_get_frame_size(termios->c_cflag); in pl011_set_termios()
2097 * Update the per-port timeout. in pl011_set_termios()
2099 uart_update_timeout(port, termios->c_cflag, baud); in pl011_set_termios()
2103 * with the given baud rate. We use this as the poll interval when we in pl011_set_termios()
2106 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud); in pl011_set_termios()
2110 if (UART_ENABLE_MS(port, termios->c_cflag)) in pl011_set_termios()
2113 if (port->rs485.flags & SER_RS485_ENABLED) in pl011_set_termios()
2114 termios->c_cflag &= ~CRTSCTS; in pl011_set_termios()
2118 if (termios->c_cflag & CRTSCTS) { in pl011_set_termios()
2123 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in pl011_set_termios()
2126 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_set_termios()
2129 if (uap->vendor->oversampling) { in pl011_set_termios()
2130 if (baud > port->uartclk / 16) in pl011_set_termios()
2142 if (uap->vendor->oversampling) { in pl011_set_termios()
2143 if (baud >= 3000000 && baud < 3250000 && quot > 1) in pl011_set_termios()
2144 quot -= 1; in pl011_set_termios()
2145 else if (baud > 3250000 && quot > 2) in pl011_set_termios()
2146 quot -= 2; in pl011_set_termios()
2148 /* Set baud rate */ in pl011_set_termios()
2153 * ----------v----------v----------v----------v----- in pl011_set_termios()
2156 * ----------^----------^----------^----------^----- in pl011_set_termios()
2179 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); in sbsa_uart_set_termios()
2182 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); in sbsa_uart_set_termios()
2183 termios->c_cflag &= ~(CMSPAR | CRTSCTS); in sbsa_uart_set_termios()
2184 termios->c_cflag |= CS8 | CLOCAL; in sbsa_uart_set_termios()
2187 uart_update_timeout(port, CS8, uap->fixed_baud); in sbsa_uart_set_termios()
2196 return uap->port.type == PORT_AMBA ? uap->type : NULL; in pl011_type()
2205 port->type = PORT_AMBA; in pl011_config_port()
2215 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) in pl011_verify_port()
2216 ret = -EINVAL; in pl011_verify_port()
2217 if (ser->irq < 0 || ser->irq >= nr_irqs) in pl011_verify_port()
2218 ret = -EINVAL; in pl011_verify_port()
2219 if (ser->baud_base < 9600) in pl011_verify_port()
2220 ret = -EINVAL; in pl011_verify_port()
2221 if (port->mapbase != (unsigned long)ser->iomem_base) in pl011_verify_port()
2222 ret = -EINVAL; in pl011_verify_port()
2232 if (port->rs485.flags & SER_RS485_ENABLED) in pl011_rs485_config()
2235 /* Make sure auto RTS is disabled */ in pl011_rs485_config()
2236 if (rs485->flags & SER_RS485_ENABLED) { in pl011_rs485_config()
2241 port->status &= ~UPSTAT_AUTORTS; in pl011_rs485_config()
2318 struct uart_amba_port *uap = amba_ports[co->index]; in pl011_console_write()
2323 clk_enable(uap->clk); in pl011_console_write()
2326 if (uap->port.sysrq) in pl011_console_write()
2329 locked = uart_port_trylock(&uap->port); in pl011_console_write()
2331 uart_port_lock(&uap->port); in pl011_console_write()
2336 if (!uap->vendor->always_enabled) { in pl011_console_write()
2343 uart_console_write(&uap->port, s, count, pl011_console_putchar); in pl011_console_write()
2350 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) in pl011_console_write()
2351 & uap->vendor->fr_busy) in pl011_console_write()
2353 if (!uap->vendor->always_enabled) in pl011_console_write()
2357 uart_port_unlock(&uap->port); in pl011_console_write()
2360 clk_disable(uap->clk); in pl011_console_write()
2363 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, in pl011_console_get_options() argument
2389 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); in pl011_console_get_options()
2391 if (uap->vendor->oversampling && in pl011_console_get_options()
2393 *baud *= 2; in pl011_console_get_options()
2399 int baud = 38400; in pl011_console_setup() local
2410 if (co->index >= UART_NR) in pl011_console_setup()
2411 co->index = 0; in pl011_console_setup()
2412 uap = amba_ports[co->index]; in pl011_console_setup()
2414 return -ENODEV; in pl011_console_setup()
2417 pinctrl_pm_select_default_state(uap->port.dev); in pl011_console_setup()
2419 ret = clk_prepare(uap->clk); in pl011_console_setup()
2423 if (dev_get_platdata(uap->port.dev)) { in pl011_console_setup()
2426 plat = dev_get_platdata(uap->port.dev); in pl011_console_setup()
2427 if (plat->init) in pl011_console_setup()
2428 plat->init(); in pl011_console_setup()
2431 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_console_setup()
2433 if (uap->vendor->fixed_options) { in pl011_console_setup()
2434 baud = uap->fixed_baud; in pl011_console_setup()
2438 &baud, &parity, &bits, &flow); in pl011_console_setup()
2440 pl011_console_get_options(uap, &baud, &parity, &bits); in pl011_console_setup()
2443 return uart_set_options(&uap->port, co, baud, parity, bits, flow); in pl011_console_setup()
2447 * pl011_console_match - non-standard console matching
2462 * Returns 0 if console matches; otherwise non-zero to use default matching
2478 return -ENODEV; in pl011_console_match()
2481 return -ENODEV; in pl011_console_match()
2484 return -ENODEV; in pl011_console_match()
2493 port = &amba_ports[i]->port; in pl011_console_match()
2495 if (port->mapbase != addr) in pl011_console_match()
2498 co->index = i; in pl011_console_match()
2499 port->cons = co; in pl011_console_match()
2503 return -ENODEV; in pl011_console_match()
2514 .index = -1,
2522 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in qdf2400_e44_putc()
2524 writel(c, port->membase + UART01x_DR); in qdf2400_e44_putc()
2525 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) in qdf2400_e44_putc()
2531 struct earlycon_device *dev = con->data; in qdf2400_e44_early_write()
2533 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); in qdf2400_e44_early_write()
2538 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_putc()
2540 if (port->iotype == UPIO_MEM32) in pl011_putc()
2541 writel(c, port->membase + UART01x_DR); in pl011_putc()
2543 writeb(c, port->membase + UART01x_DR); in pl011_putc()
2544 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_putc()
2550 struct earlycon_device *dev = con->data; in pl011_early_write()
2552 uart_console_write(&dev->port, s, n, pl011_putc); in pl011_early_write()
2558 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) in pl011_getc()
2561 if (port->iotype == UPIO_MEM32) in pl011_getc()
2562 return readl(port->membase + UART01x_DR); in pl011_getc()
2564 return readb(port->membase + UART01x_DR); in pl011_getc()
2569 struct earlycon_device *dev = con->data; in pl011_early_read()
2573 ch = pl011_getc(&dev->port); in pl011_early_read()
2587 * On non-ACPI systems, earlycon is enabled by specifying
2601 if (!device->port.membase) in pl011_early_console_setup()
2602 return -ENODEV; in pl011_early_console_setup()
2604 device->con->write = pl011_early_write; in pl011_early_console_setup()
2605 device->con->read = pl011_early_read; in pl011_early_console_setup()
2612 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2621 * case, the SPCR code will detect the need for the E44 work-around,
2628 if (!device->port.membase) in qdf2400_e44_early_console_setup()
2629 return -ENODEV; in qdf2400_e44_early_console_setup()
2631 device->con->write = qdf2400_e44_early_write; in qdf2400_e44_early_console_setup()
2661 np = dev->of_node; in pl011_probe_dt_alias()
2678 …dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeratio… in pl011_probe_dt_alias()
2708 return -EBUSY; in pl011_find_free_port()
2713 struct uart_port *port = &uap->port; in pl011_get_rs485_mode()
2735 uap->port.dev = dev; in pl011_setup_port()
2736 uap->port.mapbase = mmiobase->start; in pl011_setup_port()
2737 uap->port.membase = base; in pl011_setup_port()
2738 uap->port.fifosize = uap->fifosize; in pl011_setup_port()
2739 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); in pl011_setup_port()
2740 uap->port.flags = UPF_BOOT_AUTOCONF; in pl011_setup_port()
2741 uap->port.line = index; in pl011_setup_port()
2763 dev_err(uap->port.dev, in pl011_register_port()
2764 "Failed to register AMBA-PL011 driver\n"); in pl011_register_port()
2772 ret = uart_add_one_port(&amba_reg, &uap->port); in pl011_register_port()
2789 struct vendor_data *vendor = id->data; in pl011_probe()
2797 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), in pl011_probe()
2800 return -ENOMEM; in pl011_probe()
2802 uap->clk = devm_clk_get(&dev->dev, NULL); in pl011_probe()
2803 if (IS_ERR(uap->clk)) in pl011_probe()
2804 return PTR_ERR(uap->clk); in pl011_probe()
2806 uap->reg_offset = vendor->reg_offset; in pl011_probe()
2807 uap->vendor = vendor; in pl011_probe()
2808 uap->fifosize = vendor->get_fifosize(dev); in pl011_probe()
2809 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in pl011_probe()
2810 uap->port.irq = dev->irq[0]; in pl011_probe()
2811 uap->port.ops = &amba_pl011_pops; in pl011_probe()
2812 uap->port.rs485_config = pl011_rs485_config; in pl011_probe()
2813 uap->port.rs485_supported = pl011_rs485_supported; in pl011_probe()
2814 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); in pl011_probe()
2816 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) { in pl011_probe()
2819 uap->port.iotype = UPIO_MEM; in pl011_probe()
2822 uap->port.iotype = UPIO_MEM32; in pl011_probe()
2825 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n", in pl011_probe()
2827 return -EINVAL; in pl011_probe()
2831 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); in pl011_probe()
2844 uart_remove_one_port(&amba_reg, &uap->port); in pl011_remove()
2854 return -EINVAL; in pl011_suspend()
2856 return uart_suspend_port(&amba_reg, &uap->port); in pl011_suspend()
2864 return -EINVAL; in pl011_resume()
2866 return uart_resume_port(&amba_reg, &uap->port); in pl011_resume()
2880 uap->vendor = &vendor_qdt_qdf2400_e44; in qpdf2400_erratum44_workaround()
2896 * Check the mandatory baud rate parameter in the DT node early in sbsa_uart_probe()
2899 if (pdev->dev.of_node) { in sbsa_uart_probe()
2900 struct device_node *np = pdev->dev.of_node; in sbsa_uart_probe()
2902 ret = of_property_read_u32(np, "current-speed", &baudrate); in sbsa_uart_probe()
2913 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), in sbsa_uart_probe()
2916 return -ENOMEM; in sbsa_uart_probe()
2921 uap->port.irq = ret; in sbsa_uart_probe()
2923 uap->vendor = &vendor_sbsa; in sbsa_uart_probe()
2924 qpdf2400_erratum44_workaround(&pdev->dev, uap); in sbsa_uart_probe()
2926 uap->reg_offset = uap->vendor->reg_offset; in sbsa_uart_probe()
2927 uap->fifosize = 32; in sbsa_uart_probe()
2928 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in sbsa_uart_probe()
2929 uap->port.ops = &sbsa_uart_pops; in sbsa_uart_probe()
2930 uap->fixed_baud = baudrate; in sbsa_uart_probe()
2932 snprintf(uap->type, sizeof(uap->type), "SBSA"); in sbsa_uart_probe()
2936 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); in sbsa_uart_probe()
2949 uart_remove_one_port(&amba_reg, &uap->port); in sbsa_uart_remove()
2954 { .compatible = "arm,sbsa-uart", },
2970 .name = "sbsa-uart",
2996 .name = "uart-pl011",