Lines Matching full:stages
139 #define SIFCTR_TFWM_64 (0UL << 29) /* Transfer Request when 64 empty stages */
140 #define SIFCTR_TFWM_32 (1UL << 29) /* Transfer Request when 32 empty stages */
141 #define SIFCTR_TFWM_24 (2UL << 29) /* Transfer Request when 24 empty stages */
142 #define SIFCTR_TFWM_16 (3UL << 29) /* Transfer Request when 16 empty stages */
143 #define SIFCTR_TFWM_12 (4UL << 29) /* Transfer Request when 12 empty stages */
144 #define SIFCTR_TFWM_8 (5UL << 29) /* Transfer Request when 8 empty stages */
145 #define SIFCTR_TFWM_4 (6UL << 29) /* Transfer Request when 4 empty stages */
151 #define SIFCTR_RFWM_1 (0 << 13) /* Transfer Request when 1 valid stages */
152 #define SIFCTR_RFWM_4 (1 << 13) /* Transfer Request when 4 valid stages */
153 #define SIFCTR_RFWM_8 (2 << 13) /* Transfer Request when 8 valid stages */
154 #define SIFCTR_RFWM_16 (3 << 13) /* Transfer Request when 16 valid stages */
155 #define SIFCTR_RFWM_32 (4 << 13) /* Transfer Request when 32 valid stages */
156 #define SIFCTR_RFWM_64 (5 << 13) /* Transfer Request when 64 valid stages */
157 #define SIFCTR_RFWM_128 (6 << 13) /* Transfer Request when 128 valid stages */
158 #define SIFCTR_RFWM_256 (7 << 13) /* Transfer Request when 256 valid stages */