Lines Matching full:controller
162 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
164 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
178 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
180 return controller->n_words * controller->w_size; in spi_qup_len()
183 static inline bool spi_qup_is_valid_state(struct spi_qup *controller) in spi_qup_is_valid_state() argument
185 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
190 static int spi_qup_vote_bw(struct spi_qup *controller, u32 speed_hz) in spi_qup_vote_bw() argument
195 if (controller->bw_speed_hz == speed_hz) in spi_qup_vote_bw()
199 ret = icc_set_bw(controller->icc_path, 0, needed_peak_bw); in spi_qup_vote_bw()
203 controller->bw_speed_hz = speed_hz; in spi_qup_vote_bw()
207 static int spi_qup_set_state(struct spi_qup *controller, u32 state) in spi_qup_set_state() argument
213 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
222 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
225 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
232 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
233 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
237 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
241 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
252 static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words) in spi_qup_read_from_fifo() argument
254 u8 *rx_buf = controller->rx_buf; in spi_qup_read_from_fifo()
260 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); in spi_qup_read_from_fifo()
262 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_read_from_fifo()
263 controller->rx_bytes, in spi_qup_read_from_fifo()
264 controller->w_size); in spi_qup_read_from_fifo()
267 controller->rx_bytes += num_bytes; in spi_qup_read_from_fifo()
271 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) { in spi_qup_read_from_fifo()
279 shift *= (controller->w_size - i - 1); in spi_qup_read_from_fifo()
280 rx_buf[controller->rx_bytes] = word >> shift; in spi_qup_read_from_fifo()
285 static void spi_qup_read(struct spi_qup *controller, u32 *opflags) in spi_qup_read() argument
288 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_read()
290 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes, in spi_qup_read()
291 controller->w_size); in spi_qup_read()
292 words_per_block = controller->in_blk_sz >> 2; in spi_qup_read()
297 controller->base + QUP_OPERATIONAL); in spi_qup_read()
306 if (!spi_qup_is_flag_set(controller, in spi_qup_read()
314 spi_qup_read_from_fifo(controller, num_words); in spi_qup_read()
319 if (is_block_mode && !spi_qup_is_flag_set(controller, in spi_qup_read()
333 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_read()
336 controller->base + QUP_OPERATIONAL); in spi_qup_read()
340 static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words) in spi_qup_write_to_fifo() argument
342 const u8 *tx_buf = controller->tx_buf; in spi_qup_write_to_fifo()
349 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_write_to_fifo()
350 controller->tx_bytes, in spi_qup_write_to_fifo()
351 controller->w_size); in spi_qup_write_to_fifo()
354 data = tx_buf[controller->tx_bytes + i]; in spi_qup_write_to_fifo()
358 controller->tx_bytes += num_bytes; in spi_qup_write_to_fifo()
360 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); in spi_qup_write_to_fifo()
371 static void spi_qup_write(struct spi_qup *controller) in spi_qup_write() argument
373 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_write()
376 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes, in spi_qup_write()
377 controller->w_size); in spi_qup_write()
378 words_per_block = controller->out_blk_sz >> 2; in spi_qup_write()
383 controller->base + QUP_OPERATIONAL); in spi_qup_write()
393 if (spi_qup_is_flag_set(controller, in spi_qup_write()
400 spi_qup_write_to_fifo(controller, num_words); in spi_qup_write()
405 if (is_block_mode && !spi_qup_is_flag_set(controller, in spi_qup_write()
472 struct spi_controller *host = spi->controller; in spi_qup_do_dma()
546 struct spi_controller *host = spi->controller; in spi_qup_do_pio()
608 static bool spi_qup_data_pending(struct spi_qup *controller) in spi_qup_data_pending() argument
612 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
613 controller->tx_bytes, controller->w_size); in spi_qup_data_pending()
615 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
616 controller->rx_bytes, controller->w_size); in spi_qup_data_pending()
623 struct spi_qup *controller = dev_id; in spi_qup_qup_irq() local
627 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
628 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
629 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
631 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
632 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
636 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); in spi_qup_qup_irq()
638 dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
640 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
642 dev_warn(controller->dev, "INPUT_OVER_RUN\n"); in spi_qup_qup_irq()
649 dev_warn(controller->dev, "CLK_OVER_RUN\n"); in spi_qup_qup_irq()
651 dev_warn(controller->dev, "CLK_UNDER_RUN\n"); in spi_qup_qup_irq()
656 spin_lock(&controller->lock); in spi_qup_qup_irq()
657 if (!controller->error) in spi_qup_qup_irq()
658 controller->error = error; in spi_qup_qup_irq()
659 spin_unlock(&controller->lock); in spi_qup_qup_irq()
661 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
662 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
665 spi_qup_read(controller, &opflags); in spi_qup_qup_irq()
668 spi_qup_write(controller); in spi_qup_qup_irq()
670 if (!spi_qup_data_pending(controller)) in spi_qup_qup_irq()
671 complete(&controller->done); in spi_qup_qup_irq()
675 complete(&controller->done); in spi_qup_qup_irq()
678 if (!spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
679 if (spi_qup_data_pending(controller)) in spi_qup_qup_irq()
682 complete(&controller->done); in spi_qup_qup_irq()
691 struct spi_qup *controller = spi_controller_get_devdata(spi->controller); in spi_qup_io_prep() local
694 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { in spi_qup_io_prep()
695 dev_err(controller->dev, "too big size for loopback %d > %d\n", in spi_qup_io_prep()
696 xfer->len, controller->in_fifo_sz); in spi_qup_io_prep()
700 ret = dev_pm_opp_set_rate(controller->dev, xfer->speed_hz); in spi_qup_io_prep()
702 dev_err(controller->dev, "fail to set frequency %d", in spi_qup_io_prep()
707 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_io_prep()
708 controller->n_words = xfer->len / controller->w_size; in spi_qup_io_prep()
710 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) in spi_qup_io_prep()
711 controller->mode = QUP_IO_M_MODE_FIFO; in spi_qup_io_prep()
712 else if (spi->controller->can_dma && in spi_qup_io_prep()
713 spi->controller->can_dma(spi->controller, spi, xfer) && in spi_qup_io_prep()
714 spi->controller->cur_msg_mapped) in spi_qup_io_prep()
715 controller->mode = QUP_IO_M_MODE_BAM; in spi_qup_io_prep()
717 controller->mode = QUP_IO_M_MODE_BLOCK; in spi_qup_io_prep()
725 struct spi_qup *controller = spi_controller_get_devdata(spi->controller); in spi_qup_io_config() local
729 spin_lock_irqsave(&controller->lock, flags); in spi_qup_io_config()
730 controller->xfer = xfer; in spi_qup_io_config()
731 controller->error = 0; in spi_qup_io_config()
732 controller->rx_bytes = 0; in spi_qup_io_config()
733 controller->tx_bytes = 0; in spi_qup_io_config()
734 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_io_config()
737 if (spi_qup_set_state(controller, QUP_STATE_RESET)) { in spi_qup_io_config()
738 dev_err(controller->dev, "cannot set RESET state\n"); in spi_qup_io_config()
742 switch (controller->mode) { in spi_qup_io_config()
744 writel_relaxed(controller->n_words, in spi_qup_io_config()
745 controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
746 writel_relaxed(controller->n_words, in spi_qup_io_config()
747 controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
749 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
750 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
753 writel_relaxed(controller->n_words, in spi_qup_io_config()
754 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
755 writel_relaxed(controller->n_words, in spi_qup_io_config()
756 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
758 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
759 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
761 if (!controller->qup_v1) { in spi_qup_io_config()
764 input_cnt = controller->base + QUP_MX_INPUT_CNT; in spi_qup_io_config()
774 writel_relaxed(controller->n_words, input_cnt); in spi_qup_io_config()
776 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
780 reinit_completion(&controller->done); in spi_qup_io_config()
781 writel_relaxed(controller->n_words, in spi_qup_io_config()
782 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
783 writel_relaxed(controller->n_words, in spi_qup_io_config()
784 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
786 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
787 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
790 dev_err(controller->dev, "unknown mode = %d\n", in spi_qup_io_config()
791 controller->mode); in spi_qup_io_config()
795 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
799 if (!spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
804 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
805 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
807 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
809 control = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
816 writel_relaxed(control, controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
818 config = readl_relaxed(controller->base + SPI_CONFIG); in spi_qup_io_config()
839 writel_relaxed(config, controller->base + SPI_CONFIG); in spi_qup_io_config()
841 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_io_config()
846 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_io_config()
853 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_io_config()
856 if (!controller->qup_v1) { in spi_qup_io_config()
864 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
867 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); in spi_qup_io_config()
877 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_transfer_one() local
890 reinit_completion(&controller->done); in spi_qup_transfer_one()
892 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
893 controller->xfer = xfer; in spi_qup_transfer_one()
894 controller->error = 0; in spi_qup_transfer_one()
895 controller->rx_bytes = 0; in spi_qup_transfer_one()
896 controller->tx_bytes = 0; in spi_qup_transfer_one()
897 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
899 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
904 spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_transfer_one()
905 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
907 ret = controller->error; in spi_qup_transfer_one()
908 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
910 if (ret && spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
1007 struct spi_qup *controller; in spi_qup_set_cs() local
1011 controller = spi_controller_get_devdata(spi->controller); in spi_qup_set_cs()
1012 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
1020 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
1028 struct spi_qup *controller; in spi_qup_probe() local
1102 controller = spi_controller_get_devdata(host); in spi_qup_probe()
1104 controller->dev = dev; in spi_qup_probe()
1105 controller->base = base; in spi_qup_probe()
1106 controller->iclk = iclk; in spi_qup_probe()
1107 controller->cclk = cclk; in spi_qup_probe()
1108 controller->icc_path = icc_path; in spi_qup_probe()
1109 controller->irq = irq; in spi_qup_probe()
1117 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev); in spi_qup_probe()
1119 if (!controller->qup_v1) in spi_qup_probe()
1122 spin_lock_init(&controller->lock); in spi_qup_probe()
1123 init_completion(&controller->done); in spi_qup_probe()
1142 controller->out_blk_sz = size * 16; in spi_qup_probe()
1144 controller->out_blk_sz = 4; in spi_qup_probe()
1148 controller->in_blk_sz = size * 16; in spi_qup_probe()
1150 controller->in_blk_sz = 4; in spi_qup_probe()
1153 controller->out_fifo_sz = controller->out_blk_sz * (2 << size); in spi_qup_probe()
1156 controller->in_fifo_sz = controller->in_blk_sz * (2 << size); in spi_qup_probe()
1159 controller->in_blk_sz, controller->in_fifo_sz, in spi_qup_probe()
1160 controller->out_blk_sz, controller->out_fifo_sz); in spi_qup_probe()
1164 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_probe()
1173 if (!controller->qup_v1) in spi_qup_probe()
1180 if (controller->qup_v1) in spi_qup_probe()
1189 IRQF_TRIGGER_HIGH, pdev->name, controller); in spi_qup_probe()
1220 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_pm_suspend_runtime() local
1224 config = readl(controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1226 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1228 clk_disable_unprepare(controller->cclk); in spi_qup_pm_suspend_runtime()
1229 spi_qup_vote_bw(controller, 0); in spi_qup_pm_suspend_runtime()
1230 clk_disable_unprepare(controller->iclk); in spi_qup_pm_suspend_runtime()
1238 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_pm_resume_runtime() local
1242 ret = clk_prepare_enable(controller->iclk); in spi_qup_pm_resume_runtime()
1246 ret = clk_prepare_enable(controller->cclk); in spi_qup_pm_resume_runtime()
1248 clk_disable_unprepare(controller->iclk); in spi_qup_pm_resume_runtime()
1253 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1255 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1264 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_suspend() local
1276 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_suspend()
1280 clk_disable_unprepare(controller->cclk); in spi_qup_suspend()
1281 spi_qup_vote_bw(controller, 0); in spi_qup_suspend()
1282 clk_disable_unprepare(controller->iclk); in spi_qup_suspend()
1289 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_resume() local
1292 ret = clk_prepare_enable(controller->iclk); in spi_qup_resume()
1296 ret = clk_prepare_enable(controller->cclk); in spi_qup_resume()
1298 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1302 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_resume()
1313 clk_disable_unprepare(controller->cclk); in spi_qup_resume()
1314 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1322 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_remove() local
1328 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_remove()
1330 dev_warn(&pdev->dev, "failed to reset controller (%pe)\n", in spi_qup_remove()
1333 clk_disable_unprepare(controller->cclk); in spi_qup_remove()
1334 clk_disable_unprepare(controller->iclk); in spi_qup_remove()