1 // SPDX-License-Identifier: (GPL-2.0)
5  * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
104 	u32 clk_gen; /* divider for spi output clock generated by the controller */
114 	return readl(spi->regs + reg);  in mchp_corespi_read()
119 	writel(val, spi->regs + reg);  in mchp_corespi_write()
136 	fifo_max = min(spi->rx_len, FIFO_DEPTH);  in mchp_corespi_read_fifo()
141 		if (spi->rx_buf)  in mchp_corespi_read_fifo()
142 			*spi->rx_buf++ = data;  in mchp_corespi_read_fifo()
145 	spi->rx_len -= i;  in mchp_corespi_read_fifo()
146 	spi->pending -= i;  in mchp_corespi_read_fifo()
214 	fifo_max = min(spi->tx_len, FIFO_DEPTH);  in mchp_corespi_write_fifo()
218 		byte = spi->tx_buf ? *spi->tx_buf++ : 0xaa;  in mchp_corespi_write_fifo()
223 	spi->tx_len -= i;  in mchp_corespi_write_fifo()
224 	spi->pending += i;  in mchp_corespi_write_fifo()
247 	struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);  in mchp_corespi_set_cs()
258 	struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);  in mchp_corespi_setup()
266 	if (spi->mode & SPI_CS_HIGH) {  in mchp_corespi_setup()
286 	/* max. possible spi clock rate is the apb clock rate */  in mchp_corespi_init()
287 	clk_hz = clk_get_rate(spi->clk);  in mchp_corespi_init()
288 	host->max_speed_hz = clk_hz;  in mchp_corespi_init()
327 	if (spi->clk_mode)  in mchp_corespi_set_clk_gen()
332 	mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen);  in mchp_corespi_set_clk_gen()
386 		if (spi->rx_len)  in mchp_corespi_interrupt()
389 		if (spi->tx_len)  in mchp_corespi_interrupt()
392 		if (!spi->rx_len)  in mchp_corespi_interrupt()
402 		dev_err(&host->dev,  in mchp_corespi_interrupt()
404 			spi->rx_len, spi->tx_len);  in mchp_corespi_interrupt()
410 		dev_err(&host->dev,  in mchp_corespi_interrupt()
412 			spi->rx_len, spi->tx_len);  in mchp_corespi_interrupt()
426 	clk_hz = clk_get_rate(spi->clk);  in mchp_corespi_calculate_clkgen()
428 		return -EINVAL;  in mchp_corespi_calculate_clkgen()
432 	 * There are two possible clock modes for the controller generated  in mchp_corespi_calculate_clkgen()
433 	 * clock's division ratio:  in mchp_corespi_calculate_clkgen()
439 	 * clk_gen is the register name for the clock divider on MPFS.  in mchp_corespi_calculate_clkgen()
441 	clk_gen = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;  in mchp_corespi_calculate_clkgen()
444 		clk_gen = fls(clk_gen) - 1;  in mchp_corespi_calculate_clkgen()
447 			return -EINVAL;  in mchp_corespi_calculate_clkgen()
449 		spi->clk_mode = 0;  in mchp_corespi_calculate_clkgen()
451 		spi->clk_mode = 1;  in mchp_corespi_calculate_clkgen()
454 	spi->clk_gen = clk_gen;  in mchp_corespi_calculate_clkgen()
465 	ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz);  in mchp_corespi_transfer_one()
467 		dev_err(&host->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz);  in mchp_corespi_transfer_one()
473 	spi->tx_buf = xfer->tx_buf;  in mchp_corespi_transfer_one()
474 	spi->rx_buf = xfer->rx_buf;  in mchp_corespi_transfer_one()
475 	spi->tx_len = xfer->len;  in mchp_corespi_transfer_one()
476 	spi->rx_len = xfer->len;  in mchp_corespi_transfer_one()
477 	spi->pending = 0;  in mchp_corespi_transfer_one()
479 	mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH)  in mchp_corespi_transfer_one()
480 				   ? FIFO_DEPTH : spi->tx_len);  in mchp_corespi_transfer_one()
482 	if (spi->tx_len)  in mchp_corespi_transfer_one()
490 	struct spi_device *spi_dev = msg->spi;  in mchp_corespi_prepare_message()
494 	mchp_corespi_set_mode(spi, spi_dev->mode);  in mchp_corespi_prepare_message()
507 	host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));  in mchp_corespi_probe()
509 		return dev_err_probe(&pdev->dev, -ENOMEM,  in mchp_corespi_probe()
514 	if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))  in mchp_corespi_probe()
517 	host->num_chipselect = num_cs;  in mchp_corespi_probe()
518 	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;  in mchp_corespi_probe()
519 	host->setup = mchp_corespi_setup;  in mchp_corespi_probe()
520 	host->bits_per_word_mask = SPI_BPW_MASK(8);  in mchp_corespi_probe()
521 	host->transfer_one = mchp_corespi_transfer_one;  in mchp_corespi_probe()
522 	host->prepare_message = mchp_corespi_prepare_message;  in mchp_corespi_probe()
523 	host->set_cs = mchp_corespi_set_cs;  in mchp_corespi_probe()
524 	host->dev.of_node = pdev->dev.of_node;  in mchp_corespi_probe()
528 	spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in mchp_corespi_probe()
529 	if (IS_ERR(spi->regs))  in mchp_corespi_probe()
530 		return PTR_ERR(spi->regs);  in mchp_corespi_probe()
532 	spi->irq = platform_get_irq(pdev, 0);  in mchp_corespi_probe()
533 	if (spi->irq < 0)  in mchp_corespi_probe()
534 		return spi->irq;  in mchp_corespi_probe()
536 	ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt,  in mchp_corespi_probe()
537 			       IRQF_SHARED, dev_name(&pdev->dev), host);  in mchp_corespi_probe()
539 		return dev_err_probe(&pdev->dev, ret,  in mchp_corespi_probe()
542 	spi->clk = devm_clk_get_enabled(&pdev->dev, NULL);  in mchp_corespi_probe()
543 	if (IS_ERR(spi->clk))  in mchp_corespi_probe()
544 		return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk),  in mchp_corespi_probe()
549 	ret = devm_spi_register_controller(&pdev->dev, host);  in mchp_corespi_probe()
552 		return dev_err_probe(&pdev->dev, ret,  in mchp_corespi_probe()
556 	dev_info(&pdev->dev, "Registered SPI controller %d\n", host->bus_num);  in mchp_corespi_probe()
578 	{ .compatible = "microchip,mpfs-spi" },
587 		.name = "microchip-corespi",