Lines Matching +full:imx1 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
10 #include <linux/dma-mapping.h>
26 #include <linux/dma/imx-dma.h>
133 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
138 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
143 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
148 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
156 if (spi_imx->rx_buf) { \
157 *(type *)spi_imx->rx_buf = val; \
158 spi_imx->rx_buf += sizeof(type); \
161 spi_imx->remainder -= sizeof(type); \
169 if (spi_imx->tx_buf) { \
170 val = *(type *)spi_imx->tx_buf; \
171 spi_imx->tx_buf += sizeof(type); \
174 spi_imx->count -= sizeof(type); \
176 writel(val, spi_imx->base + MXC_CSPITXDATA); \
238 if (!use_dma || controller->fallback) in spi_imx_can_dma()
241 if (!controller->dma_rx) in spi_imx_can_dma()
244 if (spi_imx->target_mode) in spi_imx_can_dma()
247 if (transfer->len < spi_imx->devtype_data->fifo_size) in spi_imx_can_dma()
250 spi_imx->dynamic_burst = 0; in spi_imx_can_dma()
259 * outside the range 0 - 3. We therefore need to limit the cs value to avoid
309 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap_u32()
311 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap_u32()
315 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_rx_swap_u32()
321 *(u32 *)spi_imx->rx_buf = val; in spi_imx_buf_rx_swap_u32()
322 spi_imx->rx_buf += sizeof(u32); in spi_imx_buf_rx_swap_u32()
325 spi_imx->remainder -= sizeof(u32); in spi_imx_buf_rx_swap_u32()
333 unaligned = spi_imx->remainder % 4; in spi_imx_buf_rx_swap()
340 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_rx_swap()
345 val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap()
347 while (unaligned--) { in spi_imx_buf_rx_swap()
348 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap()
349 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; in spi_imx_buf_rx_swap()
350 spi_imx->rx_buf++; in spi_imx_buf_rx_swap()
352 spi_imx->remainder--; in spi_imx_buf_rx_swap()
363 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap_u32()
364 val = *(u32 *)spi_imx->tx_buf; in spi_imx_buf_tx_swap_u32()
365 spi_imx->tx_buf += sizeof(u32); in spi_imx_buf_tx_swap_u32()
368 spi_imx->count -= sizeof(u32); in spi_imx_buf_tx_swap_u32()
370 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_tx_swap_u32()
377 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap_u32()
385 unaligned = spi_imx->count % 4; in spi_imx_buf_tx_swap()
392 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_tx_swap()
397 while (unaligned--) { in spi_imx_buf_tx_swap()
398 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap()
399 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); in spi_imx_buf_tx_swap()
400 spi_imx->tx_buf++; in spi_imx_buf_tx_swap()
402 spi_imx->count--; in spi_imx_buf_tx_swap()
405 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap()
410 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); in mx53_ecspi_rx_target()
412 if (spi_imx->rx_buf) { in mx53_ecspi_rx_target()
413 int n_bytes = spi_imx->target_burst % sizeof(val); in mx53_ecspi_rx_target()
418 memcpy(spi_imx->rx_buf, in mx53_ecspi_rx_target()
419 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); in mx53_ecspi_rx_target()
421 spi_imx->rx_buf += n_bytes; in mx53_ecspi_rx_target()
422 spi_imx->target_burst -= n_bytes; in mx53_ecspi_rx_target()
425 spi_imx->remainder -= sizeof(u32); in mx53_ecspi_rx_target()
431 int n_bytes = spi_imx->count % sizeof(val); in mx53_ecspi_tx_target()
436 if (spi_imx->tx_buf) { in mx53_ecspi_tx_target()
437 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, in mx53_ecspi_tx_target()
438 spi_imx->tx_buf, n_bytes); in mx53_ecspi_tx_target()
440 spi_imx->tx_buf += n_bytes; in mx53_ecspi_tx_target()
443 spi_imx->count -= n_bytes; in mx53_ecspi_tx_target()
445 writel(val, spi_imx->base + MXC_CSPITXDATA); in mx53_ecspi_tx_target()
453 * there are two 4-bit dividers, the pre-divider divides by in mx51_ecspi_clkdiv()
454 * $pre, the post-divider by 2^$post in mx51_ecspi_clkdiv()
457 unsigned int fin = spi_imx->spi_clk; in mx51_ecspi_clkdiv()
461 post = fls(fin) - fls(fspi); in mx51_ecspi_clkdiv()
467 post = max(4U, post) - 4; in mx51_ecspi_clkdiv()
469 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", in mx51_ecspi_clkdiv()
474 pre = DIV_ROUND_UP(fin, fspi << post) - 1; in mx51_ecspi_clkdiv()
476 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", in mx51_ecspi_clkdiv()
499 writel(val, spi_imx->base + MX51_ECSPI_INT); in mx51_ecspi_intctrl()
506 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
508 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
515 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
517 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
524 return spi->controller->unused_native_cs; in mx51_ecspi_channel()
530 struct spi_device *spi = msg->spi; in mx51_ecspi_prepare_message()
535 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
540 if (spi_imx->target_mode) in mx51_ecspi_prepare_message()
548 if (spi->mode & SPI_READY) in mx51_ecspi_prepare_message()
549 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); in mx51_ecspi_prepare_message()
558 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_message()
560 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
561 if (spi->mode & SPI_LOOP) in mx51_ecspi_prepare_message()
565 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
572 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_message()
577 if (spi->mode & SPI_CPOL) { in mx51_ecspi_prepare_message()
585 if (spi->mode & SPI_MOSI_IDLE_LOW) in mx51_ecspi_prepare_message()
590 if (spi->mode & SPI_CS_HIGH) in mx51_ecspi_prepare_message()
598 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
603 * SCLK clock, but we will wait two SCLK clock just to be sure. The in mx51_ecspi_prepare_message()
605 * is noticable if the SCLK clock run very slow. In such a case, if in mx51_ecspi_prepare_message()
609 * the change of SCLK polarity as a clock tick already. in mx51_ecspi_prepare_message()
611 * Because spi_imx->spi_bus_clk is only set in prepare_message in mx51_ecspi_prepare_message()
617 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in mx51_ecspi_prepare_message()
618 if (!xfer->speed_hz) in mx51_ecspi_prepare_message()
620 min_speed_hz = min(xfer->speed_hz, min_speed_hz); in mx51_ecspi_prepare_message()
635 bool cpha = (spi->mode & SPI_CPHA); in mx51_configure_cpha()
636 bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; in mx51_configure_cpha()
637 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_configure_cpha()
648 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_configure_cpha()
654 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
659 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_transfer()
660 ctrl |= (spi_imx->target_burst * 8 - 1) in mx51_ecspi_prepare_transfer()
663 if (spi_imx->usedma) { in mx51_ecspi_prepare_transfer()
664 ctrl |= (spi_imx->bits_per_word - 1) in mx51_ecspi_prepare_transfer()
667 if (spi_imx->count >= MX51_ECSPI_CTRL_MAX_BURST) in mx51_ecspi_prepare_transfer()
668 ctrl |= (MX51_ECSPI_CTRL_MAX_BURST * BITS_PER_BYTE - 1) in mx51_ecspi_prepare_transfer()
671 ctrl |= spi_imx->count / DIV_ROUND_UP(spi_imx->bits_per_word, in mx51_ecspi_prepare_transfer()
672 BITS_PER_BYTE) * spi_imx->bits_per_word in mx51_ecspi_prepare_transfer()
677 /* set clock speed */ in mx51_ecspi_prepare_transfer()
680 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); in mx51_ecspi_prepare_transfer()
681 spi_imx->spi_bus_clk = clk; in mx51_ecspi_prepare_transfer()
689 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed) in mx51_ecspi_prepare_transfer()
694 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
703 if (spi_imx->devtype_data->tx_glitch_fixed) in mx51_setup_wml()
704 tx_wml = spi_imx->wml; in mx51_setup_wml()
709 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | in mx51_setup_wml()
711 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | in mx51_setup_wml()
713 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); in mx51_setup_wml()
718 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; in mx51_ecspi_rx_available()
725 readl(spi_imx->base + MXC_CSPIRXDATA); in mx51_ecspi_reset()
768 writel(val, spi_imx->base + MXC_CSPIINT); in mx31_intctrl()
775 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
777 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
792 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx31_prepare_transfer()
794 spi_imx->spi_bus_clk = clk; in mx31_prepare_transfer()
797 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; in mx31_prepare_transfer()
800 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; in mx31_prepare_transfer()
803 if (spi->mode & SPI_CPHA) in mx31_prepare_transfer()
805 if (spi->mode & SPI_CPOL) in mx31_prepare_transfer()
807 if (spi->mode & SPI_CS_HIGH) in mx31_prepare_transfer()
814 if (spi_imx->usedma) in mx31_prepare_transfer()
817 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_prepare_transfer()
819 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
820 if (spi->mode & SPI_LOOP) in mx31_prepare_transfer()
824 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
826 if (spi_imx->usedma) { in mx31_prepare_transfer()
832 spi_imx->base + MX31_CSPI_DMAREG); in mx31_prepare_transfer()
840 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; in mx31_rx_available()
846 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) in mx31_reset()
847 readl(spi_imx->base + MXC_CSPIRXDATA); in mx31_reset()
872 writel(val, spi_imx->base + MXC_CSPIINT); in mx21_intctrl()
879 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
881 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
897 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) in mx21_prepare_transfer()
899 spi_imx->spi_bus_clk = clk; in mx21_prepare_transfer()
901 reg |= spi_imx->bits_per_word - 1; in mx21_prepare_transfer()
903 if (spi->mode & SPI_CPHA) in mx21_prepare_transfer()
905 if (spi->mode & SPI_CPOL) in mx21_prepare_transfer()
907 if (spi->mode & SPI_CS_HIGH) in mx21_prepare_transfer()
912 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_prepare_transfer()
919 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; in mx21_rx_available()
924 writel(1, spi_imx->base + MXC_RESET); in mx21_reset()
947 writel(val, spi_imx->base + MXC_CSPIINT); in mx1_intctrl()
954 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
956 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
971 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx1_prepare_transfer()
973 spi_imx->spi_bus_clk = clk; in mx1_prepare_transfer()
975 reg |= spi_imx->bits_per_word - 1; in mx1_prepare_transfer()
977 if (spi->mode & SPI_CPHA) in mx1_prepare_transfer()
979 if (spi->mode & SPI_CPOL) in mx1_prepare_transfer()
982 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_prepare_transfer()
989 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; in mx1_rx_available()
994 writel(1, spi_imx->base + MXC_RESET); in mx1_reset()
1117 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1118 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1119 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1120 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1121 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1122 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1123 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1124 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1133 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1135 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); in spi_imx_set_burst_len()
1136 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1148 if (!spi_imx->remainder) { in spi_imx_push()
1149 if (spi_imx->dynamic_burst) { in spi_imx_push()
1152 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; in spi_imx_push()
1159 spi_imx->remainder = burst_len; in spi_imx_push()
1161 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_push()
1165 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { in spi_imx_push()
1166 if (!spi_imx->count) in spi_imx_push()
1168 if (spi_imx->dynamic_burst && in spi_imx_push()
1169 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4)) in spi_imx_push()
1171 spi_imx->tx(spi_imx); in spi_imx_push()
1172 spi_imx->txfifo++; in spi_imx_push()
1175 if (!spi_imx->target_mode) in spi_imx_push()
1176 spi_imx->devtype_data->trigger(spi_imx); in spi_imx_push()
1183 while (spi_imx->txfifo && in spi_imx_isr()
1184 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_isr()
1185 spi_imx->rx(spi_imx); in spi_imx_isr()
1186 spi_imx->txfifo--; in spi_imx_isr()
1189 if (spi_imx->count) { in spi_imx_isr()
1194 if (spi_imx->txfifo) { in spi_imx_isr()
1198 spi_imx->devtype_data->intctrl( in spi_imx_isr()
1203 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_isr()
1204 complete(&spi_imx->xfer_done); in spi_imx_isr()
1216 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { in spi_imx_dma_configure()
1227 return -EINVAL; in spi_imx_dma_configure()
1231 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; in spi_imx_dma_configure()
1233 tx.dst_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1234 ret = dmaengine_slave_config(controller->dma_tx, &tx); in spi_imx_dma_configure()
1236 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1241 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; in spi_imx_dma_configure()
1243 rx.src_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1244 ret = dmaengine_slave_config(controller->dma_rx, &rx); in spi_imx_dma_configure()
1246 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1256 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_setupxfer()
1261 if (!t->speed_hz) { in spi_imx_setupxfer()
1262 if (!spi->max_speed_hz) { in spi_imx_setupxfer()
1263 dev_err(&spi->dev, "no speed_hz provided!\n"); in spi_imx_setupxfer()
1264 return -EINVAL; in spi_imx_setupxfer()
1266 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); in spi_imx_setupxfer()
1267 spi_imx->spi_bus_clk = spi->max_speed_hz; in spi_imx_setupxfer()
1269 spi_imx->spi_bus_clk = t->speed_hz; in spi_imx_setupxfer()
1271 spi_imx->bits_per_word = t->bits_per_word; in spi_imx_setupxfer()
1272 spi_imx->count = t->len; in spi_imx_setupxfer()
1275 * Initialize the functions for transfer. To transfer non byte-aligned in spi_imx_setupxfer()
1276 * words, we have to use multiple word-size bursts, we can't use in spi_imx_setupxfer()
1279 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode && in spi_imx_setupxfer()
1280 !(spi->mode & SPI_CS_WORD) && in spi_imx_setupxfer()
1281 (spi_imx->bits_per_word == 8 || in spi_imx_setupxfer()
1282 spi_imx->bits_per_word == 16 || in spi_imx_setupxfer()
1283 spi_imx->bits_per_word == 32)) { in spi_imx_setupxfer()
1285 spi_imx->rx = spi_imx_buf_rx_swap; in spi_imx_setupxfer()
1286 spi_imx->tx = spi_imx_buf_tx_swap; in spi_imx_setupxfer()
1287 spi_imx->dynamic_burst = 1; in spi_imx_setupxfer()
1290 if (spi_imx->bits_per_word <= 8) { in spi_imx_setupxfer()
1291 spi_imx->rx = spi_imx_buf_rx_u8; in spi_imx_setupxfer()
1292 spi_imx->tx = spi_imx_buf_tx_u8; in spi_imx_setupxfer()
1293 } else if (spi_imx->bits_per_word <= 16) { in spi_imx_setupxfer()
1294 spi_imx->rx = spi_imx_buf_rx_u16; in spi_imx_setupxfer()
1295 spi_imx->tx = spi_imx_buf_tx_u16; in spi_imx_setupxfer()
1297 spi_imx->rx = spi_imx_buf_rx_u32; in spi_imx_setupxfer()
1298 spi_imx->tx = spi_imx_buf_tx_u32; in spi_imx_setupxfer()
1300 spi_imx->dynamic_burst = 0; in spi_imx_setupxfer()
1303 if (spi_imx_can_dma(spi_imx->controller, spi, t)) in spi_imx_setupxfer()
1304 spi_imx->usedma = true; in spi_imx_setupxfer()
1306 spi_imx->usedma = false; in spi_imx_setupxfer()
1308 spi_imx->rx_only = ((t->tx_buf == NULL) in spi_imx_setupxfer()
1309 || (t->tx_buf == spi->controller->dummy_tx)); in spi_imx_setupxfer()
1311 if (is_imx53_ecspi(spi_imx) && spi_imx->target_mode) { in spi_imx_setupxfer()
1312 spi_imx->rx = mx53_ecspi_rx_target; in spi_imx_setupxfer()
1313 spi_imx->tx = mx53_ecspi_tx_target; in spi_imx_setupxfer()
1314 spi_imx->target_burst = t->len; in spi_imx_setupxfer()
1317 spi_imx->devtype_data->prepare_transfer(spi_imx, spi); in spi_imx_setupxfer()
1324 struct spi_controller *controller = spi_imx->controller; in spi_imx_sdma_exit()
1326 if (controller->dma_rx) { in spi_imx_sdma_exit()
1327 dma_release_channel(controller->dma_rx); in spi_imx_sdma_exit()
1328 controller->dma_rx = NULL; in spi_imx_sdma_exit()
1331 if (controller->dma_tx) { in spi_imx_sdma_exit()
1332 dma_release_channel(controller->dma_tx); in spi_imx_sdma_exit()
1333 controller->dma_tx = NULL; in spi_imx_sdma_exit()
1342 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; in spi_imx_sdma_init()
1345 controller->dma_tx = dma_request_chan(dev, "tx"); in spi_imx_sdma_init()
1346 if (IS_ERR(controller->dma_tx)) { in spi_imx_sdma_init()
1347 ret = PTR_ERR(controller->dma_tx); in spi_imx_sdma_init()
1349 controller->dma_tx = NULL; in spi_imx_sdma_init()
1354 controller->dma_rx = dma_request_chan(dev, "rx"); in spi_imx_sdma_init()
1355 if (IS_ERR(controller->dma_rx)) { in spi_imx_sdma_init()
1356 ret = PTR_ERR(controller->dma_rx); in spi_imx_sdma_init()
1358 controller->dma_rx = NULL; in spi_imx_sdma_init()
1362 init_completion(&spi_imx->dma_rx_completion); in spi_imx_sdma_init()
1363 init_completion(&spi_imx->dma_tx_completion); in spi_imx_sdma_init()
1364 controller->can_dma = spi_imx_can_dma; in spi_imx_sdma_init()
1365 controller->max_dma_len = MAX_SDMA_BD_BYTES; in spi_imx_sdma_init()
1366 spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX | in spi_imx_sdma_init()
1379 complete(&spi_imx->dma_rx_completion); in spi_imx_dma_rx_callback()
1386 complete(&spi_imx->dma_tx_completion); in spi_imx_dma_tx_callback()
1394 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; in spi_imx_calculate_timeout()
1409 struct spi_controller *controller = spi_imx->controller; in spi_imx_dma_transfer()
1410 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in spi_imx_dma_transfer()
1411 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); in spi_imx_dma_transfer()
1416 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); in spi_imx_dma_transfer()
1417 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { in spi_imx_dma_transfer()
1425 spi_imx->wml = i; in spi_imx_dma_transfer()
1431 if (!spi_imx->devtype_data->setup_wml) { in spi_imx_dma_transfer()
1432 dev_err(spi_imx->dev, "No setup_wml()?\n"); in spi_imx_dma_transfer()
1433 ret = -EINVAL; in spi_imx_dma_transfer()
1436 spi_imx->devtype_data->setup_wml(spi_imx); in spi_imx_dma_transfer()
1442 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, in spi_imx_dma_transfer()
1443 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in spi_imx_dma_transfer()
1446 ret = -EINVAL; in spi_imx_dma_transfer()
1450 desc_rx->callback = spi_imx_dma_rx_callback; in spi_imx_dma_transfer()
1451 desc_rx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1453 reinit_completion(&spi_imx->dma_rx_completion); in spi_imx_dma_transfer()
1454 dma_async_issue_pending(controller->dma_rx); in spi_imx_dma_transfer()
1456 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, in spi_imx_dma_transfer()
1457 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in spi_imx_dma_transfer()
1460 dmaengine_terminate_all(controller->dma_tx); in spi_imx_dma_transfer()
1461 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1462 return -EINVAL; in spi_imx_dma_transfer()
1465 desc_tx->callback = spi_imx_dma_tx_callback; in spi_imx_dma_transfer()
1466 desc_tx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1468 reinit_completion(&spi_imx->dma_tx_completion); in spi_imx_dma_transfer()
1469 dma_async_issue_pending(controller->dma_tx); in spi_imx_dma_transfer()
1471 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_dma_transfer()
1474 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, in spi_imx_dma_transfer()
1477 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); in spi_imx_dma_transfer()
1478 dmaengine_terminate_all(controller->dma_tx); in spi_imx_dma_transfer()
1479 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1480 return -ETIMEDOUT; in spi_imx_dma_transfer()
1483 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, in spi_imx_dma_transfer()
1486 dev_err(&controller->dev, "I/O Error in DMA RX\n"); in spi_imx_dma_transfer()
1487 spi_imx->devtype_data->reset(spi_imx); in spi_imx_dma_transfer()
1488 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1489 return -ETIMEDOUT; in spi_imx_dma_transfer()
1495 transfer->error |= SPI_TRANS_FAIL_NO_START; in spi_imx_dma_transfer()
1502 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_pio_transfer()
1506 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer()
1507 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer()
1508 spi_imx->count = transfer->len; in spi_imx_pio_transfer()
1509 spi_imx->txfifo = 0; in spi_imx_pio_transfer()
1510 spi_imx->remainder = 0; in spi_imx_pio_transfer()
1512 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer()
1516 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); in spi_imx_pio_transfer()
1518 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_pio_transfer()
1520 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, in spi_imx_pio_transfer()
1523 dev_err(&spi->dev, "I/O Error in PIO\n"); in spi_imx_pio_transfer()
1524 spi_imx->devtype_data->reset(spi_imx); in spi_imx_pio_transfer()
1525 return -ETIMEDOUT; in spi_imx_pio_transfer()
1534 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_poll_transfer()
1537 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_poll_transfer()
1538 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_poll_transfer()
1539 spi_imx->count = transfer->len; in spi_imx_poll_transfer()
1540 spi_imx->txfifo = 0; in spi_imx_poll_transfer()
1541 spi_imx->remainder = 0; in spi_imx_poll_transfer()
1549 timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies; in spi_imx_poll_transfer()
1550 while (spi_imx->txfifo) { in spi_imx_poll_transfer()
1552 while (spi_imx->txfifo && in spi_imx_poll_transfer()
1553 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_poll_transfer()
1554 spi_imx->rx(spi_imx); in spi_imx_poll_transfer()
1555 spi_imx->txfifo--; in spi_imx_poll_transfer()
1559 if (spi_imx->count) { in spi_imx_poll_transfer()
1564 if (spi_imx->txfifo && in spi_imx_poll_transfer()
1567 dev_err_ratelimited(&spi->dev, in spi_imx_poll_transfer()
1568 "timeout period reached: jiffies: %lu- falling back to interrupt mode\n", in spi_imx_poll_transfer()
1569 jiffies - timeout); in spi_imx_poll_transfer()
1582 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_pio_transfer_target()
1586 transfer->len > MX53_MAX_TRANSFER_BYTES) { in spi_imx_pio_transfer_target()
1587 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", in spi_imx_pio_transfer_target()
1589 return -EMSGSIZE; in spi_imx_pio_transfer_target()
1592 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer_target()
1593 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer_target()
1594 spi_imx->count = transfer->len; in spi_imx_pio_transfer_target()
1595 spi_imx->txfifo = 0; in spi_imx_pio_transfer_target()
1596 spi_imx->remainder = 0; in spi_imx_pio_transfer_target()
1598 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer_target()
1599 spi_imx->target_aborted = false; in spi_imx_pio_transfer_target()
1603 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); in spi_imx_pio_transfer_target()
1605 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || in spi_imx_pio_transfer_target()
1606 spi_imx->target_aborted) { in spi_imx_pio_transfer_target()
1607 dev_dbg(&spi->dev, "interrupted\n"); in spi_imx_pio_transfer_target()
1608 ret = -EINTR; in spi_imx_pio_transfer_target()
1617 if (spi_imx->devtype_data->disable) in spi_imx_pio_transfer_target()
1618 spi_imx->devtype_data->disable(spi_imx); in spi_imx_pio_transfer_target()
1627 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_transfer_one()
1631 transfer->effective_speed_hz = spi_imx->spi_bus_clk; in spi_imx_transfer_one()
1634 while (spi_imx->devtype_data->rx_available(spi_imx)) in spi_imx_transfer_one()
1635 readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_transfer_one()
1637 if (spi_imx->target_mode) in spi_imx_transfer_one()
1645 if (spi_imx->usedma) in spi_imx_transfer_one()
1652 byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1; in spi_imx_transfer_one()
1655 if (transfer->len < byte_limit) in spi_imx_transfer_one()
1663 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, in spi_imx_setup()
1664 spi->mode, spi->bits_per_word, spi->max_speed_hz); in spi_imx_setup()
1679 ret = pm_runtime_resume_and_get(spi_imx->dev); in spi_imx_prepare_message()
1681 dev_err(spi_imx->dev, "failed to enable clock\n"); in spi_imx_prepare_message()
1685 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); in spi_imx_prepare_message()
1687 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_prepare_message()
1688 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_prepare_message()
1699 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_unprepare_message()
1700 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_unprepare_message()
1708 spi_imx->target_aborted = true; in spi_imx_target_abort()
1709 complete(&spi_imx->xfer_done); in spi_imx_target_abort()
1716 struct device_node *np = pdev->dev.of_node; in spi_imx_probe()
1722 of_device_get_match_data(&pdev->dev); in spi_imx_probe()
1726 target_mode = devtype_data->has_targetmode && in spi_imx_probe()
1727 of_property_read_bool(np, "spi-slave"); in spi_imx_probe()
1729 controller = spi_alloc_target(&pdev->dev, in spi_imx_probe()
1732 controller = spi_alloc_host(&pdev->dev, in spi_imx_probe()
1735 return -ENOMEM; in spi_imx_probe()
1737 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); in spi_imx_probe()
1745 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); in spi_imx_probe()
1746 controller->bus_num = np ? -1 : pdev->id; in spi_imx_probe()
1747 controller->use_gpio_descriptors = true; in spi_imx_probe()
1750 spi_imx->controller = controller; in spi_imx_probe()
1751 spi_imx->dev = &pdev->dev; in spi_imx_probe()
1752 spi_imx->target_mode = target_mode; in spi_imx_probe()
1754 spi_imx->devtype_data = devtype_data; in spi_imx_probe()
1762 if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) in spi_imx_probe()
1763 controller->num_chipselect = val; in spi_imx_probe()
1765 controller->num_chipselect = 3; in spi_imx_probe()
1767 controller->transfer_one = spi_imx_transfer_one; in spi_imx_probe()
1768 controller->setup = spi_imx_setup; in spi_imx_probe()
1769 controller->cleanup = spi_imx_cleanup; in spi_imx_probe()
1770 controller->prepare_message = spi_imx_prepare_message; in spi_imx_probe()
1771 controller->unprepare_message = spi_imx_unprepare_message; in spi_imx_probe()
1772 controller->target_abort = spi_imx_target_abort; in spi_imx_probe()
1773 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS | in spi_imx_probe()
1778 controller->mode_bits |= SPI_LOOP | SPI_READY; in spi_imx_probe()
1781 controller->mode_bits |= SPI_RX_CPHA_FLIP; in spi_imx_probe()
1784 device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) in spi_imx_probe()
1786 * When using HW-CS implementing SPI_CS_WORD can be done by just in spi_imx_probe()
1790 controller->mode_bits |= SPI_CS_WORD; in spi_imx_probe()
1793 controller->max_native_cs = 4; in spi_imx_probe()
1794 controller->flags |= SPI_CONTROLLER_GPIO_SS; in spi_imx_probe()
1797 spi_imx->spi_drctl = spi_drctl; in spi_imx_probe()
1799 init_completion(&spi_imx->xfer_done); in spi_imx_probe()
1801 spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in spi_imx_probe()
1802 if (IS_ERR(spi_imx->base)) { in spi_imx_probe()
1803 ret = PTR_ERR(spi_imx->base); in spi_imx_probe()
1806 spi_imx->base_phys = res->start; in spi_imx_probe()
1814 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, in spi_imx_probe()
1815 dev_name(&pdev->dev), spi_imx); in spi_imx_probe()
1817 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in spi_imx_probe()
1821 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in spi_imx_probe()
1822 if (IS_ERR(spi_imx->clk_ipg)) { in spi_imx_probe()
1823 ret = PTR_ERR(spi_imx->clk_ipg); in spi_imx_probe()
1827 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); in spi_imx_probe()
1828 if (IS_ERR(spi_imx->clk_per)) { in spi_imx_probe()
1829 ret = PTR_ERR(spi_imx->clk_per); in spi_imx_probe()
1833 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_probe()
1837 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_probe()
1841 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); in spi_imx_probe()
1842 pm_runtime_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1843 pm_runtime_get_noresume(spi_imx->dev); in spi_imx_probe()
1844 pm_runtime_set_active(spi_imx->dev); in spi_imx_probe()
1845 pm_runtime_enable(spi_imx->dev); in spi_imx_probe()
1847 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); in spi_imx_probe()
1852 if (spi_imx->devtype_data->has_dmamode) { in spi_imx_probe()
1853 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller); in spi_imx_probe()
1854 if (ret == -EPROBE_DEFER) in spi_imx_probe()
1858 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", in spi_imx_probe()
1862 spi_imx->devtype_data->reset(spi_imx); in spi_imx_probe()
1864 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_probe()
1866 controller->dev.of_node = pdev->dev.of_node; in spi_imx_probe()
1869 dev_err_probe(&pdev->dev, ret, "register controller failed\n"); in spi_imx_probe()
1873 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_probe()
1874 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_probe()
1879 if (spi_imx->devtype_data->has_dmamode) in spi_imx_probe()
1882 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1883 pm_runtime_set_suspended(&pdev->dev); in spi_imx_probe()
1884 pm_runtime_disable(spi_imx->dev); in spi_imx_probe()
1886 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_probe()
1888 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_probe()
1903 ret = pm_runtime_get_sync(spi_imx->dev); in spi_imx_remove()
1905 writel(0, spi_imx->base + MXC_CSPICTRL); in spi_imx_remove()
1907 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n"); in spi_imx_remove()
1909 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_remove()
1910 pm_runtime_put_sync(spi_imx->dev); in spi_imx_remove()
1911 pm_runtime_disable(spi_imx->dev); in spi_imx_remove()
1924 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_runtime_resume()
1928 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_runtime_resume()
1930 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_resume()
1944 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_suspend()
1945 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_runtime_suspend()