Lines Matching +full:spi +full:- +full:only +full:- +full:use +full:- +full:cs1 +full:- +full:sel
1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
22 #include <linux/dma/imx-dma.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/spi_bitbang.h>
34 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
125 { .compatible = "fsl,imx7ulp-spi", },
133 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
135 if (fsl_lpspi->rx_buf) { \
136 *(type *)fsl_lpspi->rx_buf = val; \
137 fsl_lpspi->rx_buf += sizeof(type); \
146 if (fsl_lpspi->tx_buf) { \
147 val = *(type *)fsl_lpspi->tx_buf; \
148 fsl_lpspi->tx_buf += sizeof(type); \
151 fsl_lpspi->remain -= sizeof(type); \
152 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
165 writel(enable, fsl_lpspi->base + IMX7ULP_IER); in LPSPI_BUF_TX()
174 struct spi_device *spi, in fsl_lpspi_can_dma() argument
179 if (!controller->dma_rx) in fsl_lpspi_can_dma()
182 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word); in fsl_lpspi_can_dma()
202 ret = pm_runtime_resume_and_get(fsl_lpspi->dev); in lpspi_prepare_xfer_hardware()
204 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); in lpspi_prepare_xfer_hardware()
216 pm_runtime_mark_last_busy(fsl_lpspi->dev); in lpspi_unprepare_xfer_hardware()
217 pm_runtime_put_autosuspend(fsl_lpspi->dev); in lpspi_unprepare_xfer_hardware()
227 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; in fsl_lpspi_write_tx_fifo()
229 while (txfifo_cnt < fsl_lpspi->txfifosize) { in fsl_lpspi_write_tx_fifo()
230 if (!fsl_lpspi->remain) in fsl_lpspi_write_tx_fifo()
232 fsl_lpspi->tx(fsl_lpspi); in fsl_lpspi_write_tx_fifo()
236 if (txfifo_cnt < fsl_lpspi->txfifosize) { in fsl_lpspi_write_tx_fifo()
237 if (!fsl_lpspi->is_target) { in fsl_lpspi_write_tx_fifo()
238 temp = readl(fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_write_tx_fifo()
240 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_write_tx_fifo()
250 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY)) in fsl_lpspi_read_rx_fifo()
251 fsl_lpspi->rx(fsl_lpspi); in fsl_lpspi_read_rx_fifo()
258 temp |= fsl_lpspi->config.bpw - 1; in fsl_lpspi_set_cmd()
259 temp |= (fsl_lpspi->config.mode & 0x3) << 30; in fsl_lpspi_set_cmd()
260 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; in fsl_lpspi_set_cmd()
261 if (!fsl_lpspi->is_target) { in fsl_lpspi_set_cmd()
262 temp |= fsl_lpspi->config.prescale << 27; in fsl_lpspi_set_cmd()
268 if (!fsl_lpspi->usedma) { in fsl_lpspi_set_cmd()
270 if (fsl_lpspi->is_first_byte) in fsl_lpspi_set_cmd()
276 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_set_cmd()
278 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp); in fsl_lpspi_set_cmd()
285 if (!fsl_lpspi->usedma) in fsl_lpspi_set_watermark()
286 temp = fsl_lpspi->watermark >> 1 | in fsl_lpspi_set_watermark()
287 (fsl_lpspi->watermark >> 1) << 16; in fsl_lpspi_set_watermark()
289 temp = fsl_lpspi->watermark >> 1; in fsl_lpspi_set_watermark()
291 writel(temp, fsl_lpspi->base + IMX7ULP_FCR); in fsl_lpspi_set_watermark()
293 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp); in fsl_lpspi_set_watermark()
298 struct lpspi_config config = fsl_lpspi->config; in fsl_lpspi_set_bitrate()
302 perclk_rate = clk_get_rate(fsl_lpspi->clk_per); in fsl_lpspi_set_bitrate()
305 dev_err(fsl_lpspi->dev, in fsl_lpspi_set_bitrate()
307 return -EINVAL; in fsl_lpspi_set_bitrate()
311 dev_err(fsl_lpspi->dev, in fsl_lpspi_set_bitrate()
312 "per-clk should be at least two times of transfer speed"); in fsl_lpspi_set_bitrate()
313 return -EINVAL; in fsl_lpspi_set_bitrate()
317 scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2; in fsl_lpspi_set_bitrate()
319 fsl_lpspi->config.prescale = prescale; in fsl_lpspi_set_bitrate()
325 return -EINVAL; in fsl_lpspi_set_bitrate()
328 fsl_lpspi->base + IMX7ULP_CCR); in fsl_lpspi_set_bitrate()
330 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n", in fsl_lpspi_set_bitrate()
344 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) { in fsl_lpspi_dma_configure()
355 return -EINVAL; in fsl_lpspi_dma_configure()
359 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR; in fsl_lpspi_dma_configure()
362 ret = dmaengine_slave_config(controller->dma_tx, &tx); in fsl_lpspi_dma_configure()
364 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n", in fsl_lpspi_dma_configure()
370 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR; in fsl_lpspi_dma_configure()
373 ret = dmaengine_slave_config(controller->dma_rx, &rx); in fsl_lpspi_dma_configure()
375 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n", in fsl_lpspi_dma_configure()
388 if (!fsl_lpspi->is_target) { in fsl_lpspi_config()
396 if (!fsl_lpspi->is_target) in fsl_lpspi_config()
400 if (fsl_lpspi->config.mode & SPI_CS_HIGH) in fsl_lpspi_config()
402 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1); in fsl_lpspi_config()
404 temp = readl(fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_config()
406 writel(temp, fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_config()
409 if (fsl_lpspi->usedma) in fsl_lpspi_config()
411 writel(temp, fsl_lpspi->base + IMX7ULP_DER); in fsl_lpspi_config()
417 struct spi_device *spi, in fsl_lpspi_setup_transfer() argument
421 spi_controller_get_devdata(spi->controller); in fsl_lpspi_setup_transfer()
424 return -EINVAL; in fsl_lpspi_setup_transfer()
426 fsl_lpspi->config.mode = spi->mode; in fsl_lpspi_setup_transfer()
427 fsl_lpspi->config.bpw = t->bits_per_word; in fsl_lpspi_setup_transfer()
428 fsl_lpspi->config.speed_hz = t->speed_hz; in fsl_lpspi_setup_transfer()
429 if (fsl_lpspi->is_only_cs1) in fsl_lpspi_setup_transfer()
430 fsl_lpspi->config.chip_select = 1; in fsl_lpspi_setup_transfer()
432 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0); in fsl_lpspi_setup_transfer()
434 if (!fsl_lpspi->config.speed_hz) in fsl_lpspi_setup_transfer()
435 fsl_lpspi->config.speed_hz = spi->max_speed_hz; in fsl_lpspi_setup_transfer()
436 if (!fsl_lpspi->config.bpw) in fsl_lpspi_setup_transfer()
437 fsl_lpspi->config.bpw = spi->bits_per_word; in fsl_lpspi_setup_transfer()
440 if (fsl_lpspi->config.bpw <= 8) { in fsl_lpspi_setup_transfer()
441 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8; in fsl_lpspi_setup_transfer()
442 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8; in fsl_lpspi_setup_transfer()
443 } else if (fsl_lpspi->config.bpw <= 16) { in fsl_lpspi_setup_transfer()
444 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16; in fsl_lpspi_setup_transfer()
445 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16; in fsl_lpspi_setup_transfer()
447 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32; in fsl_lpspi_setup_transfer()
448 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32; in fsl_lpspi_setup_transfer()
451 if (t->len <= fsl_lpspi->txfifosize) in fsl_lpspi_setup_transfer()
452 fsl_lpspi->watermark = t->len; in fsl_lpspi_setup_transfer()
454 fsl_lpspi->watermark = fsl_lpspi->txfifosize; in fsl_lpspi_setup_transfer()
456 if (fsl_lpspi_can_dma(controller, spi, t)) in fsl_lpspi_setup_transfer()
457 fsl_lpspi->usedma = true; in fsl_lpspi_setup_transfer()
459 fsl_lpspi->usedma = false; in fsl_lpspi_setup_transfer()
469 fsl_lpspi->target_aborted = true; in fsl_lpspi_target_abort()
470 if (!fsl_lpspi->usedma) in fsl_lpspi_target_abort()
471 complete(&fsl_lpspi->xfer_done); in fsl_lpspi_target_abort()
473 complete(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_target_abort()
474 complete(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_target_abort()
485 if (fsl_lpspi->is_target) { in fsl_lpspi_wait_for_completion()
486 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) || in fsl_lpspi_wait_for_completion()
487 fsl_lpspi->target_aborted) { in fsl_lpspi_wait_for_completion()
488 dev_dbg(fsl_lpspi->dev, "interrupted\n"); in fsl_lpspi_wait_for_completion()
489 return -EINTR; in fsl_lpspi_wait_for_completion()
492 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) { in fsl_lpspi_wait_for_completion()
493 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n"); in fsl_lpspi_wait_for_completion()
494 return -ETIMEDOUT; in fsl_lpspi_wait_for_completion()
505 if (!fsl_lpspi->usedma) { in fsl_lpspi_reset()
512 writel(temp, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_reset()
516 writel(temp, fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_reset()
525 complete(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_rx_callback()
532 complete(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_tx_callback()
541 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz; in fsl_lpspi_calculate_timeout()
557 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in fsl_lpspi_dma_transfer()
564 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, in fsl_lpspi_dma_transfer()
565 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in fsl_lpspi_dma_transfer()
568 return -EINVAL; in fsl_lpspi_dma_transfer()
570 desc_rx->callback = fsl_lpspi_dma_rx_callback; in fsl_lpspi_dma_transfer()
571 desc_rx->callback_param = (void *)fsl_lpspi; in fsl_lpspi_dma_transfer()
573 reinit_completion(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_transfer()
574 dma_async_issue_pending(controller->dma_rx); in fsl_lpspi_dma_transfer()
576 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, in fsl_lpspi_dma_transfer()
577 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in fsl_lpspi_dma_transfer()
580 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
581 return -EINVAL; in fsl_lpspi_dma_transfer()
584 desc_tx->callback = fsl_lpspi_dma_tx_callback; in fsl_lpspi_dma_transfer()
585 desc_tx->callback_param = (void *)fsl_lpspi; in fsl_lpspi_dma_transfer()
587 reinit_completion(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_transfer()
588 dma_async_issue_pending(controller->dma_tx); in fsl_lpspi_dma_transfer()
590 fsl_lpspi->target_aborted = false; in fsl_lpspi_dma_transfer()
592 if (!fsl_lpspi->is_target) { in fsl_lpspi_dma_transfer()
594 transfer->len); in fsl_lpspi_dma_transfer()
597 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion, in fsl_lpspi_dma_transfer()
600 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n"); in fsl_lpspi_dma_transfer()
601 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
602 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
604 return -ETIMEDOUT; in fsl_lpspi_dma_transfer()
607 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion, in fsl_lpspi_dma_transfer()
610 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n"); in fsl_lpspi_dma_transfer()
611 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
612 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
614 return -ETIMEDOUT; in fsl_lpspi_dma_transfer()
617 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) || in fsl_lpspi_dma_transfer()
618 fsl_lpspi->target_aborted) { in fsl_lpspi_dma_transfer()
619 dev_dbg(fsl_lpspi->dev, in fsl_lpspi_dma_transfer()
621 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
622 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
624 return -EINTR; in fsl_lpspi_dma_transfer()
627 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) || in fsl_lpspi_dma_transfer()
628 fsl_lpspi->target_aborted) { in fsl_lpspi_dma_transfer()
629 dev_dbg(fsl_lpspi->dev, in fsl_lpspi_dma_transfer()
631 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
632 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
634 return -EINTR; in fsl_lpspi_dma_transfer()
645 if (controller->dma_rx) { in fsl_lpspi_dma_exit()
646 dma_release_channel(controller->dma_rx); in fsl_lpspi_dma_exit()
647 controller->dma_rx = NULL; in fsl_lpspi_dma_exit()
650 if (controller->dma_tx) { in fsl_lpspi_dma_exit()
651 dma_release_channel(controller->dma_tx); in fsl_lpspi_dma_exit()
652 controller->dma_tx = NULL; in fsl_lpspi_dma_exit()
663 controller->dma_tx = dma_request_chan(dev, "tx"); in fsl_lpspi_dma_init()
664 if (IS_ERR(controller->dma_tx)) { in fsl_lpspi_dma_init()
665 ret = PTR_ERR(controller->dma_tx); in fsl_lpspi_dma_init()
667 controller->dma_tx = NULL; in fsl_lpspi_dma_init()
672 controller->dma_rx = dma_request_chan(dev, "rx"); in fsl_lpspi_dma_init()
673 if (IS_ERR(controller->dma_rx)) { in fsl_lpspi_dma_init()
674 ret = PTR_ERR(controller->dma_rx); in fsl_lpspi_dma_init()
676 controller->dma_rx = NULL; in fsl_lpspi_dma_init()
680 init_completion(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_init()
681 init_completion(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_init()
682 controller->can_dma = fsl_lpspi_can_dma; in fsl_lpspi_dma_init()
683 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES; in fsl_lpspi_dma_init()
698 fsl_lpspi->tx_buf = t->tx_buf; in fsl_lpspi_pio_transfer()
699 fsl_lpspi->rx_buf = t->rx_buf; in fsl_lpspi_pio_transfer()
700 fsl_lpspi->remain = t->len; in fsl_lpspi_pio_transfer()
702 reinit_completion(&fsl_lpspi->xfer_done); in fsl_lpspi_pio_transfer()
703 fsl_lpspi->target_aborted = false; in fsl_lpspi_pio_transfer()
717 struct spi_device *spi, in fsl_lpspi_transfer_one() argument
724 fsl_lpspi->is_first_byte = true; in fsl_lpspi_transfer_one()
725 ret = fsl_lpspi_setup_transfer(controller, spi, t); in fsl_lpspi_transfer_one()
730 fsl_lpspi->is_first_byte = false; in fsl_lpspi_transfer_one()
732 if (fsl_lpspi->usedma) in fsl_lpspi_transfer_one()
747 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER); in fsl_lpspi_isr()
749 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
759 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) { in fsl_lpspi_isr()
760 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
766 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
767 complete(&fsl_lpspi->xfer_done); in fsl_lpspi_isr()
783 ret = clk_prepare_enable(fsl_lpspi->clk_per); in fsl_lpspi_runtime_resume()
787 ret = clk_prepare_enable(fsl_lpspi->clk_ipg); in fsl_lpspi_runtime_resume()
789 clk_disable_unprepare(fsl_lpspi->clk_per); in fsl_lpspi_runtime_resume()
803 clk_disable_unprepare(fsl_lpspi->clk_per); in fsl_lpspi_runtime_suspend()
804 clk_disable_unprepare(fsl_lpspi->clk_ipg); in fsl_lpspi_runtime_suspend()
812 struct device *dev = fsl_lpspi->dev; in fsl_lpspi_init_rpm()
831 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave"); in fsl_lpspi_probe()
833 controller = spi_alloc_target(&pdev->dev, in fsl_lpspi_probe()
836 controller = spi_alloc_host(&pdev->dev, in fsl_lpspi_probe()
840 return -ENOMEM; in fsl_lpspi_probe()
845 fsl_lpspi->dev = &pdev->dev; in fsl_lpspi_probe()
846 fsl_lpspi->is_target = is_target; in fsl_lpspi_probe()
847 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node, in fsl_lpspi_probe()
848 "fsl,spi-only-use-cs1-sel"); in fsl_lpspi_probe()
850 init_completion(&fsl_lpspi->xfer_done); in fsl_lpspi_probe()
852 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in fsl_lpspi_probe()
853 if (IS_ERR(fsl_lpspi->base)) { in fsl_lpspi_probe()
854 ret = PTR_ERR(fsl_lpspi->base); in fsl_lpspi_probe()
857 fsl_lpspi->base_phys = res->start; in fsl_lpspi_probe()
865 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0, in fsl_lpspi_probe()
866 dev_name(&pdev->dev), fsl_lpspi); in fsl_lpspi_probe()
868 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in fsl_lpspi_probe()
872 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per"); in fsl_lpspi_probe()
873 if (IS_ERR(fsl_lpspi->clk_per)) { in fsl_lpspi_probe()
874 ret = PTR_ERR(fsl_lpspi->clk_per); in fsl_lpspi_probe()
878 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in fsl_lpspi_probe()
879 if (IS_ERR(fsl_lpspi->clk_ipg)) { in fsl_lpspi_probe()
880 ret = PTR_ERR(fsl_lpspi->clk_ipg); in fsl_lpspi_probe()
889 ret = pm_runtime_get_sync(fsl_lpspi->dev); in fsl_lpspi_probe()
891 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); in fsl_lpspi_probe()
895 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM); in fsl_lpspi_probe()
896 fsl_lpspi->txfifosize = 1 << (temp & 0x0f); in fsl_lpspi_probe()
897 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f); in fsl_lpspi_probe()
898 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs", in fsl_lpspi_probe()
900 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi")) in fsl_lpspi_probe()
906 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); in fsl_lpspi_probe()
907 controller->transfer_one = fsl_lpspi_transfer_one; in fsl_lpspi_probe()
908 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; in fsl_lpspi_probe()
909 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; in fsl_lpspi_probe()
910 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in fsl_lpspi_probe()
911 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; in fsl_lpspi_probe()
912 controller->dev.of_node = pdev->dev.of_node; in fsl_lpspi_probe()
913 controller->bus_num = pdev->id; in fsl_lpspi_probe()
914 controller->num_chipselect = num_cs; in fsl_lpspi_probe()
915 controller->target_abort = fsl_lpspi_target_abort; in fsl_lpspi_probe()
916 if (!fsl_lpspi->is_target) in fsl_lpspi_probe()
917 controller->use_gpio_descriptors = true; in fsl_lpspi_probe()
919 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller); in fsl_lpspi_probe()
920 if (ret == -EPROBE_DEFER) in fsl_lpspi_probe()
923 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret); in fsl_lpspi_probe()
931 ret = devm_spi_register_controller(&pdev->dev, controller); in fsl_lpspi_probe()
933 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n"); in fsl_lpspi_probe()
937 pm_runtime_mark_last_busy(fsl_lpspi->dev); in fsl_lpspi_probe()
938 pm_runtime_put_autosuspend(fsl_lpspi->dev); in fsl_lpspi_probe()
945 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev); in fsl_lpspi_probe()
946 pm_runtime_put_sync(fsl_lpspi->dev); in fsl_lpspi_probe()
947 pm_runtime_disable(fsl_lpspi->dev); in fsl_lpspi_probe()
962 pm_runtime_disable(fsl_lpspi->dev); in fsl_lpspi_remove()