Lines Matching +full:rclk +full:- +full:en
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
307 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
314 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); in cqspi_get_rd_sram_level()
324 dma_status = readl(cqspi->iobase + in cqspi_get_versal_dma_status()
326 writel(dma_status, cqspi->iobase + in cqspi_get_versal_dma_status()
336 struct device *device = &cqspi->pdev->dev; in cqspi_irq_handler()
342 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
345 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
347 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { in cqspi_irq_handler()
348 if (ddata->get_dma_status(cqspi)) { in cqspi_irq_handler()
349 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
354 else if (!cqspi->slow_sram) in cqspi_irq_handler()
360 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
369 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; in cqspi_calc_rdreg()
370 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; in cqspi_calc_rdreg()
371 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; in cqspi_calc_rdreg()
380 if (!op->dummy.nbytes) in cqspi_calc_dummy()
383 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); in cqspi_calc_dummy()
384 if (op->cmd.dtr) in cqspi_calc_dummy()
413 dev_err(&cqspi->pdev->dev, in cqspi_wait_idle()
416 return -ETIMEDOUT; in cqspi_wait_idle()
425 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd()
438 dev_err(&cqspi->pdev->dev, in cqspi_exec_flash_cmd()
451 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_setup_opcode_ext()
452 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext()
456 if (op->cmd.nbytes != 2) in cqspi_setup_opcode_ext()
457 return -EINVAL; in cqspi_setup_opcode_ext()
460 ext = op->cmd.opcode & 0xff; in cqspi_setup_opcode_ext()
473 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_enable_dtr()
474 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr()
484 if (op->cmd.dtr) { in cqspi_enable_dtr()
505 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_read()
506 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read()
507 u8 *rxbuf = op->data.buf.in; in cqspi_command_read()
509 size_t n_rx = op->data.nbytes; in cqspi_command_read()
521 dev_err(&cqspi->pdev->dev, in cqspi_command_read()
524 return -EINVAL; in cqspi_command_read()
527 if (op->cmd.dtr) in cqspi_command_read()
528 opcode = op->cmd.opcode >> 8; in cqspi_command_read()
530 opcode = op->cmd.opcode; in cqspi_command_read()
539 return -EOPNOTSUPP; in cqspi_command_read()
548 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) in cqspi_command_read()
552 if (op->addr.nbytes) { in cqspi_command_read()
554 reg |= ((op->addr.nbytes - 1) & in cqspi_command_read()
558 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_read()
575 read_len = n_rx - read_len; in cqspi_command_read()
588 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_write()
589 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write()
591 const u8 *txbuf = op->data.buf.out; in cqspi_command_write()
592 size_t n_tx = op->data.nbytes; in cqspi_command_write()
603 dev_err(&cqspi->pdev->dev, in cqspi_command_write()
606 return -EINVAL; in cqspi_command_write()
612 if (op->cmd.dtr) in cqspi_command_write()
613 opcode = op->cmd.opcode >> 8; in cqspi_command_write()
615 opcode = op->cmd.opcode; in cqspi_command_write()
619 if (op->addr.nbytes) { in cqspi_command_write()
621 reg |= ((op->addr.nbytes - 1) & in cqspi_command_write()
625 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_write()
630 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) in cqspi_command_write()
640 write_len = n_tx - 4; in cqspi_command_write()
657 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read_setup()
658 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup()
668 if (op->cmd.dtr) in cqspi_read_setup()
669 opcode = op->cmd.opcode >> 8; in cqspi_read_setup()
671 opcode = op->cmd.opcode; in cqspi_read_setup()
680 return -EOPNOTSUPP; in cqspi_read_setup()
691 reg |= (op->addr.nbytes - 1); in cqspi_read_setup()
700 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_read_execute()
701 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_read_execute()
702 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute()
703 void __iomem *ahb_base = cqspi->ahb_base; in cqspi_indirect_read_execute()
724 if (!cqspi->slow_sram) in cqspi_indirect_read_execute()
729 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
734 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_read_execute()
736 ret = -ETIMEDOUT; in cqspi_indirect_read_execute()
742 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
755 bytes_to_read *= cqspi->fifo_width; in cqspi_indirect_read_execute()
768 (rxbuf_end - rxbuf), in cqspi_indirect_read_execute()
772 remaining -= bytes_to_read; in cqspi_indirect_read_execute()
777 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
778 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
811 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable()
828 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_versal_indirect_read_dma()
829 struct device *dev = &cqspi->pdev->dev; in cqspi_versal_indirect_read_dma()
830 void __iomem *reg_base = cqspi->iobase; in cqspi_versal_indirect_read_dma()
839 bytes_to_dma = (n_rx - bytes_rem); in cqspi_versal_indirect_read_dma()
844 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); in cqspi_versal_indirect_read_dma()
850 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
852 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
859 return -ENOMEM; in cqspi_versal_indirect_read_dma()
884 writel(cqspi->trigger_address, reg_base + in cqspi_versal_indirect_read_dma()
897 reinit_completion(&cqspi->transfer_complete); in cqspi_versal_indirect_read_dma()
899 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_versal_indirect_read_dma()
901 ret = -ETIMEDOUT; in cqspi_versal_indirect_read_dma()
906 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); in cqspi_versal_indirect_read_dma()
910 cqspi->iobase + CQSPI_REG_INDIRECTRD); in cqspi_versal_indirect_read_dma()
915 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
917 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
921 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, in cqspi_versal_indirect_read_dma()
948 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
950 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
952 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); in cqspi_versal_indirect_read_dma()
962 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write_setup()
963 void __iomem *reg_base = cqspi->iobase; in cqspi_write_setup()
970 if (op->cmd.dtr) in cqspi_write_setup()
971 opcode = op->cmd.opcode >> 8; in cqspi_write_setup()
973 opcode = op->cmd.opcode; in cqspi_write_setup()
977 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; in cqspi_write_setup()
978 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; in cqspi_write_setup()
986 * cypress Semper flash expect a 4-byte dummy address in the Read SR in cqspi_write_setup()
990 * command when doing auto-HW polling. So, disable write completion in cqspi_write_setup()
991 * polling on the controller's side. spinand and spi-nor will take in cqspi_write_setup()
994 if (cqspi->wr_completion) { in cqspi_write_setup()
1003 cqspi->use_direct_mode_wr = false; in cqspi_write_setup()
1008 reg |= (op->addr.nbytes - 1); in cqspi_write_setup()
1017 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_write_execute()
1018 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_write_execute()
1019 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_write_execute()
1032 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1042 if (cqspi->wr_delay) in cqspi_indirect_write_execute()
1043 ndelay(cqspi->wr_delay); in cqspi_indirect_write_execute()
1049 if (cqspi->apb_ahb_hazard) in cqspi_indirect_write_execute()
1060 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); in cqspi_indirect_write_execute()
1067 iowrite32(temp, cqspi->ahb_base); in cqspi_indirect_write_execute()
1071 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_write_execute()
1074 ret = -ETIMEDOUT; in cqspi_indirect_write_execute()
1078 remaining -= write_bytes; in cqspi_indirect_write_execute()
1081 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1114 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_chipselect()
1115 void __iomem *reg_base = cqspi->iobase; in cqspi_chipselect()
1116 unsigned int chip_select = f_pdata->cs; in cqspi_chipselect()
1120 if (cqspi->is_decoded_cs) { in cqspi_chipselect()
1154 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_delay()
1155 void __iomem *iobase = cqspi->iobase; in cqspi_delay()
1156 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_delay()
1162 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); in cqspi_delay()
1164 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); in cqspi_delay()
1169 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); in cqspi_delay()
1170 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); in cqspi_delay()
1171 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); in cqspi_delay()
1186 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_config_baudrate_div()
1187 void __iomem *reg_base = cqspi->iobase; in cqspi_config_baudrate_div()
1191 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; in cqspi_config_baudrate_div()
1196 dev_warn(&cqspi->pdev->dev, in cqspi_config_baudrate_div()
1198 cqspi->sclk, ref_clk_hz/((div+1)*2)); in cqspi_config_baudrate_div()
1211 void __iomem *reg_base = cqspi->iobase; in cqspi_readdata_capture()
1233 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_configure()
1234 int switch_cs = (cqspi->current_cs != f_pdata->cs); in cqspi_configure()
1235 int switch_ck = (cqspi->sclk != sclk); in cqspi_configure()
1242 cqspi->current_cs = f_pdata->cs; in cqspi_configure()
1248 cqspi->sclk = sclk; in cqspi_configure()
1251 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, in cqspi_configure()
1252 f_pdata->read_delay); in cqspi_configure()
1262 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write()
1263 loff_t to = op->addr.val; in cqspi_write()
1264 size_t len = op->data.nbytes; in cqspi_write()
1265 const u_char *buf = op->data.buf.out; in cqspi_write()
1273 * Some flashes like the Cypress Semper flash expect a dummy 4-byte in cqspi_write()
1280 if (!op->cmd.dtr && cqspi->use_direct_mode && in cqspi_write()
1281 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { in cqspi_write()
1282 memcpy_toio(cqspi->ahb_base + to, buf, len); in cqspi_write()
1293 complete(&cqspi->rx_dma_complete); in cqspi_rx_dma_callback()
1299 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_direct_read_execute()
1300 struct device *dev = &cqspi->pdev->dev; in cqspi_direct_read_execute()
1302 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; in cqspi_direct_read_execute()
1309 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { in cqspi_direct_read_execute()
1310 memcpy_fromio(buf, cqspi->ahb_base + from, len); in cqspi_direct_read_execute()
1314 ddev = cqspi->rx_chan->device->dev; in cqspi_direct_read_execute()
1318 return -ENOMEM; in cqspi_direct_read_execute()
1320 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, in cqspi_direct_read_execute()
1324 ret = -EIO; in cqspi_direct_read_execute()
1328 tx->callback = cqspi_rx_dma_callback; in cqspi_direct_read_execute()
1329 tx->callback_param = cqspi; in cqspi_direct_read_execute()
1330 cookie = tx->tx_submit(tx); in cqspi_direct_read_execute()
1331 reinit_completion(&cqspi->rx_dma_complete); in cqspi_direct_read_execute()
1336 ret = -EIO; in cqspi_direct_read_execute()
1340 dma_async_issue_pending(cqspi->rx_chan); in cqspi_direct_read_execute()
1341 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, in cqspi_direct_read_execute()
1343 dmaengine_terminate_sync(cqspi->rx_chan); in cqspi_direct_read_execute()
1345 ret = -ETIMEDOUT; in cqspi_direct_read_execute()
1358 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read()
1359 struct device *dev = &cqspi->pdev->dev; in cqspi_read()
1361 loff_t from = op->addr.val; in cqspi_read()
1362 size_t len = op->data.nbytes; in cqspi_read()
1363 u_char *buf = op->data.buf.in; in cqspi_read()
1373 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) in cqspi_read()
1376 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && in cqspi_read()
1378 return ddata->indirect_read_dma(f_pdata, buf, from, len); in cqspi_read()
1385 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_mem_process()
1388 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; in cqspi_mem_process()
1389 cqspi_configure(f_pdata, mem->spi->max_speed_hz); in cqspi_mem_process()
1391 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { in cqspi_mem_process()
1397 if (!op->addr.nbytes || in cqspi_mem_process()
1398 op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) in cqspi_mem_process()
1404 if (!op->addr.nbytes || !op->data.buf.out) in cqspi_mem_process()
1413 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); in cqspi_exec_mem_op()
1414 struct device *dev = &cqspi->pdev->dev; in cqspi_exec_mem_op()
1418 dev_err(&mem->spi->dev, "resume failed with %d\n", ret); in cqspi_exec_mem_op()
1428 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); in cqspi_exec_mem_op()
1439 * op->dummy.dtr is required for converting nbytes into ncycles. in cqspi_supports_mem_op()
1442 all_true = op->cmd.dtr && in cqspi_supports_mem_op()
1443 (!op->addr.nbytes || op->addr.dtr) && in cqspi_supports_mem_op()
1444 (!op->dummy.nbytes || op->dummy.dtr) && in cqspi_supports_mem_op()
1445 (!op->data.nbytes || op->data.dtr); in cqspi_supports_mem_op()
1447 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && in cqspi_supports_mem_op()
1448 !op->data.dtr; in cqspi_supports_mem_op()
1451 /* Right now we only support 8-8-8 DTR mode. */ in cqspi_supports_mem_op()
1452 if (op->cmd.nbytes && op->cmd.buswidth != 8) in cqspi_supports_mem_op()
1454 if (op->addr.nbytes && op->addr.buswidth != 8) in cqspi_supports_mem_op()
1456 if (op->data.nbytes && op->data.buswidth != 8) in cqspi_supports_mem_op()
1470 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { in cqspi_of_get_flash_pdata()
1471 dev_err(&pdev->dev, "couldn't determine read-delay\n"); in cqspi_of_get_flash_pdata()
1472 return -ENXIO; in cqspi_of_get_flash_pdata()
1475 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { in cqspi_of_get_flash_pdata()
1476 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); in cqspi_of_get_flash_pdata()
1477 return -ENXIO; in cqspi_of_get_flash_pdata()
1480 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { in cqspi_of_get_flash_pdata()
1481 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); in cqspi_of_get_flash_pdata()
1482 return -ENXIO; in cqspi_of_get_flash_pdata()
1485 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { in cqspi_of_get_flash_pdata()
1486 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); in cqspi_of_get_flash_pdata()
1487 return -ENXIO; in cqspi_of_get_flash_pdata()
1490 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { in cqspi_of_get_flash_pdata()
1491 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); in cqspi_of_get_flash_pdata()
1492 return -ENXIO; in cqspi_of_get_flash_pdata()
1495 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { in cqspi_of_get_flash_pdata()
1496 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); in cqspi_of_get_flash_pdata()
1497 return -ENXIO; in cqspi_of_get_flash_pdata()
1505 struct device *dev = &cqspi->pdev->dev; in cqspi_of_get_pdata()
1506 struct device_node *np = dev->of_node; in cqspi_of_get_pdata()
1509 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); in cqspi_of_get_pdata()
1511 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { in cqspi_of_get_pdata()
1512 dev_err(dev, "couldn't determine fifo-depth\n"); in cqspi_of_get_pdata()
1513 return -ENXIO; in cqspi_of_get_pdata()
1516 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { in cqspi_of_get_pdata()
1517 dev_err(dev, "couldn't determine fifo-width\n"); in cqspi_of_get_pdata()
1518 return -ENXIO; in cqspi_of_get_pdata()
1521 if (of_property_read_u32(np, "cdns,trigger-address", in cqspi_of_get_pdata()
1522 &cqspi->trigger_address)) { in cqspi_of_get_pdata()
1523 dev_err(dev, "couldn't determine trigger-address\n"); in cqspi_of_get_pdata()
1524 return -ENXIO; in cqspi_of_get_pdata()
1527 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) in cqspi_of_get_pdata()
1528 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; in cqspi_of_get_pdata()
1530 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); in cqspi_of_get_pdata()
1532 if (!of_property_read_u32_array(np, "power-domains", id, in cqspi_of_get_pdata()
1534 cqspi->pd_dev_id = id[1]; in cqspi_of_get_pdata()
1546 writel(0, cqspi->iobase + CQSPI_REG_REMAP); in cqspi_controller_init()
1549 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); in cqspi_controller_init()
1552 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_init()
1555 writel(cqspi->trigger_address, in cqspi_controller_init()
1556 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); in cqspi_controller_init()
1558 /* Program read watermark -- 1/2 of the FIFO. */ in cqspi_controller_init()
1559 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, in cqspi_controller_init()
1560 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); in cqspi_controller_init()
1561 /* Program write watermark -- 1/8 of the FIFO. */ in cqspi_controller_init()
1562 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, in cqspi_controller_init()
1563 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); in cqspi_controller_init()
1566 if (!cqspi->use_direct_mode) { in cqspi_controller_init()
1567 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1569 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1573 if (cqspi->use_dma_read) { in cqspi_controller_init()
1574 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1576 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1589 cqspi->rx_chan = dma_request_chan_by_mask(&mask); in cqspi_request_mmap_dma()
1590 if (IS_ERR(cqspi->rx_chan)) { in cqspi_request_mmap_dma()
1591 int ret = PTR_ERR(cqspi->rx_chan); in cqspi_request_mmap_dma()
1593 cqspi->rx_chan = NULL; in cqspi_request_mmap_dma()
1594 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); in cqspi_request_mmap_dma()
1596 init_completion(&cqspi->rx_dma_complete); in cqspi_request_mmap_dma()
1603 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_get_name()
1604 struct device *dev = &cqspi->pdev->dev; in cqspi_get_name()
1607 spi_get_chipselect(mem->spi, 0)); in cqspi_get_name()
1622 struct platform_device *pdev = cqspi->pdev; in cqspi_setup_flash()
1623 struct device *dev = &pdev->dev; in cqspi_setup_flash()
1624 struct device_node *np = dev->of_node; in cqspi_setup_flash()
1630 for_each_available_child_of_node(dev->of_node, np) { in cqspi_setup_flash()
1641 return -EINVAL; in cqspi_setup_flash()
1644 f_pdata = &cqspi->f_pdata[cs]; in cqspi_setup_flash()
1645 f_pdata->cqspi = cqspi; in cqspi_setup_flash()
1646 f_pdata->cs = cs; in cqspi_setup_flash()
1667 ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); in cqspi_jh7110_clk_init()
1669 dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); in cqspi_jh7110_clk_init()
1673 cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk; in cqspi_jh7110_clk_init()
1674 cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk; in cqspi_jh7110_clk_init()
1676 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_clk_init()
1678 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); in cqspi_jh7110_clk_init()
1682 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); in cqspi_jh7110_clk_init()
1684 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); in cqspi_jh7110_clk_init()
1688 cqspi->is_jh7110 = true; in cqspi_jh7110_clk_init()
1693 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_clk_init()
1700 clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); in cqspi_jh7110_disable_clk()
1701 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_disable_clk()
1707 struct device *dev = &pdev->dev; in cqspi_probe()
1714 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); in cqspi_probe()
1716 dev_err(&pdev->dev, "devm_spi_alloc_host failed\n"); in cqspi_probe()
1717 return -ENOMEM; in cqspi_probe()
1719 host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; in cqspi_probe()
1720 host->mem_ops = &cqspi_mem_ops; in cqspi_probe()
1721 host->mem_caps = &cqspi_mem_caps; in cqspi_probe()
1722 host->dev.of_node = pdev->dev.of_node; in cqspi_probe()
1726 cqspi->pdev = pdev; in cqspi_probe()
1727 cqspi->host = host; in cqspi_probe()
1728 cqspi->is_jh7110 = false; in cqspi_probe()
1735 return -ENODEV; in cqspi_probe()
1739 cqspi->clk = devm_clk_get(dev, NULL); in cqspi_probe()
1740 if (IS_ERR(cqspi->clk)) { in cqspi_probe()
1742 ret = PTR_ERR(cqspi->clk); in cqspi_probe()
1747 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); in cqspi_probe()
1748 if (IS_ERR(cqspi->iobase)) { in cqspi_probe()
1750 ret = PTR_ERR(cqspi->iobase); in cqspi_probe()
1755 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); in cqspi_probe()
1756 if (IS_ERR(cqspi->ahb_base)) { in cqspi_probe()
1758 ret = PTR_ERR(cqspi->ahb_base); in cqspi_probe()
1761 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; in cqspi_probe()
1762 cqspi->ahb_size = resource_size(res_ahb); in cqspi_probe()
1764 init_completion(&cqspi->transfer_complete); in cqspi_probe()
1769 return -ENXIO; in cqspi_probe()
1776 ret = clk_prepare_enable(cqspi->clk); in cqspi_probe()
1790 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); in cqspi_probe()
1797 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { in cqspi_probe()
1814 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); in cqspi_probe()
1815 host->max_speed_hz = cqspi->master_ref_clk_hz; in cqspi_probe()
1818 cqspi->wr_completion = true; in cqspi_probe()
1822 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) in cqspi_probe()
1823 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, in cqspi_probe()
1824 cqspi->master_ref_clk_hz); in cqspi_probe()
1825 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) in cqspi_probe()
1826 host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; in cqspi_probe()
1827 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { in cqspi_probe()
1828 cqspi->use_direct_mode = true; in cqspi_probe()
1829 cqspi->use_direct_mode_wr = true; in cqspi_probe()
1831 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) in cqspi_probe()
1832 cqspi->use_dma_read = true; in cqspi_probe()
1833 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) in cqspi_probe()
1834 cqspi->wr_completion = false; in cqspi_probe()
1835 if (ddata->quirks & CQSPI_SLOW_SRAM) in cqspi_probe()
1836 cqspi->slow_sram = true; in cqspi_probe()
1837 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) in cqspi_probe()
1838 cqspi->apb_ahb_hazard = true; in cqspi_probe()
1840 if (ddata->jh7110_clk_init) { in cqspi_probe()
1846 if (of_device_is_compatible(pdev->dev.of_node, in cqspi_probe()
1847 "xlnx,versal-ospi-1.0")) { in cqspi_probe()
1848 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); in cqspi_probe()
1855 pdev->name, cqspi); in cqspi_probe()
1863 cqspi->current_cs = -1; in cqspi_probe()
1864 cqspi->sclk = 0; in cqspi_probe()
1866 host->num_chipselect = cqspi->num_chipselect; in cqspi_probe()
1874 if (cqspi->use_direct_mode) { in cqspi_probe()
1876 if (ret == -EPROBE_DEFER) in cqspi_probe()
1882 if (cqspi->rx_chan) in cqspi_probe()
1883 dma_release_channel(cqspi->rx_chan); in cqspi_probe()
1893 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); in cqspi_probe()
1904 if (cqspi->is_jh7110) in cqspi_probe()
1906 clk_disable_unprepare(cqspi->clk); in cqspi_probe()
1915 spi_unregister_controller(cqspi->host); in cqspi_remove()
1918 if (cqspi->rx_chan) in cqspi_remove()
1919 dma_release_channel(cqspi->rx_chan); in cqspi_remove()
1921 clk_disable_unprepare(cqspi->clk); in cqspi_remove()
1923 if (cqspi->is_jh7110) in cqspi_remove()
1926 pm_runtime_put_sync(&pdev->dev); in cqspi_remove()
1927 pm_runtime_disable(&pdev->dev); in cqspi_remove()
1935 clk_disable_unprepare(cqspi->clk); in cqspi_runtime_suspend()
1943 clk_prepare_enable(cqspi->clk); in cqspi_runtime_resume()
1947 cqspi->current_cs = -1; in cqspi_runtime_resume()
1948 cqspi->sclk = 0; in cqspi_runtime_resume()
1956 return spi_controller_suspend(cqspi->host); in cqspi_suspend()
1963 return spi_controller_resume(cqspi->host); in cqspi_resume()
2012 .compatible = "cdns,qspi-nor",
2016 .compatible = "ti,k2g-qspi",
2020 .compatible = "ti,am654-ospi",
2024 .compatible = "intel,lgm-qspi",
2028 .compatible = "xlnx,versal-ospi-1.0",
2032 .compatible = "intel,socfpga-qspi",
2036 .compatible = "starfive,jh7110-qspi",
2040 .compatible = "amd,pensando-elba-qspi",