Lines Matching full:ctrl
209 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
210 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
281 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_ahb_reg_read() argument
284 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_read()
301 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_ahb_reg_write() argument
304 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_write()
321 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_cpu_reg_read() argument
324 *val = readl(ctrl->mmio + reg); in qcom_swrm_cpu_reg_read()
328 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_cpu_reg_write() argument
331 writel(val, ctrl->mmio + reg); in qcom_swrm_cpu_reg_write()
353 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_rd_fifo_avail() argument
360 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_rd_fifo_avail()
372 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); in swrm_wait_for_rd_fifo_avail()
379 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_wr_fifo_avail() argument
386 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_wr_fifo_avail()
391 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) in swrm_wait_for_wr_fifo_avail()
397 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { in swrm_wait_for_wr_fifo_avail()
398 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); in swrm_wait_for_wr_fifo_avail()
405 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_wr_fifo_done() argument
411 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
417 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
431 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, in qcom_swrm_cmd_fifo_wr_cmd() argument
444 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, in qcom_swrm_cmd_fifo_wr_cmd()
448 if (swrm_wait_for_wr_fifo_avail(ctrl)) in qcom_swrm_cmd_fifo_wr_cmd()
452 reinit_completion(&ctrl->broadcast); in qcom_swrm_cmd_fifo_wr_cmd()
455 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); in qcom_swrm_cmd_fifo_wr_cmd()
457 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_cmd_fifo_wr_cmd()
461 swrm_wait_for_wr_fifo_done(ctrl); in qcom_swrm_cmd_fifo_wr_cmd()
466 ret = wait_for_completion_timeout(&ctrl->broadcast, in qcom_swrm_cmd_fifo_wr_cmd()
479 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_cmd_fifo_rd_cmd() argument
485 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr); in qcom_swrm_cmd_fifo_rd_cmd()
491 swrm_wait_for_wr_fifo_avail(ctrl); in qcom_swrm_cmd_fifo_rd_cmd()
495 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); in qcom_swrm_cmd_fifo_rd_cmd()
499 if (swrm_wait_for_rd_fifo_avail(ctrl)) in qcom_swrm_cmd_fifo_rd_cmd()
503 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], in qcom_swrm_cmd_fifo_rd_cmd()
508 if (cmd_id != ctrl->rcmd_id) { in qcom_swrm_cmd_fifo_rd_cmd()
512 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, in qcom_swrm_cmd_fifo_rd_cmd()
514 ctrl->reg_write(ctrl, in qcom_swrm_cmd_fifo_rd_cmd()
515 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], in qcom_swrm_cmd_fifo_rd_cmd()
525 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ in qcom_swrm_cmd_fifo_rd_cmd()
527 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
532 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_get_alert_slave_dev_num() argument
537 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_alert_slave_dev_num()
543 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; in qcom_swrm_get_alert_slave_dev_num()
551 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_get_device_status() argument
556 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_device_status()
557 ctrl->slave_status = val; in qcom_swrm_get_device_status()
564 ctrl->status[i] = s; in qcom_swrm_get_device_status()
571 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_set_slave_dev_num() local
574 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); in qcom_swrm_set_slave_dev_num()
589 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_enumerate() local
600 if (!ctrl->status[i]) in qcom_swrm_enumerate()
604 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); in qcom_swrm_enumerate()
607 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); in qcom_swrm_enumerate()
618 ctrl->clock_stop_not_supported = false; in qcom_swrm_enumerate()
624 ctrl->clock_stop_not_supported = true; in qcom_swrm_enumerate()
637 complete(&ctrl->enumeration); in qcom_swrm_enumerate()
643 struct qcom_swrm_ctrl *ctrl = dev_id; in qcom_swrm_wake_irq_handler() local
646 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_wake_irq_handler()
648 dev_err_ratelimited(ctrl->dev, in qcom_swrm_wake_irq_handler()
651 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_wake_irq_handler()
655 if (ctrl->wake_irq > 0) { in qcom_swrm_wake_irq_handler()
656 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) in qcom_swrm_wake_irq_handler()
657 disable_irq_nosync(ctrl->wake_irq); in qcom_swrm_wake_irq_handler()
660 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_wake_irq_handler()
661 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_wake_irq_handler()
668 struct qcom_swrm_ctrl *ctrl = dev_id; in qcom_swrm_irq_handler() local
673 clk_prepare_enable(ctrl->hclk); in qcom_swrm_irq_handler()
675 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
677 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
687 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); in qcom_swrm_irq_handler()
689 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
692 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
698 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); in qcom_swrm_irq_handler()
699 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); in qcom_swrm_irq_handler()
700 if (ctrl->slave_status == slave_status) { in qcom_swrm_irq_handler()
701 dev_dbg(ctrl->dev, "Slave status not changed %x\n", in qcom_swrm_irq_handler()
704 qcom_swrm_get_device_status(ctrl); in qcom_swrm_irq_handler()
705 qcom_swrm_enumerate(&ctrl->bus); in qcom_swrm_irq_handler()
706 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
710 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
713 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; in qcom_swrm_irq_handler()
714 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
715 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
716 ctrl->intr_mask); in qcom_swrm_irq_handler()
719 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
720 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
722 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
727 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
728 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
730 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
735 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
736 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
738 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
741 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
744 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
745 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
747 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
750 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
753 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
756 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; in qcom_swrm_irq_handler()
757 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
758 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
759 ctrl->intr_mask); in qcom_swrm_irq_handler()
762 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
765 ctrl->intr_mask &= in qcom_swrm_irq_handler()
767 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
768 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
769 ctrl->intr_mask); in qcom_swrm_irq_handler()
772 complete(&ctrl->broadcast); in qcom_swrm_irq_handler()
781 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
782 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
784 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
792 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
799 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_irq_handler()
801 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
803 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
806 clk_disable_unprepare(ctrl->hclk); in qcom_swrm_irq_handler()
810 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_frame_gen_enabled() argument
816 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED], in swrm_wait_for_frame_gen_enabled()
824 dev_err(ctrl->dev, "%s: link status not %s\n", __func__, in swrm_wait_for_frame_gen_enabled()
830 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_init() argument
835 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); in qcom_swrm_init()
836 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); in qcom_swrm_init()
838 reset_control_reset(ctrl->audio_cgcr); in qcom_swrm_init()
840 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); in qcom_swrm_init()
843 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); in qcom_swrm_init()
845 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; in qcom_swrm_init()
847 if (ctrl->version < SWRM_VERSION_2_0_0) in qcom_swrm_init()
848 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], in qcom_swrm_init()
852 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); in qcom_swrm_init()
854 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); in qcom_swrm_init()
856 if (ctrl->version == SWRM_VERSION_1_7_0) { in qcom_swrm_init()
857 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
858 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, in qcom_swrm_init()
860 } else if (ctrl->version >= SWRM_VERSION_2_0_0) { in qcom_swrm_init()
861 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
862 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, in qcom_swrm_init()
865 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); in qcom_swrm_init()
869 if (ctrl->version >= SWRM_VERSION_1_5_1) { in qcom_swrm_init()
870 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
874 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
879 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); in qcom_swrm_init()
882 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
885 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_init()
889 if (ctrl->mmio) { in qcom_swrm_init()
890 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_init()
895 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
899 swrm_wait_for_frame_gen_enabled(ctrl); in qcom_swrm_init()
900 ctrl->slave_status = 0; in qcom_swrm_init()
901 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_init()
902 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); in qcom_swrm_init()
903 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); in qcom_swrm_init()
911 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_xfer_msg() local
921 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, in qcom_swrm_xfer_msg()
931 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], in qcom_swrm_xfer_msg()
945 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_pre_bank_switch() local
948 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_pre_bank_switch()
950 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
951 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
953 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_pre_bank_switch()
960 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_port_params() local
962 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), in qcom_swrm_port_params()
971 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_transport_params() local
977 pcfg = &ctrl->pconfig[params->port_num]; in qcom_swrm_transport_params()
983 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
990 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
998 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1006 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1015 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1019 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1027 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); in qcom_swrm_transport_params()
1039 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_port_enable() local
1042 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_port_enable()
1049 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_port_enable()
1065 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_compute_params() local
1076 pcfg = &ctrl->pconfig[p_rt->num]; in qcom_swrm_compute_params()
1093 pcfg = &ctrl->pconfig[m_port]; in qcom_swrm_compute_params()
1095 pcfg = &ctrl->pconfig[i]; in qcom_swrm_compute_params()
1126 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_stream_free_ports() argument
1133 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1137 port_mask = &ctrl->dout_port_mask; in qcom_swrm_stream_free_ports()
1139 port_mask = &ctrl->din_port_mask; in qcom_swrm_stream_free_ports()
1145 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1148 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_stream_alloc_ports() argument
1174 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1177 maxport = ctrl->num_dout_ports; in qcom_swrm_stream_alloc_ports()
1178 port_mask = &ctrl->dout_port_mask; in qcom_swrm_stream_alloc_ports()
1180 maxport = ctrl->num_din_ports; in qcom_swrm_stream_alloc_ports()
1181 port_mask = &ctrl->din_port_mask; in qcom_swrm_stream_alloc_ports()
1195 dev_err(ctrl->dev, "All ports busy\n"); in qcom_swrm_stream_alloc_ports()
1207 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, in qcom_swrm_stream_alloc_ports()
1210 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1219 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_params() local
1220 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_params()
1223 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, in qcom_swrm_hw_params()
1226 qcom_swrm_stream_free_ports(ctrl, sruntime); in qcom_swrm_hw_params()
1234 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_free() local
1235 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_free()
1237 qcom_swrm_stream_free_ports(ctrl, sruntime); in qcom_swrm_hw_free()
1238 sdw_stream_remove_master(&ctrl->bus, sruntime); in qcom_swrm_hw_free()
1246 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_set_sdw_stream() local
1248 ctrl->sruntime[dai->id] = stream; in qcom_swrm_set_sdw_stream()
1255 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_get_sdw_stream() local
1257 return ctrl->sruntime[dai->id]; in qcom_swrm_get_sdw_stream()
1263 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_startup() local
1266 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_startup()
1268 dev_err_ratelimited(ctrl->dev, in qcom_swrm_startup()
1271 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_startup()
1281 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_shutdown() local
1283 swrm_wait_for_wr_fifo_done(ctrl); in qcom_swrm_shutdown()
1284 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_shutdown()
1285 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_shutdown()
1302 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_register_dais() argument
1304 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_register_dais()
1307 struct device *dev = ctrl->dev; in qcom_swrm_register_dais()
1320 if (i < ctrl->num_dout_ports) in qcom_swrm_register_dais()
1334 return devm_snd_soc_register_component(ctrl->dev, in qcom_swrm_register_dais()
1339 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_get_port_config() argument
1341 struct device_node *np = ctrl->dev->of_node; in qcom_swrm_get_port_config()
1354 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_get_port_config()
1356 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); in qcom_swrm_get_port_config()
1357 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); in qcom_swrm_get_port_config()
1363 if (val > ctrl->num_din_ports) in qcom_swrm_get_port_config()
1366 ctrl->num_din_ports = val; in qcom_swrm_get_port_config()
1372 if (val > ctrl->num_dout_ports) in qcom_swrm_get_port_config()
1375 ctrl->num_dout_ports = val; in qcom_swrm_get_port_config()
1377 nports = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_get_port_config()
1382 set_bit(0, &ctrl->dout_port_mask); in qcom_swrm_get_port_config()
1383 set_bit(0, &ctrl->din_port_mask); in qcom_swrm_get_port_config()
1408 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_get_port_config()
1432 ctrl->pconfig[i + 1].si = si[i]; in qcom_swrm_get_port_config()
1434 ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; in qcom_swrm_get_port_config()
1435 ctrl->pconfig[i + 1].off1 = off1[i]; in qcom_swrm_get_port_config()
1436 ctrl->pconfig[i + 1].off2 = off2[i]; in qcom_swrm_get_port_config()
1437 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; in qcom_swrm_get_port_config()
1438 ctrl->pconfig[i + 1].hstart = hstart[i]; in qcom_swrm_get_port_config()
1439 ctrl->pconfig[i + 1].hstop = hstop[i]; in qcom_swrm_get_port_config()
1440 ctrl->pconfig[i + 1].word_length = word_length[i]; in qcom_swrm_get_port_config()
1441 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; in qcom_swrm_get_port_config()
1442 ctrl->pconfig[i + 1].lane_control = lane_control[i]; in qcom_swrm_get_port_config()
1451 struct qcom_swrm_ctrl *ctrl = s_file->private; in swrm_reg_show() local
1454 ret = pm_runtime_get_sync(ctrl->dev); in swrm_reg_show()
1456 dev_err_ratelimited(ctrl->dev, in swrm_reg_show()
1459 pm_runtime_put_noidle(ctrl->dev); in swrm_reg_show()
1463 for (reg = 0; reg <= ctrl->max_reg; reg += 4) { in swrm_reg_show()
1464 ctrl->reg_read(ctrl, reg, ®_val); in swrm_reg_show()
1467 pm_runtime_mark_last_busy(ctrl->dev); in swrm_reg_show()
1468 pm_runtime_put_autosuspend(ctrl->dev); in swrm_reg_show()
1481 struct qcom_swrm_ctrl *ctrl; local
1486 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1487 if (!ctrl)
1491 ctrl->max_reg = data->max_reg;
1492 ctrl->reg_layout = data->reg_layout;
1493 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1494 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1500 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1501 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1502 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1503 if (!ctrl->regmap)
1506 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1507 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1508 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1509 if (IS_ERR(ctrl->mmio))
1510 return PTR_ERR(ctrl->mmio);
1514 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1515 if (IS_ERR(ctrl->audio_cgcr)) {
1516 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1517 ret = PTR_ERR(ctrl->audio_cgcr);
1522 ctrl->irq = of_irq_get(dev->of_node, 0);
1523 if (ctrl->irq < 0) {
1524 ret = ctrl->irq;
1528 ctrl->hclk = devm_clk_get(dev, "iface");
1529 if (IS_ERR(ctrl->hclk)) {
1530 ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1534 clk_prepare_enable(ctrl->hclk);
1536 ctrl->dev = dev;
1537 dev_set_drvdata(&pdev->dev, ctrl);
1538 mutex_init(&ctrl->port_lock);
1539 init_completion(&ctrl->broadcast);
1540 init_completion(&ctrl->enumeration);
1542 ctrl->bus.ops = &qcom_swrm_ops;
1543 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1544 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1545 ctrl->bus.clk_stop_timeout = 300;
1547 ret = qcom_swrm_get_port_config(ctrl);
1551 params = &ctrl->bus.params;
1556 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1560 prop = &ctrl->bus.prop;
1568 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1570 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1574 "soundwire", ctrl);
1580 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1581 if (ctrl->wake_irq > 0) {
1582 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1585 "swr_wake_irq", ctrl);
1592 ctrl->bus.controller_id = -1;
1594 if (ctrl->version > SWRM_VERSION_1_3_0) {
1595 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1596 ctrl->bus.controller_id = val;
1599 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1606 qcom_swrm_init(ctrl);
1607 wait_for_completion_timeout(&ctrl->enumeration,
1609 ret = qcom_swrm_register_dais(ctrl);
1614 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1615 ctrl->version & 0xffff);
1624 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1625 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1632 sdw_bus_master_delete(&ctrl->bus);
1634 clk_disable_unprepare(ctrl->hclk);
1641 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); local
1643 sdw_bus_master_delete(&ctrl->bus);
1644 clk_disable_unprepare(ctrl->hclk);
1651 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); local
1654 if (ctrl->wake_irq > 0) {
1655 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1656 disable_irq_nosync(ctrl->wake_irq);
1659 clk_prepare_enable(ctrl->hclk);
1661 if (ctrl->clock_stop_not_supported) {
1662 reinit_completion(&ctrl->enumeration);
1663 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1666 qcom_swrm_init(ctrl);
1669 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1670 dev_err(ctrl->dev, "link failed to connect\n");
1673 wait_for_completion_timeout(&ctrl->enumeration,
1675 qcom_swrm_get_device_status(ctrl);
1676 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1678 reset_control_reset(ctrl->audio_cgcr);
1680 if (ctrl->version == SWRM_VERSION_1_7_0) {
1681 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1682 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1684 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1685 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1686 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1689 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1691 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1694 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1695 if (ctrl->version < SWRM_VERSION_2_0_0)
1696 ctrl->reg_write(ctrl,
1697 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1698 ctrl->intr_mask);
1699 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1700 ctrl->intr_mask);
1703 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1704 dev_err(ctrl->dev, "link failed to connect\n");
1706 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1708 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1716 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); local
1719 swrm_wait_for_wr_fifo_done(ctrl);
1720 if (!ctrl->clock_stop_not_supported) {
1722 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1723 if (ctrl->version < SWRM_VERSION_2_0_0)
1724 ctrl->reg_write(ctrl,
1725 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1726 ctrl->intr_mask);
1727 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1728 ctrl->intr_mask);
1730 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1736 ret = sdw_bus_clk_stop(&ctrl->bus);
1743 clk_disable_unprepare(ctrl->hclk);
1747 if (ctrl->wake_irq > 0) {
1748 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1749 enable_irq(ctrl->wake_irq);