Lines Matching +full:0 +full:x1740
25 #define SWRM_COMP_SW_RESET 0x008
26 #define SWRM_COMP_STATUS 0x014
27 #define SWRM_LINK_MANAGER_EE 0x018
29 #define SWRM_FRM_GEN_ENABLED BIT(0)
30 #define SWRM_VERSION_1_3_0 0x01030000
31 #define SWRM_VERSION_1_5_1 0x01050001
32 #define SWRM_VERSION_1_7_0 0x01070000
33 #define SWRM_VERSION_2_0_0 0x02000000
34 #define SWRM_COMP_HW_VERSION 0x00
35 #define SWRM_COMP_CFG_ADDR 0x04
37 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
38 #define SWRM_COMP_PARAMS 0x100
41 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
43 #define SWRM_COMP_MASTER_ID 0x104
44 #define SWRM_V1_3_INTERRUPT_STATUS 0x200
45 #define SWRM_V2_0_INTERRUPT_STATUS 0x5000
46 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
47 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
65 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204
66 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208
67 #define SWRM_V2_0_INTERRUPT_CLEAR 0x5008
68 #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210
69 #define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004
70 #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300
71 #define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020
72 #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304
73 #define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024
74 #define SWRM_CMD_FIFO_CMD 0x308
75 #define SWRM_CMD_FIFO_FLUSH 0x1
76 #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C
77 #define SWRM_V2_0_CMD_FIFO_STATUS 0x5050
80 #define SWRM_CMD_FIFO_CFG_ADDR 0x314
82 #define SWRM_RD_WR_CMD_RETRIES 0x7
83 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318
84 #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040
86 #define SWRM_ENUMERATOR_CFG_ADDR 0x500
87 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
88 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
89 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
90 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
92 #define SWRM_MCP_BUS_CTRL 0x1044
94 #define SWRM_MCP_CFG_ADDR 0x1048
96 #define SWRM_DEF_CMD_NO_PINGS 0x1f
97 #define SWRM_MCP_STATUS 0x104C
98 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
99 #define SWRM_MCP_SLV_STATUS 0x1090
100 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
102 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
103 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
104 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
105 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
106 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
107 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
108 #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m)
109 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
110 #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
111 #define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac
113 #define SWRM_V2_0_CLK_CTRL 0x5060
114 #define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0)
115 #define SWRM_V2_0_LINK_STATUS 0x5064
117 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
118 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
119 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
120 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
121 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
122 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
123 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
130 #define QCOM_SWRM_MAX_RD_LEN 0x1
133 #define SWRM_MAX_DAIS 0xF
134 #define SWR_INVALID_PARAM 0xFF
135 #define SWR_HSTOP_MAX_VAL 0xF
136 #define SWR_HSTART_MIN_VAL 0x0
137 #define SWR_BROADCAST_CMD_ID 0x0F
262 [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
290 if (ret < 0) in qcom_swrm_ahb_reg_read()
295 if (ret < 0) in qcom_swrm_ahb_reg_read()
345 id = 0; in swrm_get_packed_reg_val()
365 if (fifo_outstanding_data > 0) in swrm_wait_for_rd_fifo_avail()
366 return 0; in swrm_wait_for_rd_fifo_avail()
371 if (fifo_outstanding_data == 0) { in swrm_wait_for_rd_fifo_avail()
376 return 0; in swrm_wait_for_rd_fifo_avail()
392 return 0; in swrm_wait_for_wr_fifo_avail()
402 return 0; in swrm_wait_for_wr_fifo_avail()
420 if (fifo_outstanding_cmds == 0) in swrm_wait_for_wr_fifo_done()
436 int ret = 0; in qcom_swrm_cmd_fifo_wr_cmd()
437 u8 cmd_id = 0x0; in qcom_swrm_cmd_fifo_wr_cmd()
483 u32 cmd_data, cmd_id, val, retry_attempt = 0; in qcom_swrm_cmd_fifo_rd_cmd()
505 rval[0] = cmd_data & 0xFF; in qcom_swrm_cmd_fifo_rd_cmd()
525 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ in qcom_swrm_cmd_fifo_rd_cmd()
526 dev_num: 0x%x, cmd_data: 0x%x\n", in qcom_swrm_cmd_fifo_rd_cmd()
606 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ in qcom_swrm_enumerate()
612 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) | in qcom_swrm_enumerate()
614 ((u64)buf1[0] << 40); in qcom_swrm_enumerate()
621 if (sdw_compare_devid(slave, id) == 0) { in qcom_swrm_enumerate()
638 return 0; in qcom_swrm_enumerate()
647 if (ret < 0 && ret != -EACCES) { in qcom_swrm_wake_irq_handler()
655 if (ctrl->wake_irq > 0) { in qcom_swrm_wake_irq_handler()
680 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { in qcom_swrm_irq_handler()
688 if (devnum < 0) { in qcom_swrm_irq_handler()
723 "%s: SWR read FIFO overflow fifo status 0x%x\n", in qcom_swrm_irq_handler()
731 "%s: SWR read FIFO underflow fifo status 0x%x\n", in qcom_swrm_irq_handler()
741 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
748 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", in qcom_swrm_irq_handler()
750 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
840 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); in qcom_swrm_init()
886 0xFFFFFFFF); in qcom_swrm_init()
900 ctrl->slave_status = 0; in qcom_swrm_init()
905 return 0; in qcom_swrm_init()
915 for (i = 0; i < msg->len;) { in qcom_swrm_xfer_msg()
930 for (i = 0; i < msg->len; i++) { in qcom_swrm_xfer_msg()
981 value |= pcfg->si & 0xff; in qcom_swrm_transport_params()
987 if (pcfg->si > 0xff) { in qcom_swrm_transport_params()
988 value = (pcfg->si >> 8) & 0xff; in qcom_swrm_transport_params()
1047 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); in qcom_swrm_port_enable()
1091 /* port config starts at offset 0 so -1 from actual port number */ in qcom_swrm_compute_params()
1119 return 0; in qcom_swrm_compute_params()
1160 int maxport, pn, nports = 0, ret = 0; in qcom_swrm_stream_alloc_ports()
1240 return 0; in qcom_swrm_hw_free()
1250 return 0; in qcom_swrm_set_sdw_stream()
1267 if (ret < 0 && ret != -EACCES) { in qcom_swrm_startup()
1275 return 0; in qcom_swrm_startup()
1315 for (i = 0; i < num_dais; i++) { in qcom_swrm_register_dais()
1345 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; in qcom_swrm_get_port_config()
1381 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ in qcom_swrm_get_port_config()
1382 set_bit(0, &ctrl->dout_port_mask); in qcom_swrm_get_port_config()
1383 set_bit(0, &ctrl->din_port_mask); in qcom_swrm_get_port_config()
1429 for (i = 0; i < nports; i++) { in qcom_swrm_get_port_config()
1445 return 0; in qcom_swrm_get_port_config()
1455 if (ret < 0 && ret != -EACCES) { in swrm_reg_show()
1463 for (reg = 0; reg <= ctrl->max_reg; reg += 4) { in swrm_reg_show()
1465 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); in swrm_reg_show()
1471 return 0; in swrm_reg_show()
1508 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1522 ctrl->irq = of_irq_get(dev->of_node, 0);
1523 if (ctrl->irq < 0) {
1562 prop->num_clk_gears = 0;
1564 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1581 if (ctrl->wake_irq > 0) {
1614 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1615 ctrl->version & 0xffff);
1629 return 0;
1646 return 0;
1654 if (ctrl->wake_irq > 0) {
1663 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1707 if (ret < 0)
1711 return 0;
1731 if (ret < 0 && ret != -ENODATA) {
1737 if (ret < 0 && ret != -ENODATA) {
1747 if (ctrl->wake_irq > 0) {
1752 return 0;