tegra/fuse/tegra-apbmisc.c

17 #define FUSE_SKU_INFO	0x10
19 #define ERD_ERR_CONFIG 0x120c
20 #define ERD_MASK_INBAND_ERR 0x1
24 	(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
26 	(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
42 	return (tegra_read_chipid() >> 8) & 0xff;  in tegra_get_chip_id()
47 	return (tegra_read_chipid() >> 4) & 0xf;  in tegra_get_major_rev()
52 	return (tegra_read_chipid() >> 16) & 0xf;  in tegra_get_minor_rev()
57 	return (tegra_read_chipid() >> 20) & 0xf;  in tegra_get_platform()
66 		if (tegra_get_platform() == 0)  in tegra_is_silicon()
119 	return 0;  in tegra194_miscreg_mask_serror()
181 			apbmisc.start = 0x70000800;  in tegra_init_apbmisc()
182 			apbmisc.end = 0x70000863;  in tegra_init_apbmisc()
187 				straps.start = 0x7000e864;  in tegra_init_apbmisc()
188 				straps.end = 0x7000e867;  in tegra_init_apbmisc()
190 				straps.start = 0x70000008;  in tegra_init_apbmisc()
191 				straps.end = 0x7000000b;  in tegra_init_apbmisc()
211 		if (of_address_to_resource(np, 0, &apbmisc) < 0) {  in tegra_init_apbmisc()
216 		if (of_address_to_resource(np, 1, &straps) < 0) {  in tegra_init_apbmisc()