Lines Matching +full:clock +full:- +full:source
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * QE UCC API Set - UCC specific routines implementations.
33 if (ucc_num > UCC_MAX_NUM - 1) in ucc_set_qe_mux_mii_mng()
34 return -EINVAL; in ucc_set_qe_mux_mii_mng()
37 qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, in ucc_set_qe_mux_mii_mng()
50 * 'ucc_num' is the UCC number, from 0 - 7.
62 case 0: guemr = &qe_immr->ucc1.slow.guemr; in ucc_set_type()
64 case 1: guemr = &qe_immr->ucc2.slow.guemr; in ucc_set_type()
66 case 2: guemr = &qe_immr->ucc3.slow.guemr; in ucc_set_type()
68 case 3: guemr = &qe_immr->ucc4.slow.guemr; in ucc_set_type()
70 case 4: guemr = &qe_immr->ucc5.slow.guemr; in ucc_set_type()
72 case 5: guemr = &qe_immr->ucc6.slow.guemr; in ucc_set_type()
74 case 6: guemr = &qe_immr->ucc7.slow.guemr; in ucc_set_type()
76 case 7: guemr = &qe_immr->ucc8.slow.guemr; in ucc_set_type()
79 return -EINVAL; in ucc_set_type()
94 *cmxucr = &qe_immr->qmx.cmxucr[cmx]; in get_cmxucr_reg()
95 *shift = 16 - 8 * (ucc_num & 2); in get_cmxucr_reg()
105 if (ucc_num > UCC_MAX_NUM - 1) in ucc_mux_set_grant_tsa_bkpt()
106 return -EINVAL; in ucc_mux_set_grant_tsa_bkpt()
118 int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock, in ucc_set_qe_mux_rxtx() argument
127 if (ucc_num > UCC_MAX_NUM - 1) in ucc_set_qe_mux_rxtx()
128 return -EINVAL; in ucc_set_qe_mux_rxtx()
132 return -EINVAL; in ucc_set_qe_mux_rxtx()
138 switch (clock) { in ucc_set_qe_mux_rxtx()
153 switch (clock) { in ucc_set_qe_mux_rxtx()
168 switch (clock) { in ucc_set_qe_mux_rxtx()
184 switch (clock) { in ucc_set_qe_mux_rxtx()
202 /* Check for invalid combination of clock and UCC number */ in ucc_set_qe_mux_rxtx()
204 return -ENOENT; in ucc_set_qe_mux_rxtx()
215 static int ucc_get_tdm_common_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_common_clk() argument
217 int clock_bits = -EINVAL; in ucc_get_tdm_common_clk()
221 * clock source BRG3,4 and CLK1,2 in ucc_get_tdm_common_clk()
223 * clock source BRG12,13 and CLK23,24 in ucc_get_tdm_common_clk()
230 switch (clock) { in ucc_get_tdm_common_clk()
251 switch (clock) { in ucc_get_tdm_common_clk()
275 static int ucc_get_tdm_rx_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_rx_clk() argument
277 int clock_bits = -EINVAL; in ucc_get_tdm_rx_clk()
281 switch (clock) { in ucc_get_tdm_rx_clk()
293 switch (clock) { in ucc_get_tdm_rx_clk()
305 switch (clock) { in ucc_get_tdm_rx_clk()
317 switch (clock) { in ucc_get_tdm_rx_clk()
329 switch (clock) { in ucc_get_tdm_rx_clk()
341 switch (clock) { in ucc_get_tdm_rx_clk()
353 switch (clock) { in ucc_get_tdm_rx_clk()
365 switch (clock) { in ucc_get_tdm_rx_clk()
381 static int ucc_get_tdm_tx_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_tx_clk() argument
383 int clock_bits = -EINVAL; in ucc_get_tdm_tx_clk()
387 switch (clock) { in ucc_get_tdm_tx_clk()
399 switch (clock) { in ucc_get_tdm_tx_clk()
411 switch (clock) { in ucc_get_tdm_tx_clk()
423 switch (clock) { in ucc_get_tdm_tx_clk()
435 switch (clock) { in ucc_get_tdm_tx_clk()
447 switch (clock) { in ucc_get_tdm_tx_clk()
459 switch (clock) { in ucc_get_tdm_tx_clk()
471 switch (clock) { in ucc_get_tdm_tx_clk()
487 /* tdm_num: TDM A-H port num is 0-7 */
489 enum qe_clock clock) in ucc_get_tdm_rxtx_clk() argument
493 clock_bits = ucc_get_tdm_common_clk(tdm_num, clock); in ucc_get_tdm_rxtx_clk()
497 clock_bits = ucc_get_tdm_rx_clk(tdm_num, clock); in ucc_get_tdm_rxtx_clk()
499 clock_bits = ucc_get_tdm_tx_clk(tdm_num, clock); in ucc_get_tdm_rxtx_clk()
509 shift -= tdm_num * 4; in ucc_get_tdm_clk_shift()
511 shift -= (tdm_num - 4) * 4; in ucc_get_tdm_clk_shift()
516 int ucc_set_tdm_rxtx_clk(u32 tdm_num, enum qe_clock clock, in ucc_set_tdm_rxtx_clk() argument
524 qe_mux_reg = &qe_immr->qmx; in ucc_set_tdm_rxtx_clk()
527 return -EINVAL; in ucc_set_tdm_rxtx_clk()
531 return -EINVAL; in ucc_set_tdm_rxtx_clk()
533 clock_bits = ucc_get_tdm_rxtx_clk(mode, tdm_num, clock); in ucc_set_tdm_rxtx_clk()
535 return -EINVAL; in ucc_set_tdm_rxtx_clk()
539 cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l : in ucc_set_tdm_rxtx_clk()
540 &qe_mux_reg->cmxsi1cr_h; in ucc_set_tdm_rxtx_clk()
548 static int ucc_get_tdm_sync_source(u32 tdm_num, enum qe_clock clock, in ucc_get_tdm_sync_source() argument
551 int source = -EINVAL; in ucc_get_tdm_sync_source() local
553 if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) { in ucc_get_tdm_sync_source()
554 source = 0; in ucc_get_tdm_sync_source()
555 return source; in ucc_get_tdm_sync_source()
557 if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) { in ucc_get_tdm_sync_source()
558 source = 0; in ucc_get_tdm_sync_source()
559 return source; in ucc_get_tdm_sync_source()
565 switch (clock) { in ucc_get_tdm_sync_source()
567 source = 1; in ucc_get_tdm_sync_source()
570 source = 2; in ucc_get_tdm_sync_source()
578 switch (clock) { in ucc_get_tdm_sync_source()
580 source = 1; in ucc_get_tdm_sync_source()
583 source = 2; in ucc_get_tdm_sync_source()
591 switch (clock) { in ucc_get_tdm_sync_source()
593 source = 1; in ucc_get_tdm_sync_source()
596 source = 2; in ucc_get_tdm_sync_source()
604 switch (clock) { in ucc_get_tdm_sync_source()
606 source = 1; in ucc_get_tdm_sync_source()
609 source = 2; in ucc_get_tdm_sync_source()
617 return source; in ucc_get_tdm_sync_source()
625 shift -= tdm_num * 2; in ucc_get_tdm_sync_shift()
630 int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock, in ucc_set_tdm_rxtx_sync() argument
633 int source; in ucc_set_tdm_rxtx_sync() local
637 qe_mux_reg = &qe_immr->qmx; in ucc_set_tdm_rxtx_sync()
640 return -EINVAL; in ucc_set_tdm_rxtx_sync()
644 return -EINVAL; in ucc_set_tdm_rxtx_sync()
646 source = ucc_get_tdm_sync_source(tdm_num, clock, mode); in ucc_set_tdm_rxtx_sync()
647 if (source < 0) in ucc_set_tdm_rxtx_sync()
648 return -EINVAL; in ucc_set_tdm_rxtx_sync()
652 qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr, in ucc_set_tdm_rxtx_sync()
654 source << shift); in ucc_set_tdm_rxtx_sync()